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Gate Level Design of a Digital Clock with Asynchronous- Synchronous Logic

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 Global Journal of researches in engineering
Electrical and electronics engineering
Volume 12 Issue 4 Version 1.0 March 2012
Type: Double Blind Peer Reviewed International Research Journal
Publisher: Global Journals Inc. (USA)
Online ISSN: 2249-4596 & Print ISSN: 0975-5861

Gate Level Design of a Digital Clock with Asynchronous-

Synchronous Logic
By Sheikh Md. Rabiul Islam & Md. Jobayer Hossain
Khulna University of Engineering and Technology, Bangladesh
Abstract - A digital clock has been designed at gate level and is being presented in this paper.
The clock architecture consists of three major blocks SECOND,MINUTE and HOUR. The
architecture is the amalgam both of synchronous and asynchronous logic. All the flip-flops at
each block run synchronously. The triggering operation of a block is asynchronous in nature. It
serves the design requiring lower power consumption, provides lesser noise and
electromagnetic interference, lower delay and greater throughput. The clock is designed at Xilinx
System Generator, synthesized with Xilinx Synthesis Tool (XST) and Simulated by Vegilogger Pro
6.5.
Keywords : Counter, asynchronous counter, synchronous counter, system level design, gate
level design, GALS.
GJRE-F Classification : FOR Code: 090601

Gate Level Design of a Digital Clock with Asynchronous-Synchronous Logic

Strictly as per the compliance and regulations of:

© 2012 Sheikh Md. Rabiul Islam & Md. Jobayer Hossain.This is a research/review paper, distributed under the terms of the
Creative Commons Attribution-Noncommercial 3.0 Unported License http://creativecommons.org/licenses/by-nc/3.0/), permitting
all non commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.
 Gate Level Design of a Digital Clock with
Asynchronous-Synchronous Logic
Sheikh Md. Rabiul Islam Į & Md. Jobayer Hossain Į

Abstract - A digital clock has been designed at gate level and synchronous circuit [13] is a digital circuit in which the
is being presented in this paper. The clock architecture parts are synchronized by a single clock signal. In an

March 2012
consists of three major blocks SECOND,MINUTE and HOUR. ideal synchronous circuit, every change in the logical
The architecture is the amalgam both of synchronous and levels of its storage components is simultaneous. These
asynchronous logic. All the flip-flops at each block run
transitions follow the level change of a special clock
synchronously. The triggering operation of a block is
asynchronous in nature. It serves the design requiring lower signal. Ideally, the input to each storage element has
power consumption, provides lesser noise and reached its final value before the next clock occurs, so
electromagnetic interference, lower delay and greater the behavior of the whole circuit can be predicted 17
throughput. The clock is designed at Xilinx System Generator, exactly. Practically, some delay is required for each
synthesized with Xilinx Synthesis Tool (XST) and Simulated by logical operation, resulting in a maximum speed at

IV Version I
Vegilogger Pro 6.5. which each synchronous system can run [13]. Thus in a
Keywords : Counter, asynchronous counter, synchronous counter [7] all the flip-flops are clocked
synchronous counter, system level design, gate level simultaneously. The decision whether a flip-flop is to be
design, GALS. complemented or not is determined from the values of

F ) Volume XII Issue v

the T inputs at the time of pulse. If T=0, the flip-flop
I. INTRODUCTION remains unchanged. If T=1, the flip flop complements.

A
digital clock is a type of clock that displays the Thus the states of the counters get changed.
time digitally. Instead of the rotary mechanism of Synchronous logic suffers from some disadvantages: As
electromechanical clock, it uses digital counters the clock is usually a high-frequency signal, this
that count second, minute and hours. Each sixty distribution consumes a relatively large amount of power
seconds make a minute and each sixty minutes an hour. and dissipates much heat. Even the flip-flops that are
After twenty four hours the clock resets and starts from doing nothing consume a small amount of power,

Global Journal of Researches in Engineering ( D

initial condition. The functional unit of a digital clock is a thereby generating waste heat in the chip [12]. Again
counter that represents a second, minute or hour block. the maximum possible clock rate is determined by the
A counter [7] may be defined as a register i.e. a group slowest logic path in the circuit, otherwise known as the
of flip-flops that goes through a predetermined critical path. This means that every logical calculation,
sequence of states upon the application of input pulses. from the simplest to the most complex, must complete
The logic gates in a counter are connected in such a in one clock cycle. In spite of these drawbacks
way as to produce a prescribed sequence of binary synchronous counters are more suited for some
states in the register. reasons.
There are two types of input/output (I/O) At an asynchronous counter [11], [14] the
synchronization technique to design a counter [10]: output of any flip-flop (except the first) depends solely
synchronous and asynchronous technique. In an upon the output of the previous T flip-flop. Due to the RC
asynchronous counter, the flip-flop output transition time delay at each transistor there occurs a large
serves as a source for triggering other flip-flops. In aggregation of delay time after several flip-flops [8]. So
otherwords, the CP inputs of all flip-flops (except the to design asynchronous counter is impractical. For this
first) are triggered not only by the incoming pulses but reason synchronous logic has been adopted to
rather by the transitions that occur in other flip-flops. The construct counter blocks. In addition to this the
asynchronous counter is also referred to as overlapped synchronous technique serves greater throughput and
counter. A problem [7] in designing an asynchronous much lower overhead for its design simplicity [9].
logic is that it cannot be described by Boolean In the way to integrated circuit implementation
equations developed for describing clocked sequential process way can notice two major steps [3]: Design
circuits. Again as output of one flip-flop acts as the input stage and fabrication stage. Design stage includes
of another one, the system designed at asynchronous system design, logic design and mask layout
logic faces considerable delay. On the other hand, a preparation. At the system level design [4] the
architecture is checked against the system specification
to ensure that all required hardware features and data
Author Į : Dept. of Electronics and Communication Engineering
Khulna University of Engineering and Technology,Bangladesh. paths have been included. At the next level of hierarchy,
E-mail : [email protected], [email protected] the architectural blocks are expanded into logic
© 2012 Global Journals Inc. (US)
 Gate Level Design of a Digital Clock with Asynchronous-Synchronous Logic

diagrams. In this stage the whole system is transferred III. MODEL DEVELOPMENT
into aggregation of registers [9]. Here each item
represents a particular logic function. If that particular There are three asynchronously operating
logic functions are represented by logic gates such as blocks at the architectural design of the digital clock. But
AND, OR or XOR, then it is called Gate level design [6]. flip-flops at each block are energised synchronously.
Gate level design realizes intensive aggregation of The SECOND and MINUTE block have six T flip-flops
elements at much lower area. To solve the problems each. When they operate synchronously they are
associated both with synchronous and asynchronous projected to have 64 distinct states. But we want them
logic the author adopted a recently emerged logic to go to their primary state after counting 60 states. So
structure GALS [1], [2]. Globally Asynchronous Locally we need to modify the input and output relationships of
Synchronous logic is the amalgam of the two logics. It flip-flops. Representing the input as Ta, Tb, Tc etc and
not only removes the drawbacks but also provides more A, B, C etc for flip-flops a, b, c respectively as shown in
March 2012

advantages [16]. The advantages include lower power Fig.2, the relations for SECOND and MINUTE blocks
consumption and electromagnetic interferences. are:
Ta=BCEF (A’D+AD’)
II. OVERVIEW OF THE ARCHITECTURE
Tb= ABCD’EF+CDEF (A’+B')
18 The digital clock designed as shown in Fig.1 Tc =ABEFCD’+ DEF (A’+B’+C’)
assumes three functional blocks: second, minute and
Td=EF (A’+C’+B’)
hour. The second and minute block count from 0 to 59.
Global Journal of Researches in Engineering ( FD ) Volume XII Issue vIV Version I

So six T flip-flops are required to construct either second Te= F (A’+B’+C’+D’)

or minute block (2^6=64). The hour block counts from Tf =1
0 to 23. So it requires five T flip-flops (2^5=32). Similarly we want to make the flip-flops of
HOUR block to go to its primary state after counting 24
states instead of 32 states. For this case the input-
output relationships of the flip-flops are simplified as
follows:
Ta= CDE (A’B+AB’)
Tb=A’CDE
Tc=DE (A’+B’)
Td=E (A’+B’)
Te=1
Thus in the designed architecture sixty seconds
Fig.1 : simplified architecture of the design clock.
make a minute and sixty minute an hour. After twenty
four hour the clock resets and starts counting from initial
The flip-flops inside a block (second, minute or states at another day. It is customary to keep a RESET
hour) run simultaneously as they are triggered by same button so that the user can reset the clock at any time.
clock pulse. But the clock pulse of minute block is a
function of the outputs of the second block. Again the IV. OPERATION
clock pulse of the hour block is also a function of the
The individual block of the design is an
outputs of the minute block. So the block to block
aggregate of several synchronous binary counters.
logical relation is asynchronous in nature. Thus the
Therefore, the flip-flop in the lowest order position is
design architecture is a combination both of
complemented with every pulse. This means that its T
asynchronous and synchronous logic.
input must be maintained at logic 1. A flip flop in any
other position is complemented with a pulse provided all
the bits in the lower order positions are equal to 1. As
the input functions T’s of the flip flops are configured,
after the desired sequence (111011 for second and
minute block) comes, all the outputs of the flip flops will
be 0.
When the second block reaches to 59 (111011
in binary), all the flip flops of this second block resets.
Then clock signal of minute block becomes 1. As Tfm
=1 now logically, minute block state is increased by one
at the next clock pulse. Thus each time second block
faces state 111011, minute increases by one. The same
Fig.2 : Logic diagram of SECOND and MINUTE block thing occurs from minute to hour interaction. After
© 2012 Global Journals Inc. (US)
 Gate Level Design of a Digital Clock with Asynchronous-Synchronous Logic

counting 23 hour (10111), 59 minute and 59 seconds all

the flip-flops resets. As shown in Fig.3. Flow chart
explaining the operation of digital clock.

March 2012
19
Fig. 6(a) : RTL Design hierarchy

IV Version I
F ) Volume XII Issue v
Fig.3 : Flowchart explaining the operation of digital Fig. 6(b) : Gate level logic diagram showing net _n0068

Global Journal of Researches in Engineering ( D

clock.

V. SYNTHESIS
The model is designed at Xilinx System
Generator. Then it is synthesized with Xilinx Synthesis
Tool (XST) as shown in Fig.4&5.
The outcomes include a IC package with two
input ports:: RESET and CLOCK PULSE and seventeen
output ports. The RTL(Register Transfer Level)
schematic of the design is provided as in
Fig.6(a),(b),(c)&(d).It assembles logic gates which meet
the systems requirements [6]. The details description of Fig.6(c) : Gate level representation of block FDRE.
Pin numbers for the design of clock is given in Table.1.

Fig.4 : RTL schematic diagrams found from XST (system

level).
© 2012 Global Journals Inc. (US)
 Gate Level Design of a Digital Clock with Asynchronous-Synchronous Logic

Table.1 : Detail Description of the Pin Number Specification

Pin type Pin Pin Description Function
name no.
Input clk, 1,2 Single bit clk is the line with input
reset binary signal period=1second
resets resets the clock to
zero state
Output ah,bh,ch, 3,6,9,12, Single bit Pins that jointly show time in
(Hour block) dh,eh 15, binary hour
Output am,bm,c 4,7,10,13, Single bit Pins that jointly show time in
(Minute block) m,dm, 16,18 binary minute
March 2012

em,fm
Output as,bs,cs,d 5,8,11,14, Single bit Pins that jointly show time in
(Second block s,es,fs 17,19 binary second

20 VII. LIMITATIONS
The digital clock that is designed can count
Global Journal of Researches in Engineering ( FD ) Volume XII Issue vIV Version I

seconds, minutes and hours only. But at the real world

people are not satisfied at this. They are interested in
having notified other information such as date, month,
year etc. It is also expected that the clock will serve
some other facilities such as alarm, reminder etc. These
features can be added just extending the design a little
Fig.6(d) : Gate level logic diagram forming clkh signal. bit further. Again the design includes lesser number of
gates. So it will be cost-inefficient to design on an entire
chip. The author wishes to design a complete package
A few portion of the total gate level of digital clock at the near future that will overcome the
representation is demonstrated in Fig.6(b), 6(c) and remaining drawbacks.
6(d). It shows that all the components of the RTL
schematic diagram are at gate level including AND, OR, VIII. CONCLUSION
INVERTER, XOR etc both at single and multiple inputs.
The figure clearly demonstrates the interrelation among Logic gate level design of a digital clock has
inputs and outputs. been presented. The design comprises the amalgam of
synchronous and asynchronous techniques to attain its
VI. SIMULATION purpose. The Gate level design realizes intensive
aggregation of components at smaller size of the chip.
The simulation of the design was run at
Again the combinational structure assumes lower power
verilolgger pro 6.5. The result was the exact replica of
requirement, electromagnetic interference and greater
our expectation. From the timing diagram at Fig.7 we
throughput. The designed structure was synthesized
can notice that initially all the flip-flops are at initial state
using XST and simulated at verilogger pro 6.5. The
(zero state) when RESET is at state 0. The rest part of
design was successfully loaded at Xilinx FPGA device,
the circuitry remains inactive until RESET is at state 1.
MDA-ASIC2 (XC25150). In spite of having some
When RESET is at state 1 the flip-flops are allowed to
limitations the design has been found to be useful
follow counting. The state of SECOND block changes as enough.
000000, 000001, 000010, 000011 and so on. When it
reaches state 111011 (i.e. 59 in decimal), a clock pulse References Références Referencias
goes to MINUTE block and its state changes from
000000 to 000001 and the SECOND block starts 1. A. Hemaini, T. Meincke, S. Kumar, A. Postula, T.
counting again from 000000 state. Thus after 60 minutes Olsson, P. Nilson, J. Oberrg, P. Ellervee, ”Lowering
when state 111011 appears at MINUTE block it resets Power Consumpsion in Clock by using Globally
and the state of HOUR block changes from 00000 to Asynchronous Locally Synchronous Design Style”.
00001. After counting 23 hour 59 minutes and 59 DAC 99, New Orleans, Louisiana (c) 1999 ACM 1-
seconds, all the flip flops of the system get reseted (i.e. 58113-109-7/99/06.
zero state) when the next clock pulse appears at the 2. Jonas Carlson, Kent Palmnvist, Lars Wanhammar,
SECOND block. “Synchronous Design Flow for Globally
Asynchronous Locally Synchronous Systems”.
www.es.isy.liu.se/publications/papers

© 2012 Global Journals Inc. (US)

 Gate Level Design of a Digital Clock with Asynchronous-Synchronous Logic

3. F.E. Barber, T. J. Bartoli, R. L. Freyman, J.A. Grand, Chen-han Tsai, Chih-hao-Chao, Xin_Yu Shi, Bo-
J. Kane and Kershaw, “An Overview of the Silicon Yuan Peng and Bo-Yuan Peng.
Very-Large-Scale-Integration Implementation”. 7. M. Moris Mano, Digital Logic and Computer design.
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12. en. wikipedia.org/wiki/Sequential logic
5. Mark E. Dean, David L.Dill and Mark Horowitz, “Self 13. en. wikipedia.org/wiki/Synchronous_circuit
Timed Logic using Current-Sensing Completion 14. en. wikipedia.org/wiki/asynchronous _circuit
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Global Journal of Researches in Engineering ( D

Fig.5 : RTL schematic diagrams found from XST (showing block level)

© 2012 Global Journals Inc. (US)

March 2012 Gate Level Design of a Digital Clock with Asynchronous-Synchronous Logic

22
Global Journal of Researches in Engineering ( FD ) Volume XII Issue vIV Version I

Fig.7 : Timing diagram simulated at Test bench.

© 2012 Global Journals Inc. (US)

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