Lab Record

Digital Electronics and Computer

Organisation (CSE207)

DEPARTMENT OF INFORMATION TECHNOLOGY

AMITY SCHOOL OF ENGINEERING AND TECHNOLOGY
AMITY UNIVERSITY UTTAR PRADESH

3rd Semester,
July-December 2020

By
Faculty: ……………..
……………. ………………
……………….

1
 INDEX
S.N Category of Cod Experimen Name of Date of Date of Max. Marks Signatur
o Assignment e t No. Experiment Allotment Evaluatio obtaine e of
Mark
of n d Faculty
s
experimen
t

1. Mandatory LR 1 TO SIMULATE 21/07/20 1

Experiment (10) BASIC GATES.

2. Mandatory 2 TO SIMULATE 28/07/20 1

Experiment HALF ADDER.

3. Mandatory 3 TO SIMULATE FULL 04/08/20 1

Experiment ADDER.

4. Mandatory 4 TO SIMULATE THE 11/08/20 1

Experiment LOGICAL PART OF
A SIMPLE
ARITHMETIC
LOGICAL UNIT.

5. Mandatory 5 TO SIMULATE A 4- 18/08/20 1

Experiment BIT BINARY
ADDER-
SUBTRACTOR
CIRCUIT.

6. Mandatory 6 SIMULATION OF 25/08/20 1

Experiment ONE-DIGIT BCD
ADDER.

7. Mandatory 7 TO SIMULATE AND 01/09/20 1

Experiment STUDY THE
TRISTATE BUFFER.

8. Mandatory 8 TO SIMULATE THE 15/09/20 1

Experiment COMMON BUS
USING TRI-STATE
BUFFERS AND
DECODER.

9. Mandatory 9 TO SIMULATE 21/09/20 1

2
 Experiment COMMON BUS
USING
MULTIPLEXER.

10. Mandatory 10 STUDY OF 8085 13/10/20 1

Experiment MICROPROCESSOR
.
11. Mandatory 11 STUDY OF 13/10/20
Experiment INSTRUCTION SET
OF 8085.

12. NON- 12 TO STUDY & 11/08/20

Mandatory VERIFY HALF AND
Experiment FULL SUBTRACTOR
13. NON- 13 TO SIMULATE THE 28/09/20
Mandatory 8:3 ENCODER AND
Experiment 8:3 PRIORITY
ENCODER

14. NON- 14 TO SIMULATE THE 03/10/20

Mandatory 1-BIT AND 2-BIT
Experiment COMPARATOR
CIRCUIT

15. Design Based PR 10

Open Ended (10)
experiment*
*

16. Viva Viva 5

(5)

3
 Experiment – 1
Objective  To interpret, implement and verify the logic and truth table for AND, OR, NOT, NAND,
NOR, Ex-OR, Ex-NOR.

Software Used: Circuit Verse and Virtual Labs.

Theory:

Logic gates are the basic building blocks of any digital system. Logic gates are electronic circuits having
one or more than one input and only one output. The relationship between the input and the output is
based on certain logic. Based on this, logic gates are named as

1) AND gate
2) OR gate
3) NOT gate
4) NAND gate
5) NOR gate
6) Ex-OR gate
7) Ex-NOR gate

1) AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is
used to show the AND operation i.e. A.B or can be written as AB

Y= A.B

Figure-1: Logic Symbol of AND Gate

4
 Figure-2:Truth Table of AND Gate

2) OR gate

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A
plus (+) is used to show the OR operation.

Y= A+B

Figure-4:Logic Symbol of OR Gate

Figure-5:Truth Table of OR Gate

5
3) NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also
known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also
shown as A' or A with a bar over the top, as shown at the outputs.

Y= A'

Figure-7:Logic Symbol of NOT Gate

Figure-8:Truth Table of NOT Gate

4) NAND gate

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all
NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the
output. The small circle represents inversion.

Y= AB

6
 Figure-10:Logic Symbol of NAND Gate

Figure-11:Truth Table of NAND Gate

5) NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR
gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output.
The small circle represents inversion.

Y= A+B

Figure-13:Logic Symbol of NOR gate

7
 Figure-14:Truth Table of NOR gate

6) Ex-OR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its two inputs
are high. An encircled plus sign (⊕) is used to show the Ex-OR operation.

Y= A⊕B

Figure-16:Logic Symbol of Ex-OR gate

Figure-17:Truth Table of Ex-OR gate

8
7) Ex-NOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output if either,
but not both of its two inputs are high. The symbol is an EX-OR gate with a small circle on the output.
The small circle represents inversion.

Y= A⊕B

Figure-19: Logic Symbol of Ex-NOR gate

Figure-20:Truth Table of Ex-NOR gate

Implementation:
OR, AND and NOT Gates:

9
10
NAND and NOR Gates:

11
Ex OR and Ex NOR Gates:

12
13
Result:
OR, AND and NOR Gates:

NAND and NOR Gates:

14
Ex OR and Ex NOR Gates:

15
 Conclusion  Hence, we interpret, implement and verify the logic and truth table for AND, OR,
NOT, NAND, NOR, Ex-OR, Ex-NOR.

Precautions:
1. Make sure that the circuit is connected properly.
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

16
 Experiment – 2
Objective  To simulate and verify Half Adder circuit using NAND and NOR gates.
Software Used – Circuit Verse and Virtual Lab.
Theory:
Adders are digital circuits that carry out addition of numbers. Adders are a key component of arithmetic
logic unit. Adders can be constructed for most of the numerical representations like Binary Coded
Decimal (BDC), Excess – 3, Gray code, Binary etc. out of these, binary addition is the most frequently
performed task by most common adders. Apart from addition, adders are also used in certain digital
applications like table index calculation, address decoding etc.

Binary addition is similar to that of decimal addition. Some basic binary additions are shown below.

Schematic representation of half adder

Half Adder

Half adder is a combinational circuit that performs simple addition of two binary numbers. The block
diagram of a half adder is shown below.

Half Adder Truth Table

If we assume A and B as the two bits whose addition is to be performed, a truth table for half adder with
A, B as inputs and Sum, Carry as outputs can be tabulated as follows.

The sum output of the binary addition carried out above is similar to that of an Ex-OR operation while the
carry output is similar to that of an AND operation. The same can be verified with help of Karnaugh Map.

17
    

The truth table and K Map simplification for sum output is shown below.

   

18
    

Sum = A B' + A' B

The truth table and K Map simplification for carry is shown below.

      

   
Carry = AB

19
If A and B are binary inputs to the half adder, then the logic function to calculate sum S is Ex – OR of A
and B and logic function to calculate carry C is AND of A and B. Combining these two, the logical circuit
to implement the combinational circuit of half adder is shown below.

Half Adder Logic Diagram

As we know that NAND and NOR are called universal gates as any logic system can be implemented
using these two, the half adder circuit can also be implemented using them. We know that a half adder
circuit has one Ex – OR gate and one AND gate.

Half Adder using NAND gates

Five NAND gates are required in order to design a half adder. The circuit to realize half adder using
NAND gates is shown below.

Realization of half adder using NAND gates

Half Adder using NOR gates

20
Five NOR gates are required in order to design a half adder. The circuit to realize half adder using NOR
gates is shown below.

Realization of half adder using NOR Gates

Implementation:
Half Adder:

21
Half Adder Using NAND Gate:

22
23
Half Adder Using NOR Gate:

24
Result:
Half Adder:

25
Half Adder Using NAND Gate:

Half Adder Using NOR Gate:

26
Conclusion  Hence, we simulate and verify Half Adder circuit using NAND and NOR gates.
Precautions:
1. Make sure that the circuit is connected properly.
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

27
 Experiment – 3
Objective  To simulate and verify Full Adder Circuit using gates and half adder.
Software Used – Circuit Verse and Virtual Labs.
Theory:
Adders are digital circuits that carry out addition of numbers. Adders are a key component of arithmetic
logic unit. Adders can be constructed for most of the numerical representations like Binary Coded
Decimal (BDC), Excess – 3, Gray code, Binary etc. out of these, binary addition is the most frequently
performed task by most common adders. Apart from addition, adders are also used in certain digital
applications like table index calculation, address decoding etc

Full Adder

Full adder is a digital circuit used to calculate the sum of three binary bits which is the main difference
between full adder and half adder. Full adders are complex and difficult to implement when compared to
half adders. Two of the three bits are same as before which are A, the augend bit and B, the addend bit.
The additional third bit is carry bit from the previous stage and is called 'Carry' – in generally represented
by CIN. It calculates the sum of three bits along with the carry. The output carry is called Carry – out and
is represented by COUT.

The block diagram of a full adder with A, B and CIN as inputs and S, COUT as outputs is shown below.

 
Full Adder Block Diagram and Truth Table

28
Based on the truth table, the Boolean functions for Sum (S) and Carry – out (COUT) can be derived using
K – Map.

 
The simplified equation for sum is S = A'B'Cin + A'BCin' + ABCin
The simplified equation for COUT is COUT = AB + ACIN + BCIN
In order to implement a combinational circuit for full adder, it is clear from the equations derived above,
that we need four 3-input AND gates and one 4-input OR gates for Sum and three 2-input AND gates and
one 3-input OR gate for Carry – out.

Full Adder Logic Diagram

Full Adder using NAND gates

As mentioned earlier, a NAND gate is one of the universal gates and can be used to implement any logic
design. The circuit of full adder using only NAND gates is shown below.

29
 Full Adder using NAND gates

Full Adder using NOR gates

As mentioned earlier, a NOR gate is one of the universal gates and can be used to implement any logic
design. The circuit of full adder using only NOR gates is shown below.

Full Adder using NOR gates

Implementation:
Full Adder:

30
31
32
Full Adder Using Half Adder:

33
34
35
Result:
Full Adder:

36
Full Adder Using Half Adder:

37
Conclusion  Hence, we simulate and verify Full Adder Circuit using gates and half adder.
Precautions:
1. Make sure that the circuit is connected properly.
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

38
Performance (C) 2

Total 6 (To be scaled down to 1)

39
 Experiment 4

Objective: To simulate the logical part of a simple Arithmetic logical Unit.

Software Used: Circuit Verse and Virtual Labs.

Theory:
Introduction
Inside a computer, there is an Arithmetic Logic Unit (ALU), which is capable of performing
logical operations (e.g. AND, OR, Ex-OR, Invert etc.) in addition to the arithmetic operations
(e.g. Addition, Subtraction etc.). The control unit supplies the data required by the ALU from
memory, or from input devices, and directs the ALU to perform a specific operation based on the
instruction fetched from the memory. ALU is the “calculator” portion of the computer.

Fig 1. ALU
An arithmetic logic unit(ALU) is a major component of the central processing unit of the a
computer system. It does all processes related to arithmetic and logic operations that need to be
done on instruction words. In some microprocessor architectures, the ALU is divided into the
arithmetic unit (AU) and the logic unit (LU).
An ALU can be designed by engineers to calculate many different operations. When the
operations become more and more complex, then the ALU will also become more and more
expensive and also takes up more space in the CPU and dissipates more heat. That is why
engineers make the ALU powerful enough to ensure that the CPU is also powerful and fast, but
not so complex as to become prohibitive in terms of cost and other disadvantages.

40
ALU is also known as an Integer Unit (IU). The arithmetic logic unit is that part of the CPU that
handles all the calculations the CPU may need. Most of these operations are logical in nature.
Depending on how the ALU is designed, it can make the CPU more powerful, but it also
consumes more energy and creates more heat. Therefore, there must be a balance between how
powerful and complex the ALU is and how expensive the whole unit becomes. This is why faster
CPUs are more expensive, consume more power and dissipate more heat.
Different operation as carried out by ALU can be categorized as follows –
 logical operations − These include operations like AND, OR, NOT, XOR, NOR,
NAND, etc.

Fig. 2 – One Stage logic circuit

 Bit-Shifting Operations − This pertains to shifting the positions of the bits by a certain
number of places either towards the right or left, which is considered a multiplication or
division operations.
 Arithmetic operations − This refers to bit addition and subtraction. Although
multiplication and division are sometimes used, these operations are more expensive to

41
 make. Multiplication and subtraction can also be done by repetitive additions and
subtractions, respectively.

Circuit Implementation:

1) Logical part of ALU using MUX

2) Logical part of ALU using Decoder

42
Result:

1) Logical part of ALU using MUX:

2)Logical part of ALU using Decoder:

Conclusion:
Hence, we can simulate the logical part of a simple Arithmetic logical Unit.

Precautions:
1. Make sure that the circuit is connected properly.
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

43
 Experiment 5

Objective: To simulate a 4-bit binary adder-subtractor circuit.

Software Used: Circuit Verse and Virtual Labs.

Theory:
Introduction
In Digital Circuits, A Binary Adder-Subtractor is one which is capable of both addition and
subtraction of binary numbers in one circuit itself. The operation being performed depends upon
the binary value the control signal holds. It is one of the components of the ALU (Arithmetic
Logic Unit).
This Circuit Requires prerequisite knowledge of Exor Gate, Binary Addition and Subtraction,
Full Adder.

Lets consider two 4-bit binary numbers A and B as inputs to the Digital Circuit for the operation
with digits
A0 A1 A2 A3 for A
B0 B1 B2 B3 for B
The circuit consists of 4 full adders since we are performing operation on 4-bit numbers. There is
a control line K that holds a binary value of either 0 or 1 which determines that the operation
being carried out is addition or subtraction.

Fig 1. 4-bit Adder-subtractor circuit

44
As shown in the figure, the first full adder has control line directly as its input(input carry C0),
The input A0 (The least significant bit of A) is directly input in the full adder. The third input is
the exor of B0 and K (S in fig But do not confuse it with Sum-S). The two outputs produced are
Sum/Difference (S0) and Carry (C1).
If the value of K (Control line) is 1, th output of B0(exor)K=B0′(Complement B0). Thus the
operation would be A+(B0′). Now 2’s complement subtraction for two numbers A and B is given
by A+B’. This suggests that when K=1, the operation being performed on the four bit numbers is
subtraction.
Similarly If the Value of K=0, B0 (exor) K=B0. The operation is A+B which is simple binary
addition. This suggests that When K=0, the operation being performed on the four bit numbers is
addition.
Then C0 is serially passed to the second full adder as one of it’s outputs. The sum/difference S0
is recorded as the least significant bit of the sum/difference. A1, A2, A3 are direct inputs to the
second, third and fourth full adders. Then the third input is the B1, B2, B3 EXORed with K to
the second, third and fourth full adder respectively. The carry C1, C2 are serially passed to the
successive full adder as one of the inputs. C3 becomes the total carry to the sum/difference. S1,
S2, S3 are recorded to form the result with S0.

Circuit Implementation:

45
Result:

Conclusion:
Hence, we can simulate 4-bit binary adder-subtractor circuit.

Precautions:
1.Make sure that the circuit is connected properly.

46
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

47
 Experiment 6

Objective: Simulation of one-digit BCD Adder.

Software Used: Circuit Verse and Virtual Labs.

Theory:
Introduction
BCD stand for binary coded decimal. Suppose we have two 4-bit numbers A and B. The value of A and B
can vary from 0(0000 in binary) to 9(1001 in binary) because we are considering decimal numbers.

Fig 1. BCD Adder

The output will vary from 0 to 18, if we are not considering the carry from the previous sum. But if we
are considering the carry, then the maximum value of output will be 19 (i.e. 9+9+1 = 19).
When we are simply adding A and B, then we get the binary sum. Here, to get the output in BCD form,
we will use BCD Adder.
If the sum of two number is less than or equal to 9, then the value of BCD sum and binary sum will be
same otherwise they will differ by 6(0110 in binary).
Now, lets move to the table and find out the logic when we are going to add “0110”.

48
 Fig 2. Truth table of BCD Adder
We are adding “0110” (=6) only to the second half of the table.
The conditions are:
1. If C’ = 1 (Satisfies 16-19)
2. If S3′. S2′ = 1 (Satisfies 12-15)
3. If S3′. S1′ = 1 (Satisfies 10 and 11)
So, our logic is
C' + S3'. S2' + S3'.S1' = 1
Implementation:

Fig 3. 4-bit BCD adder circuit implementation

49
Circuit Implementation:

Result:

50
Conclusion:
Hence, we can simulate one-digit BCD adder.

Precautions:
1.Make sure that the circuit is connected properly.
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

51
 Experiment 7

Objective: To simulate and study the tristate buffer.

Software Used: Circuit Verse and Virtual Labs.

Theory:
Introduction
As well as the standard Digital Buffer seen above, there is another type of digital buffer circuit whose
output can be “electronically” disconnected from its output circuitry when required. This type of Buffer is
known as a 3-State Buffer or more commonly a Tri-state Buffer.
A Tri-state Buffer can be thought of as an input controlled switch with an output that can be electronically
turned “ON” or “OFF” by means of an external “Control” or “Enable” ( EN ) signal input. This control
signal can be either a logic “0” or a logic “1” type signal resulting in the Tri-state Buffer being in one
state allowing its output to operate normally producing the required output or in another state were its
output is blocked or disconnected.

Then a tri-state buffer requires two inputs. One being the data input and the other being the enable or
control input as shown.

Tri-state Buffer Switch Equivalent

When activated into its third state it disables or turns “OFF” its output producing an open circuit
condition that is neither at a logic “HIGH” or “LOW”, but instead gives an output state of very high
impedance, High-Z, or more commonly Hi-Z. Then this type of device has two logic state inputs, “0” or a
“1” but can produce three different output states, “0”, “1” or ” Hi-Z ” which is why it is called a “Tri” or
“3-state” device.

52
Note that this third state is NOT equal to a logic level “0” or “1”, but is an high impedance state in which
the buffers output is electrically disconnected from the rest of the circuit. As a result, no current is drawn
from the supply.
There are four different types of Tri-state Buffer, one set whose output is enabled or disabled by an
“Active-HIGH” control signal producing an inverted or non-inverted output, and another set whose buffer
output is controlled by an “Active-LOW” control signal producing an inverted or non-inverted output as
shown below.

Circuit Implementation:

53
Result:

Conclusion:
Hence, we can simulate the tristate buffer.

Precautions:
1.Make sure that the circuit is connected properly.
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

54
 Experiment 8

Objective: To simulate the common bus using tri-state buffers and decoder.

Software Used: Circuit Verse and Virtual Labs.

Theory:
Introduction

A bus system can be constructed with three-state gates instead of multiplexers. A three-state gate is a
digital circuit that exhibits three states. Two of the states are signals equivalent to logic 1 and 0 as in a
conventional gate. The third state is a high-impedance state. The high-impedance state behaves like an
open circuit, which means that the output is disconnected and does not have a logic significance. Three-
state gates may perform any conventional logic, such as AND or NAND. However, the one most used in
the design of a bus system is the buffer gate.

The graphic symbol of a three-state buffer gate is shown in fig. It is distinguished from a normal buffer
by having both a normal input and a control input. The control input determines the output state. When
the control input is equal to 1, the output is enabled and the gate behaves like any conventional buffer,
with the output equal to the normal input. When the control input is 0, the output is disabled and the gate
goes to a high-impedance state, regardless of the value in the normal input. The high-impedance state of
a three-state gate provides a special feature not available in other gates. Because of this feature, a large
number of three-state gate outputs can be connected with wires to form a common bus line without
endangering loading effects.

55
The construction of a bus system with three-state buffers is demonstrated in Fig. The outputs of four
buffers are connected to form a single bus line. (It must be realized that this type of connection cannot be
done with gates that do not have three-state outputs.) The control inputs to the buffers determine which
of the four normal inputs will communicate with the bus line. No more than one buffer may be in the
active state at any given time. The connected buffers must be controlled so that only one three-state
buffer has access to the bus line while all other buffers are maintained in a high impedance state.

One way to ensure that no more than one control input is active at any given time is to use a decoder, as
shown in the diagram. When the enable input of the decoder is 0, all its four outputs are 0, and the bus
line is in a high-impedance state because all four buffers are disabled. When the enable input is active,
one of the three-state buffers will be active, depending on the binary value in the select inputs of the
decoder. Careful investigation will reveal that Fig. is another way of constructing a 4 x 1 multiplexer

Circuit Implementation:

Result:
56
Conclusion:
Hence, we can simulate common bus using tristate buffer and decoder.

Precautions:
1.Make sure that the circuit is connected properly.
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

Experiment 9

57
Objective: To simulate the common bus using tri-state buffers and decoder.

Software Used: Circuit Verse and Virtual Labs.

Theory:
Introduction
A typical computer has many registers and we need to transfer the information between
these registers. A way to transfer the information is using the common bus system. In
this article we shall discuss the common bus system using multiplexers.

Let’s discuss the common bus system with multiplexers.

The construction of this bus system for 4 registers is shown above. The bus consists of
4×1 multiplexers with 4 inputs and 1 output and 4 registers with bits numbered 0 to 3.
There are 2 select inputs S0 and S1 which are connected to the select inputs of the
multiplexers.
The output 1 of register A is connected to input 0 of MUX 1 and similarly other
connections are made as shown in the diagram. The data transferred to the bus
depends upon the select lines. A table for the various combinations of select lines is
shown below.

58
 SELECT LINES COMBINATION S1S0 REGISTER SELECTED

00 Register A

01 Register B

10 Register C

11 Register D
As we can see that when S1S0=00, register A is selected because on 00 the 0 data
inputs of all the multiplexers are applied to the common bus.
Since the 0 data inputs of all the multiplexers receive the inputs from the register A, thus
register A gets selected. Similarly, for other combinations of S1S0 other register are
selected.
No. of multiplexers needed = No. of bits in each register

Circuit Implementation:

D FLIP FLOP:

COMMON BUS USING MULTIPLEXER:

59
Result:
D FLIP FLOP:

COMMON BUS USING MULTIPLEXER:

60
Conclusion:
Hence, we can simulate common bus using tristate buffer and decoder.

Precautions:
1.Make sure that the circuit is connected properly.
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

61
 Experiment 10

Objective: Study of 8085 Microprocessor

Software Used: Virtual Labs.

Theory
8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor
designed by Intel in 1977 using NMOS technology.
It has the following configuration −

 8-bit data bus

 16-bit address bus, which can address up to 64KB
 A 16-bit program counter
 A 16-bit stack pointer
 Six 8-bit registers arranged in pairs: BC, DE, HL
 Requires +5V supply to operate at 3.2 MHZ single phase clock
It is used in washing machines, microwave ovens, mobile phones, etc.
8085 Microprocessor – Functional Units
8085 consists of the following functional units −
Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is
connected to internal data bus & ALU.
Arithmetic and logic unit
As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction,
AND, OR, etc. on 8-bit data.
General purpose register
There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register
can hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing combination is like B-C,
D-E & H-L.
Program counter
It is a 16-bit register used to store the memory address location of the next instruction to be
executed. Microprocessor increments the program whenever an instruction is being executed, so

62
that the program counter points to the memory address of the next instruction that is going to be
executed.
Stack pointer
It is also a 16-bit register works like stack, which is always incremented/decremented by 2
during push & pop operations.
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.
Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the
result stored in the accumulator.
These are the set of 5 flip-flops −

 Sign (S)
 Zero (Z)
 Auxiliary Carry (AC)
 Parity (P)
 Carry (C)
Its bit position is shown in the following table −

D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder decodes the information present in the Instruction
register.
Timing and control unit
It provides timing and control signal to the microprocessor to perform operations. Following are
the timing and control signals, which control external and internal circuits −

 Control Signals: READY, RD’, WR’, ALE

 Status Signals: S0, S1, IO/M’
 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT

63
Interrupt control
As the name suggests it controls the interrupts during a process. When a microprocessor is
executing a main program and whenever an interrupt occurs, the microprocessor shifts the
control from the main program to process the incoming request. After the request is completed,
the control goes back to the main program.
There are 5 interrupt signals in 8085 microprocessors: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP.
Serial Input/output control
It controls the serial data communication by using these two instructions: SID (Serial input
data) and SOD (Serial output data).
Address buffer and address-data buffer
The content stored in the stack pointer and program counter is loaded into the address buffer
and address-data buffer to communicate with the CPU. The memory and I/O chips are
connected to these buses; the CPU can exchange the desired data with the memory and I/O
chips.
Address bus and data bus
Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the location
to where it should be stored, and it is unidirectional. It is used to transfer the data & Address I/O
devices.
8085 Architecture
We have tried to depict the architecture of 8085 with this following image −

64
Pin Configuration of 8085 Microprocessor
The following image depicts the pin diagram of 8085 Microprocessor −

The pins of a 8085 microprocessor can be classified into seven groups −

Address bus
A15-A8, it carries the most significant 8-bits of memory/IO address.
Data bus
AD7-AD0, it carries the least significant 8-bit address and data bus.
Control and status signals
These signals are used to identify the nature of operation. There are 3 control signal and 3 status
signals.
Three control signals are RD, WR & ALE.

65
  RD − This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.
 WR − This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
 ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes
down it indicates data.
Three status signals are IO/M, S0 & S1.
IO/M
This signal is used to differentiate between IO and Memory operations, i.e. when it is high
indicates IO operation and when it is low then it indicates memory operation.
S1 & S0
These signals are used to identify the type of current operation.
Power supply
There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply and VSS
indicates ground signal.
Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.
 X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set
frequency of the internal clock generator. This frequency is internally divided by 2.
 CLK OUT − This signal is used as the system clock for devices connected with the
microprocessor.
Interrupts & externally initiated signals
Interrupts are the signals generated by external devices to request the microprocessor to perform
a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. We will
discuss interrupts in detail in interrupts section.
 INTA − It is an interrupt acknowledgment signal.
 RESET IN − This signal is used to reset the microprocessor by setting the program
counter to zero.
 RESET OUT − This signal is used to reset all the connected devices when the
microprocessor is reset.

66
  READY − This signal indicates that the device is ready to send or receive data. If
READY is low, then the CPU has to wait for READY to go high.
 HOLD − This signal indicates that another master is requesting the use of the address
and data buses.
 HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD
request and it will relinquish the bus in the next clock cycle. HLDA is set to low after the
HOLD signal is removed.
Serial I/O signals
There are 2 serial signals, i.e. SID and SOD and these signals are used for serial communication.
 SOD (Serial output data line) − The output SOD is set/reset as specified by the SIM
instruction.
 SID (Serial input data line) − The data on this line is loaded into accumulator whenever a
RIM instruction is executed.

Conclusion:
Hence, we study 8085 microprocessors.

Precautions:
Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

1.Make sure that the circuit is connected properly.

2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible.

67
68
 Experiment 11

Objective: Study of instruction set of 8085.

Software Used: Virtual Labs.

Theory
Instruction sets are instruction codes to perform some task. It is classified into five categories.
1 Control Instructions
2 Logical Instructions
3 Branching Instructions
4 Arithmetic Instructions
5 Data Transfer Instructions
Control Instructions
Following is the table showing the list of Control instructions with their meanings.

Opcod Operand Meaning Explanation

e

No operation No operation is performed, i.e., the instruction is

NOP None
fetched and decoded.

Halt and enter The CPU finishes executing the current

wait state instruction and stops further execution. An
HLT None
interrupt or reset is necessary to exit from the halt
state.

Disable The interrupt enable flip-flop is reset and all the

DI None
interrupts interrupts are disabled except TRAP.

Enable The interrupt enable flip-flop is set and all the

EI None
interrupts interrupts are enabled.

RIM None Read interrupt This instruction is used to read the status of
mask interrupts 7.5, 6.5, 5.5 and read serial data input

69
 bit.

Set interrupt This instruction is used to implement the

SIM None
mask interrupts 7.5, 6.5, 5.5, and serial data output.

Logical Instructions
The following table shows the list of Logical instructions with their meanings.

Opcod Operand Meaning Explanation

e

R Compare the register The contents of the operand (register or

CMP or memory with the memory) are M compared with the contents of
M accumulator the accumulator.

Compare immediate The second byte data is compared with the

CPI 8-bit data
with the accumulator contents of the accumulator.

The contents of the accumulator are logically

R Logical AND register
AND with M the contents of the register or
ANA or memory with the
M memory, and the result is placed in the
accumulator
accumulator.

Logical AND The contents of the accumulator are logically

ANI 8-bit data immediate with the AND with the 8-bit data and the result is
accumulator placed in the accumulator.

The contents of the accumulator are Exclusive

R Exclusive OR
OR with M the contents of the register or
XRA register or memory
M memory, and the result is placed in the
with the accumulator
accumulator.

Exclusive OR The contents of the accumulator are Exclusive

XRI 8-bit data immediate with the OR with the 8-bit data and the result is placed
accumulator in the accumulator.

ORA R Logical OR register The contents of the accumulator are logically

or memory with the OR with M the contents of the register or

70
 memory, and result is placed in the
M accumulator
accumulator.

Logical OR The contents of the accumulator are logically

ORI 8-bit data immediate with the OR with the 8-bit data and the result is placed
accumulator in the accumulator.

Each binary bit of the accumulator is rotated

Rotate the left by one position. Bit D7 is placed in the
RLC None
accumulator left position of D0 as well as in the Carry flag. CY
is modified according to bit D7.

Each binary bit of the accumulator is rotated

Rotate the right by one position. Bit D0 is placed in the
RRC None
accumulator right position of D7 as well as in the Carry flag. CY
is modified according to bit D0.

Each binary bit of the accumulator is rotated

Rotate the left by one position through the Carry flag. Bit
RAL None accumulator left D7 is placed in the Carry flag, and the Carry
through carry flag is placed in the least significant position
D0. CY is modified according to bit D7.

Each binary bit of the accumulator is rotated

right by one position through the Carry flag.
Rotate the
Bit D0 is placed in the Carry flag, and the
RAR None accumulator right
Carry flag is placed in the most significant
through carry
position D7. CY is modified according to bit
D0.

Complement The contents of the accumulator are

CMA None
accumulator complemented. No flags are affected.

Complement carry The Carry flag is complemented. No other

CMC None
flags are affected.

STC None Set Carry Set Carry

Branching instructions

71
The following table shows the list of Branching instructions with their meanings.

Opcode Opera Meaning Explanation

nd

16-bit Jump The program sequence is

JMP addres uncondition transferred to the memory
s ally address given in the operand.

Opcode Description Flag

Status

Jump on
JC CY=1
Carry

Jump on no
JNC CY=0
Carry

Jump on
JP S=0
positive
The program sequence is
16-bit Jump transferred to the memory
Jump on
JM S=1 addres conditionall address given in the operand
minus
s y based on the specified flag of
the PSW.
Jump on
JZ Z=1
zero

Jump on no
JNZ Z=0
zero

Jump on
JPE P=1
parity even

Jump on
JPO P=0
parity odd

16-bit Unconditio The program sequence is

Opcode Description Flag
addres nal transferred to the memory

72
 Status

Call on
CC CY=1
Carry

Call on no
CNC CY=0
Carry

Call on
CP S=0
positive
address given in the operand.
Call on subroutine Before transferring, the address
CM S=1 s
minus call of the next instruction after
CALL is pushed onto the stack.
CZ Call on zero Z=1

Call on no
CNZ Z=0
zero

Call on
CPE P=1
parity even

Call on
CPO P=0
parity odd

Return The program sequence is

from transferred from the subroutine
RET None subroutine to the calling program.
uncondition
ally

None Return The program sequence is

Opcod Description Flag
from transferred from the subroutine
e Status
subroutine to the calling program based on
conditionall the specified flag of the PSW
Return on y and the program execution
RC CY=1
Carry begins at the new address.

73
 Return on
RNC CY=0
no Carry

Return on
RP S=0
positive

Return on
RM S=1
minus

Return on
RZ Z=1
zero

Return on
RNZ Z=0
no zero

Return on
RPE P=1
parity even

Return on
RPO P=0
parity odd

The contents of registers H & L

Load the
are copied into the program
program
counter. The contents of H are
PCHL None counter
placed as the high-order byte
with HL
and the contents of L as the
contents
loworder byte.

RST 0-7 Restart The RST instruction is used as

software instructions in a
program to transfer the program
execution to one of the
following eight locations.

Instruction Restart Address

RST 0 0000H

74
 RST 1 0008H

RST 2 0010H

RST 3 0018H

RST 4 0020H

RST 5 0028H

RST 6 0030H

RST 7 0038H

The 8085 has additionally 4

interrupts, which can generate
RST instructions internally and
doesn’t require any external
hardware. Following are those
instructions and their Restart
addresses −

Interrupt Restart Address

TRAP 0024H

RST 5.5 002CH

RST 6.5 0034H

RST 7.5 003CH

Arithmetic instructions
Following is the table showing the list of Arithmetic instructions with their meanings.

Opcode Operand Meaning Explanation

75
 The contents of the register or memory
Add register or are added to the contents of the
R
ADD memory, to the accumulator and the result is stored in
M accumulator the accumulator.
Example − ADD K.

The contents of the register or memory

& M the Carry flag are added to the
R Add register to the
ADC contents of the accumulator and the
M accumulator with carry result is stored in the accumulator.
Example − ADC K

The 8-bit data is added to the contents of

Add the immediate to the accumulator and the result is stored
ADI 8-bit data in the accumulator.
the accumulator
Example − ADI 55K

The 8-bit data and the Carry flag are

Add the immediate to added to the contents of the accumulator
ACI 8-bit data the accumulator with and the result is stored in the
carry accumulator.
Example − ACI 55K

The instruction stores 16-bit data into

Reg. pair, 16bit Load the register pair the register pair designated in the
LXI operand.
data immediate
Example − LXI K, 3025M

The 16-bit data of the specified register

Add the register pair to pair are added to the contents of the HL
DAD Reg. pair register.
H and L registers
Example − DAD K

SUB R Subtract the register or The contents of the register or the

the memory from the memory are subtracted from the
M
accumulator contents of the accumulator, and the

76
 result is stored in the accumulator.
Example − SUB K

The contents of the register or the

memory & M the Borrow flag are
R Subtract the source and subtracted from the contents of the
SBB borrow from the accumulator and the result is placed in
M accumulator the accumulator.
Example − SBB K

The 8-bit data is subtracted from the

Subtract the immediate contents of the accumulator & the result
SUI 8-bit data is stored in the accumulator.
from the accumulator
Example − SUI 55K

The contents of register H are

exchanged with the contents of register
Subtract the immediate D, and the contents of register L are
SBI 8-bit data from the accumulator exchanged with the contents of register
with borrow E.
Example − XCHG

The contents of the designated register

R Increment the register or the memory are incremented by 1 and
INR their result is stored at the same place.
M or the memory by 1
Example − INR K

The contents of the designated register

Increment register pair pair are incremented by 1 and their
INX R result is stored at the same place.
by 1
Example − INX K

The contents of the designated register

R Decrement the register or memory are decremented by 1 and
DCR their result is stored at the same place.
M or the memory by 1
Example − DCR K

77
 The contents of the designated register
Decrement the register pair are decremented by 1 and their
DCX R result is stored at the same place.
pair by 1
Example − DCX K

The contents of the accumulator are

changed from a binary value to two 4-bit
BCD digits.
If the value of the low-order 4-bits in the
accumulator is greater than 9 or if AC
Decimal adjust flag is set, the instruction adds 6 to the
DAA None low-order four bits.
accumulator
If the value of the high-order 4-bits in
the accumulator is greater than 9 or if
the Carry flag is set, the instruction adds
6 to the high-order four bits.
Example − DAA

Data-transfer instructions
Following is the table showing the list of Data-transfer instructions with their meanings.

Opcod
Operand Meaning Explanation
e

Rd, Sc This instruction copies the contents of

Copy from the source the source register into the destination
MOV M, Sc (Sc) to the register without any alteration.
destination(Dt)
Dt, M Example − MOV K, L

The 8-bit data is stored in the

Rd, data
MVI Move immediate 8-bit destination register or memory.
M, data
Example − MVI K, 55L

LDA 16-bit address Load the accumulator The contents of a memory location,
specified by a 16-bit address in the

78
 operand, are copied to the accumulator.
Example − LDA 2034K

The contents of the designated register

pair point to a memory location. This
Load the accumulator instruction copies the contents of that
LDAX B/D Reg. pair
indirect memory location into the accumulator.
Example − LDAX K

The instruction loads 16-bit data in the

Load the register pair register pair designated in the register
LXI Reg. pair, 16-bit data or the memory.
immediate
Example − LXI K, 3225L

The instruction copies the contents of

the memory location pointed out by the
Load H and L registers address into register L and copies the
LHLD 16-bit address contents of the next memory location
direct
into register H.
Example − LHLD 3225K

The contents of the accumulator are

copied into the memory location
specified by the operand.
This is a 3-byte instruction, the second
STA 16-bit address 16-bit address
byte specifies the low-order address and
the third byte specifies the high-order
address.
Example − STA 325K

The contents of the accumulator are

copied into the memory location
Store the accumulator specified by the contents of the
STAX 16-bit address
indirect operand.
Example − STAX K

79
 The contents of register L are stored in
the memory location specified by the
16-bit address in the operand and the
contents of H register are stored into the
next memory location by incrementing
Store H and L registers the operand.
SHLD 16-bit address
direct
This is a 3-byte instruction, the second
byte specifies the low-order address and
the third byte specifies the high-order
address.
Example − SHLD 3225K

The contents of register H are

exchanged with the contents of register
Exchange H and L D, and the contents of register L are
XCHG None exchanged with the contents of register
with D and E
E.
Example − XCHG

The instruction loads the contents of the

H and L registers into the stack pointer
register. The contents of the H register
Copy H and L registers provide the high-order address and the
SPHL None
to the stack pointer contents of the L register provide the
low-order address.
Example − SPHL

The contents of the L register are

exchanged with the stack location
pointed out by the contents of the stack
pointer register.
Exchange H and L
XTHL None
with top of stack The contents of the H register are
exchanged with the next stack location
(SP+1).
Example − XTHL

PUSH Reg. pair Push the register pair The contents of the register pair
onto the stack designated in the operand are copied

80
 onto the stack in the following
sequence.
The stack pointer register is
decremented and the contents of the
high order register (B, D, H, A) are
copied into that location.
The stack pointer register is
decremented again and the contents of
the low-order register (C, E, L, flags)
are copied to that location.
Example − PUSH K

The contents of the memory location

pointed out by the stack pointer register
are copied to the low-order register (C,
E, L, status flags) of the operand.
The stack pointer is incremented by 1
Pop off stack to the and the contents of that memory
POP Reg. pair
register pair location are copied to the high-order
register (B, D, H, A) of the operand.
The stack pointer register is again
incremented by 1.
Example − POPK

The contents of the accumulator are

Output the data from copied into the I/O port specified by the
OUT 8-bit port address the accumulator to a operand.
port with 8bit address
Example − OUT K9L

The contents of the input port

Input data to designated in the operand are read and
IN 8-bit port address accumulator from a loaded into the accumulator.
port with 8-bit address
Example − IN5KL

Conclusion:

81
Hence, we study instruction set of 8085 microprocessors.

Precautions:
1.Make sure that the circuit is connected properly.
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

82
 Experiment 12

Objective: To Study & Verify Half and Full Subtractor.

Software Used: Circuit Verse and Virtual Labs.

Theory:
Introduction
Subtractor circuits take two binary numbers as input and subtract one binary number input from the other
binary number input. Like adders, it gives out two outputs, difference and borrow (carry-in the case of
Adder). There are two types of subtractors.
1) Half Subtractor
2) Full Subtractor

1) Half Subtractor
The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two
inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). The logic
symbol and truth table are shown below.

Figure-1: Logic Symbol of Half

subtractor
Figure-
2: Truth Table of Half subtractor

83
 Figure-3: Circuit Diagram of Half subtractor

From the above truth table, we can find the Boolean expression.

D=X⊕Y
B = X' Y
From the equation we can draw the half-subtractor circuit as shown in the figure 3.

2) Full Subtractor
A full subtractor is a combinational circuit that performs subtraction involving three bits, namely
minuend, subtrahend, and borrow-in . It accepts three inputs: minuend, subtrahend and a borrow bit and it
produces two outputs: difference and borrow. The logic symbol and truth table are shown below.

Figure-4: Logic Symbol of Full subtractor

Figure-5: Truth Table of Full subtractor

84
From the above truth table, we can find the Boolean expression .

D = A ⊕ B ⊕ Bin
B = A' Bin + A' B + B Bin
From the equation we can draw the Full-subtractor circuit as shown in the figure 6.

Figure-6: Circuit Diagram of Full subtractor

Circuit Implementation:

1) Half Subtractor:

85
2) Full Subtractor:

3) Full Subtractor using two Half Subtractors:

Result:

86
1) Half Subtractor:

2) Full Subtractor:

3) Full Subtractor using two Half Subtractors:

Conclusion:
Hence, we can simulate Half and Full Subtractor.

Precautions:
1. Make sure that the circuit is connected properly.
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible.

87
Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

88
 Experiment 13

Objective: To simulate the 8:3 encoder and 8:3 priority encoder.

Software Used: Circuit Verse and Virtual Labs.

Theory:
Introduction
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2^n input lines and ‘n’ output lines, hence it encodes the information from 2^n
inputs into an n-bit code. It will produce a binary code equivalent to the input, which is active
High. Therefore, the encoder encodes 2^n input lines with ‘n’ bits.

The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs : Y7 to Y0 and 3 outputs :
A2, A1 & A0. Each input line corresponds to each octal digit and three outputs generate
corresponding binary code.
The figure below shows the logic symbol of octal to binary encoder:

The truth table for 8 to 3 encoders is as follows

89
Logical expression for A2, A1 and A0:
A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
The above two Boolean functions A2, A1 and A0 can be implemented using four input OR
gates :

8-to-3 Bit Priority Encoder

Priority encoders are available in standard IC form and the TTL 74LS148 is an 8-to-3 bit priority
encoder which has eight active LOW (logic “0”) inputs and provides a 3-bit code of the highest
ranked input at its output.
Priority encoders output the highest order input first for example, if input lines “D2“, “D3” and
“D5” are applied simultaneously the output code would be for input “D5” (“101”) as this has the
highest order out of the 3 inputs. Once input “D5” had been removed the next highest output
code would be for input “D3” (“011”), and so on.
The truth table for a 8-to-3 bit priority encoder is given as:

90
 Digital Inputs Binary Output

D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 X 0 0 1

0 0 0 0 0 1 X X 0 1 0

0 0 0 0 1 X X X 0 1 1

0 0 0 1 X X X X 1 0 0

0 0 1 X X X X X 1 0 1

0 1 X X X X X X 1 1 0

1 X X X X X X X 1 1 1

Where X equals “dont care”, that is logic “0” or a logic “1”.

From this truth table, the Boolean expression for the encoder above with data inputs D0 to D7 and
outputs Q0, Q1, Q2 is given as:

91
Output Q0

Output Q1

Output Q2

Then the final Boolean expression for the priority encoder including the zero inputs is defined as:

Circuit Implementation:

8:3 Encoder:

4:2 Priority Encoder:

92
8:3 Priority Encoder using two 4:2 priority encoders

Result:
8:3 Encoder

8:3 priority encoder using two 4:2 priority encoders:

93
Conclusion:
Hence, we can simulate 8:3 encoder and 8:3 priority encoder.

Precautions:
1.Make sure that the circuit is connected properly.
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

94
 Experiment 14

Objective: To simulate the 1-bit and 2-bit comparator circuit.

Software Used: Circuit Verse and Virtual Labs.

Theory:

A magnitude digital Comparator is a combinational circuit that compares two digital or binary

numbers in order to find out whether one binary number is equal, less than or greater than the
other binary number. We logically design a circuit for which we will have two inputs one for A
and other for B and have three output terminals, one for A > B condition, one for A = B
condition and one for A < B condition.

1-Bit Magnitude Comparator –

A comparator used to compare two bits is called a single bit comparator. It consists of two
inputs each for two single bit numbers and three outputs to generate less than, equal to and
greater than between two binary numbers.

The truth table for a 1-bit comparator is given below:

From the above truth table logical expressions for each output can be expressed as follows:

A>B: AB'

95
A<B: A'B

A=B: A'B' + AB

From the above expressions we can derive the following formula:

By using these Boolean expressions, we can implement a logic circuit for this comparator
as given below:

2-Bit Magnitude Comparator –

A comparator used to compare two binary numbers each of two bits is called a 2-bit Magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to and
greater than between two binary numbers.

The truth table for a 2-bit comparator is given below:

96
From the above truth table K-map for each output can be drawn as follows:

97
From the above K-maps logical expressions for each output can be expressed as follows:

A>B:A1B1’ + A0B1’B0’ + A1A0B0’

A=B: A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’

: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)

: (A0B0 + A0’B0’) (A1B1 + A1’B1’)

: (A0 Ex-Nor B0) (A1 Ex-Nor B1)

A<B:A1’B1 + A0’B1B0 + A1’A0’B0

By using these Boolean expressions, we can implement a logic circuit for this comparator as
given below:

Circuit Implementation:
98
1-Bit Comparator

2-Bit Comparator using basic gates:

2-Bit Comparator using two 1-Bit Comparators

99
Result:
1-Bit comparator

2-Bit Comparator using Basic Gates

2-Bit Comparator using two 1-Bit Comparators

Conclusion:
Hence, we can simulate 1-bit and 2-bit comparators.

100
Precautions:
1.Make sure that the circuit is connected properly.
2. Use flags wherever necessary.
3. Test the circuit for as many inputs as possible.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6 (To be scaled down to 1)

101