Lab Record

Basic Electronics Engineering (ES201)

DEPARTMENT OF INFORMATION TECHNOLOGY

AMITY SCHOOL OF ENGINEERING AND TECHNOLOGY
AMITY UNIVERSITY UTTAR PRADESH

3rd Semester,
July-December 2020

By
Faculty: ……………….
…………………… ………………..
…………………

1
 INDEX

S.N Category of Cod Experiment Name of Date of Date of Max. Marks Signature
o Assignment e No. Experiment Allotment Evaluation obtained of
Marks
of Faculty
experimen
t
1. Mandatory LR 1 To study and 27/7/20 1
Experiment* (10) plot the
characteristic
s of a junction
diode.
2. 2 To study half 10/8/20 1
wave
rectifier.
3. 3 To study full 17/8/20 1
wave
rectifier.
4. 4 To study the 24/8/20 1
characteristic
s of Common
Emitter BJT.
5. 5 To study the 31/8/20 1
characteristic
s of Common
Base BJT.
6. 6 To study the 21/9/20 1
characteristic
s of Common
Emitter BJT
Amplifier.
7. 7 To study the 28/9/20 1
op amp as an
inverting and
non- inverting
amplifier.

2
 8. 8 To study the 05/10/20 1
Drain
characteristic
s and
Transfer
characteristic
s of Junction
Field Effect
Transistor
9. 9 To verify the 12/10/20 1
truth tables of
NOT, OR,
AND, NOR,
NAND, XOR,
XNOR gates
10. 10 To study Zener 19/10/20 1
diode I-V
characteristics
and Zener
diode as
voltage
regulator
11. Design Based PR 10
Open Ended (10)
experiment**

12. Viva Viva 5

(5)

3
 Experiment – 1
Objective  To study and plot the characteristics of a junction diode.
Software Used – Virtual Labs.
Theory:
Structure of P-N junction diode

The diode is a device formed from a junction of n-type and p-type semiconductor material. The
lead connected to the p-type material is called the anode and the lead connected to the n-type
material is the cathode. In general, the cathode of a diode is marked by a solid line on the diode.

Figure: 1

Figure: 2

Function of a P-N junction diode in Forward Bias

The positive terminal of battery is connected to the P side (anode) and the negative terminal of
battery is connected to the N side (cathode) of a diode, the holes in the p-type region and the
electrons in the n-type region are pushed toward the junction and start to neutralize the depletion
zone, reducing its width. The positive potential applied to the p-type material repels the holes,
while the negative potential applied to the n-type material repels the electrons. The change in
potential between the p side and the n side decreases or switches sign. With increasing forward-
bias voltage, the depletion zone eventually becomes thin enough that the zone's electric field
cannot counteract charge carrier motion across the p–n junction, which as a consequence reduces
electrical resistance. The electrons that cross the p–n junction into the p-type material (or holes
that cross into the n-type material) will diffuse into the nearby neutral region. The amount of
minority diffusion in the near-neutral zones determines the amount of current that may flow
through the diode.

4
 Figurer:3

Function of a P-N junction diode in Reverse Bias

The positive terminal of battery is connected to the N side(cathode) and the negative terminal of
battery is connected to the P side(anode) of a diode. Therefore, very little current will flow until
the diode breaks down.

Figurer:4

The positive terminal of battery is connected to the N side(cathode) and the negative terminal of
battery is connected to the P side(anode) of a diode, the 'holes' in the p-type material are pulled
away from the junction, leaving behind charged ions and causing the width of the depletion
region to increase. Likewise, because the n-type region is connected to the positive terminal, the
electrons will also be pulled away from the junction, with similar effect. This increases the
voltage barrier causing a high resistance to the flow of charge carriers, thus allowing minimal
electric current to cross the p–n junction. The increase in resistance of the p–n junction results in
the junction behaving as an insulator.
The strength of the depletion zone electric field increases as the reverse-bias voltage increases.
Once the electric field intensity increases beyond a critical level, the p–n junction depletion zone
breaks down and current begins to flow, usually by either the Zener or the avalanche breakdown
processes. Both of these breakdown processes are non-destructive and are reversible, as long as
the amount of current flowing does not reach levels that cause the semiconductor material to
overheat and cause thermal damage.

5
Forward and reverse biased characteristics of a Silicon diode

In forward biasing, the positive terminal of battery is connected to the P side and the negative
terminal of battery is connected to the N side of the diode. Diode will conduct in forward biasing
because the forward biasing will decrease the depletion region width and overcome the barrier
potential. In order to conduct, the forward biasing voltage should be greater than the barrier
potential. During forward biasing the diode acts like a closed switch with a potential drop of
nearly 0.6 V across it for a silicon diode. The forward and reverse bias characteristics of a silicon
diode. From the graph, you may notice that the diode starts conducting when the forward bias
voltage exceeds around 0.6 volts (for Si diode). This voltage is called cut-in voltage.

Figurer:5

In reverse biasing, the positive terminal of battery is connected to the N side and the negative
terminal of battery is connected to the P side of a diode. In reverse biasing, the diode does not
conduct electricity, since reverse biasing leads to an increase in the depletion region width; hence
current carrier charges find it more difficult to overcome the barrier potential. The diode will act
like an open switch and there is no current flow.

Forward and reverse biased characteristics of a Germanium diode

6
In forward biasing, the positive terminal of battery is connected to the P side and the negative
terminal of battery is connected to the N side of the diode. Diode will conduct in forward biasing
because the forward biasing will decrease the depletion region width and overcome the barrier
potential. In order to conduct, the forward biasing voltage should be greater than the barrier
potential. During forward biasing the diode acts like a closed switch with a potential drop of
nearly 0.3 V across it for a germanium diode. The forward and reverse bias characteristics of a
germanium diode. From the graph, you may notice that the diode starts conducting when the
forward bias voltage exceeds around 0.3 volts (for Ge diode). This voltage is called cut-in
voltage.

In reverse biasing, the positive terminal of battery is connected to the N side and the negative
terminal of battery is connected to the P side of a diode. In reverse biasing, the diode does not
conduct electricity, since reverse biasing leads to an increase in the depletion region width; hence
current carrier charges find it more difficult to overcome the barrier potential. The diode will act
like an open switch and there is no current flow.

Diode Equation

In the forward-biased and reversed-biased regions, the current (\(I_f\)), and the voltage (\(V_f\)),
of a semiconductor diode are related by the diode equation:

$$I_f=I_s \times (exp^\frac{V_f}{n \times{V_T}}-1)$$

where,
\(I_s\) is reverse saturation current or leakage current,
\(I_f\) is current through the diode(forward current),
\(V_f\) is potential difference across the diode terminals(forward voltage)
\(V_T\) is thermal voltage, given by
$$V_T=\frac{k \times T}{q}$$

and
k is Boltzmann’s constant = 1.38x10−23 J /°Kelvin,
q is the electronic charge = 1.6x10−19 joules/volt(Coulombs),
T is the absolute temperature in °Kelvin(°K = 273 + temperature in °C),
At room temperature (25 °C), the thermal voltage is about 25.7 mV,
n is an empirical constant between 0.5 and 2

The empirical constant, n, is a number that can vary according to the voltage and current levels.
It depends on electron drift, diffusion, and carrier recombination in the depletion region. Among
the quantities affecting the value of n are the diode manufacture, levels of doping and purity of
materials.

If n=1, the value of \(\frac{k \times T}{q}\) is 26 mV at 25°C.

When n=2, the value of \(\frac{k \times T}{q}\) becomes 52 mV. For germanium diodes, n is

7
usually considered to be close to 1. For silicon diodes, n is in the range of 1.3 to 1.6.

Circuit Implementation:

1) Forward Biased Silicon Diode:

2) Reverse Biased Silicon Diode:

8
Observation Table:
1) Forward Biased Silicon Diode:

9
2) Reverse Biased Silicon Diode:

10
Result  Given below are the graphs of the tables above:

11
1) Forward Biased Silicon Diode:

2) Reverse Biased Silicon Diode:

12
Conclusion  Hence, we study and plot the characteristics of a junction diode.
Precautions:
1. Connect the circuit properly.
2. Check the connection before taking the readings.
3. Take at least 10 to 12 readings to plot the graph properly.

13
 Experiment – 2
Objective  To study half wave, full wave and bridge rectifier with filters.
Software Used: Virtual Labs.
Theory:
Rectification

Figure:4

A rectifier is a device that converts alternating current (AC) to direct current (DC), a process
known as rectification. Rectifiers are essentially of two types – a half wave rectifier and a full
wave rectifier.

Half Wave Rectification

14
 Figure:3

On the positive cycle the diode is forward biased and on the negative cycle the diode is reverse
biased. By using a diode we have converted an AC source into a pulsating DC source. In
summary we have ‘rectified’ the AC signal.

Figure:5

The simplest kind of rectifier circuit is the half-wave rectifier.The half-wave rectifier is a circuit
that allows only part of an input signal to pass. The circuit is simply the combination of a single
diode in series with a resistor, where the resistor is acting as a load.

Half Wave Rectifiers – Waveforms

15
 Figure:6
The output DC voltage of a half wave rectifier can be calculated with the following two ideal
equations.
Vpeak=Vrms×√2Vpeak=Vrms×√2
Vdc=VpeakΠVdc=VpeakΠ

Half Wave Rectification: For Positive Half Cycle

Figure:1

Diode is forward biased, acts as a short circuit, passes the waveform through.

For positive half cycle:

VI−Vb−I×rd−I×R=0VI−Vb−I×rd−I×R=0
where,
VIVI is the input voltage,
VbVb is barrier potential,
rdrd is diode resistance,

16
II is total current,
RR is resistance
I=VI−Vbrd+RI=VI−Vbrd+R

VO=I×RVO=I×R

VO=VI−Vbrd+R×RVO=VI−Vbrd+R×R

For rdrd<< RR,
VO=VI−VbVO=VI−Vb

VbVb is 0.3 for Germanium ,

VbVb is 0.7 for Silicon

For VIVI<VbVb,

The diode will remain OFF.The Output voltage will be,

VO=0VO=0

For VIVI>VbVb,

The diode will be ON.The Output voltage will be,

VO=VI−VbVO=VI−Vb

Half Wave Rectification: For Negative Half Cycle

Figure:2

17
Diode is reverse biased, acts as a open circuit, does not pass the waveform through.

For negative half cycle:

VO=0Since,I=0VO=0Since,I=0

Half wave Rectification:For an Ideal Diode

For Ideal Diode,

Vb=0Vb=0

For positive half cycle,

VO=VIVO=VI

For negative half cycle,

VO=0VO=0

Average output voltage

VO=Vm×sinwtfor0≤wt≤πVO=Vm×sin⁡wtfor0≤wt≤π
VO=0forπ≤wt≤2πVO=0forπ≤wt≤2π
Vav=Vmπ=0.318VmVav=Vmπ=0.318Vm

RMS load voltage

Vrms=Irms×R=Vm2Vrms=Irms×R=Vm2

Average load current

Iav=VavR=VmπRIav=VavR=VmπR
Iav=Vmπ×R=ImπIav=Vmπ×R=Imπ
18
RMS load current
Irms=Im2Irms=Im2

Form factor: It is defined as the ratio of rms load voltage and average load voltage.
F.F=VrmsVavF.F=VrmsVav
F.F=Vm2Vav2=π2=1.57F.F=Vm2Vav2=π2=1.57
F.F≥1F.F≥1
rms≥avrms≥av

Ripple Factor

γ=√(F.F2−1×100%γ=√(F.F2−1×100%
γ=√(1.572−1)×100%=1.21%γ=√(1.572−1)×100%=1.21%

Efficiency: It is defined as ratio of dc power available at the load to the input ac power.
n%=PloadPin×100%n%=PloadPin×100%
n%=I2dc×RI2rms×R×100%n%=Idc2×RIrms2×R×100%
n%=I2mπ2I2m4×100%=4π2×100%=40.56%n%=Im2π2Im24×100%=4π2×100%=40.56%

Peak Inverse Voltage

For rectifier applications, peak inverse voltage (PIV) or peak reverse voltage (PRV) is the
maximum value of reverse voltage which occurs at the peak of the input cycle when the diode is
reverse-biased. The portion of the sinusoidal waveform which repeats or duplicates itself is
known as the cycle. The part of the cycle above the horizontal axis is called the positive half-
cycle, the part of the cycle below the horizontal axis is called the negative half cycle. With
reference to the amplitude of the cycle, the peak inverse voltage is specified as the maximum
negative value of the sine-wave within a cycle's negative half cycle.
PIV=VPIV=V
−Vm+V=0⇒V=Vm−Vm+V=0⇒V=Vm
PIV≥VmPIV≥Vm
Implementation:
Half Wave Rectifier:

19
Full Wave Rectifier:

20
Result:
Half Wave Rectifier:

21
Full Wave Rectifier:

22
Conclusion  Hence, study half wave, full wave and bridge rectifier with filters.
Precautions:
1. Connect the circuit properly.
2. Check the connection before taking the readings.
3. Take at least 10 to 12 readings to plot the graph properly.

23
 Experiment 3
Objective: To study full wave rectifier.
Software Used: Virtual Labs.
Theory:
Rectification

Figure :1

A rectifier is a device that converts alternating current (AC) to direct current (DC), a process
known as rectification. Rectifiers are essentially of two types – a half wave rectifier and a full
wave rectifier.

Full Wave Rectifier:

A full-wave rectifier is exactly the same as the half-wave, but allows unidirectional current
through the load during the entire sinusoidal cycle (as opposed to only half the cycle in the half-
wave). A full-wave rectifier converts the whole of the input waveform to one of constant polarity
(positive or negative) at its output. Let us see our half wave rectifier example and deduce the
circuit.

Figure:2
24
For a half wave Rectifier this is what we have observed

Figure:3
If we change the phase of the input waveform by 180 degrees

Figure:4

25
Now if we add these two circuits, we would get

Figure:5

Full Wave Rectifier – Circuit:

So, we have seen that this rectifier circuit consists of two sources which have a phase difference
along with two diodes. When V1 is positive, V2 is negative. Hence the top diode(D1) will be a
short and the bottom diode(D2) will be an open. On the other hand, when V1 is negative, V2 is
positive. Hence the bottom diode(D2) will be on and the top diode(D1) will be an open circuit.

Figure:6

Full Wave Rectifier – Waveforms

26

Figure:7
The resulting waveform of the schematic is shown above. This configuration is rarely used
because sometimes it may be impractical to obtain two voltage sources and it is difficult to
SYNC the sources. Let us see how a single source can be used.

Full Wave Rectifier – Centre Tapped Transformer

A Full-Wave Rectifier can be constructed using Centre-Tapped transformer – which give us two
shifted sinusoids so that exactly one of the waveforms is positive at one time and two diodes. As
compared to the half wave rectifier we use two diodes instead of one, one of the two diodes
remain in conduction in both of the half cycles. At any point in time, only one of the diodes is
forward biased. This allows for continuous conduction through load.

Figure:10
Figure:11

NPNS=VPVS=12NPNS=VPVS=12
⇒VS=2×VI⇒VS=2×VI

Centre Tapped Transformer – Positive cycle

27
 Figure:12

For Positive Cycle D1D1 is Forward Biased and D2D2 is Reverse Biased

VI−VO=0VI−VO=0
⇒VO=VI⇒VO=VI

Centre Tapped Transformer– Negative cycle

Figure:13

For Negative Cycle D1D1 is Reverse Biased and D2D2 is Forward Biased

VI−VO=0VI−VO=0
⇒VO=VI⇒VO=VI

Bridge Rectifier
Bridge rectifier uses 4 rectifying diodes connected in a "bridged" configuration to produce the
desired output but does not require a special centre tapped transformer, thereby reducing its size
and cost. The single secondary winding is connected to one side of the diode bridge network and
the load to the other side as shown below.

28
 Figure:14

Bridge Rectifier – Positive Half Cycle

During the positive half cycle of the supply diodes D1 and D2 conduct in series while diodes D3
and D4 are reverse biased (ideally they can be replaced with open circuits) and the current flows
through the load as shown below.

Figure:15

For Positive Half Cycle D1D1 and D2D2 is Forward Biased and D3D3 and D4D4 is Reverse

Biased.
VI−VO=0VI−VO=0
⇒VO=VI⇒VO=VI
VO=VI−2×VbVO=VI−2×Vb
VO=VI−2×Vb−2×IrdVO=VI−2×Vb−2×Ird
where,
VIVI is the input voltage,

29
VbVb is barrier potential,
rdrd is diode resistance

Bridge Rectifier – Negative Half Cycle

During the negative half cycle of the supply, diodes D3 and D4 conduct in series, but diodes D1
and D2 switch of as they are now reverse biased. The current flowing through the load is the
same direction as before.

Figure:16

For Negative Half Cycle D1D1 and D2D2 is Reverse Biased and D3D3 and D4D4 is Forward

Biased.
VI−VO=0VI−VO=0
⇒VO=VI⇒VO=VI

Average DC Load Voltage:

VO=Vm×sinwtfor0≤wt≤πVO=Vm×sin⁡wtfor0≤wt≤π
Vav=Vdc=2×VmπVav=Vdc=2×Vmπ

Average Load Current:

Iav=VavR=2×Vmπ×RIav=VavR=2×Vmπ×R
Iav=2×ImRIav=2×ImR

30
RMS Load Current:
I=Im×sinwtfor0≤wt≤πI=Im×sin⁡wtfor0≤wt≤π
Irms=Im√2Irms=Im√2

RMS Load Voltage:

Vrms=Irms×R=Im√2×RVrms=Irms×R=Im√2×R
Vrms=Vm√2Vrms=Vm√2

Form factor: It is defined as the ratio of rms load voltage and average load voltage.
F.F=VrmsVavF.F=VrmsVav

F.F=Vm√22×Vmπ=π2√2=1.11F.F=Vm√22×Vmπ=π2√2=1.11
F.F≥1F.F≥1

Ripple Factor:
γ=√(F.F2−1)×100%γ=√(F.F2−1)×100%
γ=√(1.112−1)×100%=48.1%γ=√(1.112−1)×100%=48.1%

Efficiency: It is defined as ratio of dc power available at the load to the input ac power.
n%=PloadPin×100%n%=PloadPin×100%
n%=I2dc×RI2rms×R×100%n%=Idc2×RIrms2×R×100%
n%=4×I2mπ2I2m2×100%=8π2×100%=81.13%n%=4×Im2π2Im22×100%=8π2×100%=81.13%

Peak Inverse Voltage:

For rectifier applications, peak inverse voltage (PIV) or peak reverse voltage (PRV) is the
maximum value of reverse voltage which occurs at the peak of the input cycle when the diode is
reverse-biased. The portion of the sinusoidal waveform which repeats or duplicates itself is
known as the cycle. The part of the cycle above the horizontal axis is called the positive half-
cycle, the part of the cycle below the horizontal axis is called the negative half cycle. With
reference to the amplitude of the cycle, the peak inverse voltage is specified as the maximum
negative value of the sine-wave within a cycle's negative half cycle.

For Bridge Rectifier,

31
D1D1 and D2D2 is Forward Biased
D3D3 and D4D4 is Reverse Biased
Vm−VO=0Vm−VO=0
⇒VO=Vm⇒VO=Vm
−VO+PIV=0−VO+PIV=0
⇒PIV=Vm⇒PIV=Vm
PIV≥VmPIV≥Vm
For Center Tapped Rectifier,
D2D2 is Forward Biased,
PIV at D1D1,
Vm−VO=0Vm−VO=0
⇒VO=Vm⇒VO=Vm
VO−PIV+VmVO−PIV+Vm
⇒PIV=2Vm⇒PIV=2Vm
PIV≥2VmPIV≥2Vm

Note:
An alternative representation of full-wave bridge rectifier circuit is easier both to remember and
to comprehend. It's the exact same circuit, except all diodes are drawn in a horizontal attitude, all
“pointing” the same direction.

Figure:17

Circuit Implementation:

32
Result:

Conclusion:
Hence, we study the characteristics of half wave rectifier.

33
Precautions:
1. Connect the circuit properly.
2. Check the connection before taking the readings.
3. Take at least 10 to 12 readings to plot the graph properly.

Experiment 4
Objective: To study the characteristics of Common Emitter BJT.

34
Software Used: Virtual Labs.
Theory:
Structure of Bipolar Junction Transistor

A bipolar junction transistor, BJT, is a single piece of silicon with two back-to-back P-N
junctions. BJTs can be made either as PNP or as NPN.

Figure 1: Structures, layers and circuit symbol of NPN transistor

They have three regions and three terminals, emitter, base, and collector represented by E, B, and
C respectively. The direction of the arrow indicates the direction of the current in the emitter
when the transistor is conducting normally. An easy way to remember this is NPN stands for
"Not Pointing iN".

Figure 2: Structures, layers and circuit symbol of PNP transistor

Emitter (E): It is the region to the left end which supply free charge carriers i.e., electrons in n-
p-n or holes in p-n-p transistors. These majority carriers are injected to the middle region i.e.
electrons in the p region of n-p-n or holes in the n region of p-n-p transistor. Emitter is a heavily
doped region to supply a large number of majority carriers into the base.
Base (B): It is the middle region where either two p-type layers or two n-type layers are
sandwiched. The majority carriers from the emitter region are injected into this region. This
region is thin and very lightly doped.
Collector (C): It is the region to right end where charge carriers are collected. The area of this
region is largest compared to emitter and base region. The doping level of this region is
intermediate between heavily doped emitter region and lightly doped base region.

Note

35
 1. In digital electronics applications, the transistors are used as a switch.
2. Most bipolar switching circuits use NPN transistors.

Operation of Bipolar Junction Transistor

Figure 3: Four Operating Conditions

Cut-off Region: Base-emitter junction is reverse biased. No current flow.
Saturation Region: Base-emitter junction is forward biased and Collector-base junction is
forward biased.
Active Region: Base-emitter is junction forward biased and Collector-base junction is reverse
biased.
Breakdown Region: \(I_C\) and \(V_{CE}\) exceed specifications and can cause damage to the
transistor.

Cut-Off Region:
In Cut-Off region both junctions are reverse biased, Base-emitter junction is reverse biased (\
(V_{BE}<0\))and also Collector-Base junction is reverse biased(\(V_{CB}>0\)).With reverse
biasing, all currents are zero. There are some leakage currents associated with reverse biased
junctions, but these currents are small and therefore can be neglected.
Application: Open switch

Forward Active Region:

In Forward Active Region Base-emitter junction is forward biased(\(V_{BE}>0\)) and Collector-
Base junction is reverse biased(\(V_{CB}>0\)). In this case, the forward bias of the BE junction
will cause the injection of both holes and electrons across the junction. The holes are of little
consequence because the doping levels are adjusted to minimize the hole current. The electrons
are the carriers of interest. The electrons are injected into the base region where they are called
the minority carrier even though they greatly outnumber the holes.
Application: Amplifier in analogy circuits

36
$$I_C= -α_F \times I_E + I_{CO}$$
where,
\(α_F\) is the forward current transfer ratio
\(I_{CO}\) is Collector reverse saturation current

Saturation Region:
In Saturation region both junctions are Forward biased, Base-emitter junction is forward biased(\
(V_{BE}>0\)) and also Collector-Base junction is forward biased(\(V_{CB}<0\)). Maximum
currents flow through the transistor with only a small voltage drop across the collector junction.
The transistor also does not respond to any change in emitter current or base-emitter voltage.
Application: Closed switch

Reverse Active Region:

In Reverse Active region Base-emitter junction is reverse biased(\(V_{BE}<0\)) and Collector-
Base junction is forward biased(\(V_{CB}<0\)).The operation is just the same as the forward
active region, except all voltage sources, and hence collector and emitter currents, are the reverse
of the forward bias case. The current gain in this mode is smaller than that of forward active
mode for which this mode in general unsuitable for amplification.
Application: In digital circuits and analog switching circuits.

$$I_E = -α_R* I_C + I_{EO}$$ where,

\(α_R\) is the reverse current transfer ratio\newline \(I_{EO}\) is the Emitter reverse saturation
current

This configuration is rarely used because most transistors are doped selectively to give forward
current transfer ratios very near unity, which automatically causes the reverse current transfer
ratio to be very low.

BJT – Common Emitter Circuit

The DC behaviour of the BJT can be described by the Ebbers-Moll Model. The equations for the
model are:
$$I_F= I_{ES} \times ( exp^ \frac{V_{BE}}{V_T} -1)$$
$$I_R= I_{CS} \times(exp^ \frac{V_{CB}}{V_T} -1)$$ where,
\(I _{ES}\) is base-emitter saturation currents,
\(I_{CS}\) is base-collector saturation currents
$$V_T = \frac{k \times T}{q}$$
where,

37
k is the Boltzmann’s constant ( k = 1.381 e-23 V.C/ K ),
T is the absolute temperature in degrees Kelvin, and
q is the charge of an electron (q = 1.602 e-19 C).

$$β_F = \frac{α_F}{1 - α_F}$$ $$β_R= \frac{α_R}{1 - α_R}$$

where,
\(β_F\) is large signal forward current gain of common-emitter configuration,
\(β_R\) is the large signal reverse current gain of the common-emitter configuration
$$ α_F=\frac{β_F}{1 + β_F}$$
$$α_R=\frac{β_R}{1 + β_R}$$
where,
\(α_R\) is large signal reverse current gain of a common-base configuration,
\(α_F\) is large signal forward current gain of the common-base configuration.
$$I_C = α_F \times I_F - I_R$$
$$ I_E = -I_F + α_R * I_R$$
$$ I_B = (1 - α_F) \times I_F + (1 - α_R) \times I_R$$
The forward and reverse current gains are related by the expression
$$ α_R \times I_{CS}=α_F \times I_{ ES} =I_S$$
where,
\(I_S\) is the BJT transport saturation current.
The parameters \(α_R\) and \(α_F\) are influenced by impurity concentrations and junction
depths.
The saturation current, \(I_S\) , can be expressed as
$$ I_S = J_S \times A$$
where,
A is the area of the emitter and
\(J_S\) is the transport saturation current density

Input Characteristics
The most important characteristic of the BJT is the plot of the base current, \(I_B\), versus the
base-emitter voltage,\(V_{BE}\), for various values of the collector-emitter voltage,\(V_{CE}\)
$$I_B=\phi (V_{BE},V_{CE}) \quad for\quad constant \quad V_{CE}$$

Figure 4: Input Characteristics Circuit

38
Output Characteristics
The most important characteristic of the BJT is the plot of the collector current, IC, versus the
collector-emitter voltage, for various values of the base current, IB as shown on the circuit on the
right.
$$I_C =\phi(V_{CE} , I_B) \qquad for\quad constant \quad I_B $$

Figure 5: Output Characteristics Circuit

Readings:
1. Input:

2. Output:

39
Results:
1. Input:

2. Output:

40
Conclusion:
Hence, we study the characteristics of Common Emitter BJT.

Precautions:
1. Connect the circuit properly.
2. Check the connection before taking the readings.
3. Take at least 10 to 12 readings to plot the graph properly.

Experiment 5
Objective: To study the characteristics of Common Base BJT.
Software Used: Virtual Labs.
Theory:
Structure of Bipolar Junction Transistor

A bipolar junction transistor, BJT, is a single piece of silicon with two back-to-back P-N
junctions. BJTs can be made either as PNP or as NPN.

Figure 1: Structures, layers and circuit symbol of NPN transistor

They have three regions and three terminals, emitter, base, and collector represented by E, B, and
C respectively. The direction of the arrow indicates the direction of the current in the emitter

41
when the transistor is conducting normally. An easy way to remember this is NPN stands for
"Not Pointing iN".

Figure 2: Structures, layers and circuit symbol of PNP transistor

Emitter (E): It is the region to the left end which supply free charge carriers i.e., electrons in n-
p-n or holes in p-n-p transistors. These majority carriers are injected to the middle region i.e.
electrons in the p region of n-p-n or holes in the n region of p-n-p transistor. Emitter is a heavily
doped region to supply a large number of majority carriers into the base.
Base (B): It is the middle region where either two p-type layers or two n-type layers are
sandwiched. The majority carriers from the emitter region are injected into this region. This
region is thin and very lightly doped.
Collector (C): It is the region to right end where charge carriers are collected. The area of this
region is largest compared to emitter and base region. The doping level of this region is
intermediate between heavily doped emitter region and lightly doped base region.
Note
1. In digital electronics applications, the transistors are used as a switch.
2. Most bipolar switching circuits use NPN transistors.

Operation of Bipolar Junction Transistor

Figure 3: Four Operating Conditions

Cut-off Region: Base-emitter junction is reverse biased. No current flow.

Saturation Region: Base-emitter junction is forward biased and Collector-base junction is
forward biased.

42
Active Region: Base-emitter is junction forward biased and Collector-base junction is reverse
biased.
Breakdown Region: IC and VCE exceed specifications and can cause damage to the transistor.
Cut-off Region: Base-emitter junction is reverse biased. No current flow.
Saturation Region: Base-emitter junction is forward biased and Collector-base junction is
forward biased.
Active Region: Base-emitter is junction forward biased and Collector-base junction is reverse
biased.
Breakdown Region: \(I_C\) and \(V_{CE}\) exceed specifications and can cause damage to the
transistor.

Cut-Off Region:
In Cut-Off region both junctions are reverse biased, Base-emitter junction is reverse biased (\
(V_{BE}<0\)) and also Collector-Base junction is reverse biased(\(V_{CB}>0\)).With reverse
biasing, all currents are zero. There are some leakage currents associated with reverse biased
junctions, but these currents are small and therefore can be neglected.
Application: Open switch

Forward Active Region:

In Forward Active region Base-emitter junction is forward biased(\(V_{BE}>0\)) and Collector-

Base junction is reverse biased(\(V_{CB}>0\)). In this case, the forward bias of the BE junction
will cause the injection of both holes and electrons across the junction. The holes are of little
consequence because the doping levels are adjusted to minimize the hole current. The electrons
are the carriers of interest. The electrons are injected into the base region where they are called
the minority carrier even though they greatly outnumber the holes.
Application: Amplifier in analog circuits
$$I_C= -α_F \times I_E + I_{CO}$$
where,
\(α_F\) is the forward current transfer ratio
\(I_{CO}\) is Collector reverse saturation current

Saturation Region:
In Saturation region both junctions are Forward biased, Base-emitter junction is forward biased(\
(V_{BE}>0\)) and also Collector-Base junction is forward biased(\(V_{CB}<0\)). Maximum
currents flows through the transistor with only a small voltage drop across the collector junction.
The transistor also does not respond to any change in emitter current or base-emitter voltage.
Application: Closed switch

Reverse Active Region:

43
In Reverse Active region Base-emitter junction is reverse biased(\(V_{BE}<0\)) and Collector-
Base junction is forward biased(\(V_{CB}<0\)).The operation is just the same as the forward
active region, except all voltage sources, and hence collector and emitter currents, are the reverse
of the forward bias case. The current gain in this mode is smaller than that of forward active
mode for which this mode in general unsuitable for amplification.
Application: In digital circuits and analog switching circuits.
$$I_E = -α_R* I_C + I_{EO}$$ where,
\(α_R\) is the reverse current transfer ratio\newline \(I_{EO}\) is the Emitter reverse saturation
current.
This configuration is rarely used because most transistors are doped selectively to give forward
current transfer ratios very near unity, which automatically causes the reverse current transfer
ratio to be very low.

BJT - Common Emitter Circuit

The DC behaviour of the BJT can be described by the Ebers-Moll Model. The equations for the
model are:
$$I_F= I_{ES} \times ( exp^ \frac{V_{BE}}{V_T} -1)$$
$$I_R= I_{CS} \times(exp^ \frac{V_{CB}}{V_T} -1)$$ where,
\(I _{ES}\) is base-emitter saturation currents,
\(I_{CS}\) is base-collector saturation currents
$$V_T = \frac{k \times T}{q}$$
where,
k is the Boltzmann’s constant ( k = 1.381 e-23 V.C/ K ),
T is the absolute temperature in degrees Kelvin, and
q is the charge of an electron (q = 1.602 e-19 C).
$$β_F = \frac{α_F}{1 - α_F}$$ $$β_R= \frac{α_R}{1 - α_R}$$
where,
\(β_F\) is large signal forward current gain of common-emitter configuration,
\(β_R\) is the large signal reverse current gain of the common-emitter configuration
$$ α_F=\frac{β_F}{1 + β_F}$$
$$α_R=\frac{β_R}{1 + β_R}$$
where,
\(α_R\) is large signal reverse current gain of a common-base configuration,
\(α_F\) is large signal forward current gain of the common-base configuration.
$$I_C = α_F \times I_F - I_R$$
$$ I_E = -I_F + α_R * I_R$$
$$ I_B = (1 - α_F) \times I_F + (1 - α_R) \times I_R$$
The forward and reverse current gains are related by the expression
$$ α_R \times I_{CS}=α_F \times I_{ ES} =I_S$$
where,
\(I_S\) is the BJT transport saturation current.
The parameters \(α_R\) and \(α_F\) are influenced by impurity concentrations and junction

44
depths.
The saturation current, \(I_S\) , can be expressed as
$$ I_S = J_S \times A$$
where,
A is the area of the emitter and
\(J_S\) is the transport saturation current density

Input Characteristics:
The most important characteristic of the BJT is the plot of the emitter current, IE, versus the base-
emitter voltage, VBE, for various values of the collector-base voltage, VCB

$$I_E=\phi (V_{BE},V_{CB}) \qquad for \quad constant \quad V_{CB}$$

Figure 4: Input Characteristics Circuit

Output Characteristics:
The most important characteristic of the BJT is the plot of the collector current, IC, versus the
collector-base voltage, VCB, for various values of the emitter current, IE as shown on the circuit
on the right.
$$I_C =\phi(V_{CB} , I_E) \qquad for \quad constant \quad I_E$$

Figure 5: Output Characteristics Circuit

Readings:

45
1. Input:

2. Output:

Results:
1. Input:

46
2. Output:

Conclusion:
Hence, we study the characteristics of Common Base BJT.

Precautions:
1. Connect the circuit properly.
2. Check the connection before taking the readings.
3. Take at least 10 to 12 readings to plot the graph properly.

47
 Experiment 6
Objective: To study the characteristics of Common Emitter BJT Amplifier.
Software Used: Virtual Labs.
Theory:
The common emitter configuration is widely used as a basic amplifier as it has both voltage and
current amplification.
Resistors \(R_{B1}\) and \(R_{B2}\) form a voltage divider across the base of the transistor. The
function of this network is to provide necessary bias condition and ensure that emitter-base
junction is operating in the proper region.
In order to operate transistor as an amplifier, biasing is done in such a way that the operating
point is in the active region. For an amplifier the Q-point is placed so that the load line is
bisected. Therefore, in practical design \(V_{CE}\) is always set to \(V_{CC}/2\). This will
confirm that the Q-point always swings within the active region. This limitation can be explained
by maximum signal handling capacity. For the maximum input signal, output is produced
without any distortion and clipping.

The Bypass Capacitor

The emitter resistor RE is required to obtain the DC quiescent point stability. However the
inclusion of \(R_E\) in the circuit causes a decrease in amplification at higher frequencies. In
order to avoid such a condition, it is bypassed by a capacitor so that it acts as a short circuit for
AC and contributes stability for DC quiescent condition. Hence capacitor is connected in parallel
with emitter resistance. $$ X_{CE}<< R_E $$ $$ \frac{1}{2 \times \pi \times f \times C_E} <<
R_E $$ $$ C_E >> \frac{1}{2 \times \pi \times f \times R_E} $$

The Input/ Output Coupling (or Blocking) Capacitor

An amplifier amplifies the given AC signal. In order to have noiseless transmission of a signal
(without DC), it is necessary to block DC i.e. the direct current should not enter the amplifier or
load. This is usually accomplished by inserting a coupling capacitor between two stages. $$
X_{CC} << R_i \times h_{ie} $$ $$ \frac{1}{2 \times \pi \times f \times C_C} << R_i \times
h_{ie} $$ $$ C_C >> \frac{1}{2 \times \pi \times f \times (R_i \times h_{ie})} $$
\(C_C\) - Output Coupling Capacitor
\(C_B\) - Input Coupling Capacitor

Frequency response of Common Emitter Amplifier

Emitter bypass capacitors are used to short circuit the emitter resistor and thus increases the gain
at high frequency. The coupling and bypass capacitors cause the fall of the signal in the low
frequency response of the amplifier because their impedance becomes large at low frequencies.
The stray capacitances are effectively open circuits. In the mid frequency range large capacitors

48
are effectively short circuits and the stray capacitors are open circuits, so that no capacitance
appears in the mid frequency range. Hence the mid band frequency gain is maximum. At the
high frequencies, the bypass and coupling capacitors are replaced by short circuits. The stray
capacitors and the transistor determine the response.
The input resistance is medium and is essentially independent of the load resistance \(R_L\) . The
output resistance is relatively high and is essentially independent of the source resistance.

Figure: 1

The coupling capacitor, \(C_{C1}\) , couples the source voltage \(V_S\) to the biasing network.
Coupling capacitor \(C_{C2}\) connects the collector resistance \(R_C\) to the load \(R_L\) . The
bypass capacitance \(C_E\) is used to increase the midband gain, since it effectively short circuits
the emitter resistance \(R_E\) at midband frequencies. The resistance \(R_E\) is needed for bias
stability. The external capacitors \(C_{C1}\), \(C_{C2}\), \(C_E\) will influence the low
frequency response of the common emitter amplifier. The internal capacitances of the transistor
will influence the high frequency cut-off. $$ A(s)=\frac{A_m \times S^2 \times (S+w_Z)}
{(S+w_{L1})\times (S+w_{L2})\times (S+w_{L3})\times (1+ \frac{S}{w_H})} $$ where,
\(A_M\) is the midband gain,
\(w_H\) is the frequency of the dominant high frequency pole,
\(w_{L1}\), \(w_{L2}\), \(w_{L3}\) are low frequency poles introduced by the coupling and
bypass capacitors,
\(w_Z\) is the zero introduced by the bypass capacitor.

The midband gain is obtained by short circuiting all the external capacitors and open circuiting
the internal capacitors. Figure 2 shows the equivalent for calculating the midband gain.

49
 Figure: 2

$$ A_m=\frac{V_o}{V_s} =-β [r_{CE}|| R_C || R_L][\frac{R_B}{R_B+r_{pi}}][\frac{1}

{R_S+(R_B||r_{pi})}]$$
It can be shown that the low frequency poles, \(w_{L1}\), \(w_{L2}\), \(w_{L3}\) can be
obtained by the following equations: $$ τ_1=\frac{1}{w_{L1}}=C_{C1} \times R_{IN} $$
where, $$ R_{IN}=R_{S}+[R_B || r_{pi}] $$ $$ τ_2=\frac{1}{w_{L2}}=C_{C2} \times
[R_{L}+(R_C || r_{CE})] $$ $$ τ_3=\frac{1}{w_{L3}}=C_E \times R'_E $$ $$ R'_E=R_E ||
[\frac{r_{pi}}{β_F +1}+(\frac{R_B || R_S}{β_F +1})]$$ $$ w_Z=\frac{1}{R_E \times C_E} $
$ Normally, \(w_Z < w_{L3}\) and the low frequency cut-off \(w_L\) is larger than the largest
pole frequency. The low frequency cut-off can be approximated as $$ w_L≅\sqrt(w_{L1})^2+
(w_{L2})^2+(w_{L3})^2 $$ The high frequency equivalent circuit of the common-emitter
amplifier is shown in Figure 3.

Fig
ure: 3

In Figure 3, \(C_μ\) is the collector-base capacitance, \(C_π\) is the emitter to base capacitance, \
(r_X\) is the resistance of silicon material of the base region between the base terminal B and an
internal or intrinsic base terminal B’. Using the Miller Theorem, it can be shown that the 3-dB
frequency at high frequencies is approximately given as $$ w_H^{-1}=(r_{pi}||[r_x+(R_B||
R_S)])\times C_T $$ where, $$ C_T=C_π+C_μ[1+g_m(R_L|| R_C)] $$ and $$g_m=\frac{I_C}
{V_T}$$

50
Readings:

Results:

51
Conclusion:
Hence, we study the characteristics of Common Emitter BJT Amplifier.

Precautions:
1. Connect the circuit properly.
2. Check the connection before taking the readings.
3. Take at least 15 to 25 readings to plot the graph properly.

52
 Experiment 7
Objective: To study the op amp as an inverting and non- inverting amplifier.
Software Used: Virtual Labs.
Theory:
Operational Amplifier commonly known as Op-Amp, is a linear electronic device having three
terminals, two high impedance input and one output terminal. Op-Amp can perform multiple
function when attached to different feedback combinations like resistive, capacitive or both.
Generally, it is used as voltage amplifier and the output voltage of the Op-Amp is the difference
between the voltages at its two input terminals.

Op-Amp shows some properties that make it an ideal amplifier, its open loop gain and input
impedance is infinite (i.e., practically very high), Output impedance and offset voltage is
zero(i.e., practically very low) and bandwidth is infinite(i.e., practically limited to frequency
where its gain become unity).

Figure: 1

Inverting Op-Amp

The open loop gain(Ao) of the Om-Apm is very high which makes it very unstable, so to make it
stable with a controlable gain, a feed back is applied through some external resistor(Rf) from its
output to inverting input terminal(i.e.,also known as negative feedback) resulting in reduced
gain(cloosed loop gain, Av). So the voltage at inverting terminal is now the sum of the actual
input and feedback voltages, and to separate both a input resistor(Ri) is introduced in the circuit.
The non inverting terminal of the opamp is grounded, and the inverting terminal behaves like a
virtual ground as the junction of the input and feedback signal are at the same potential.

53
 Figure: 2

Current can be given

I=(Vin−Vout)(Rin+RF)I=(Vin−Vout)(Rin+RF)

or,
I=(Vin−V2)RinI=(Vin−V2)Rin

or,
I=(V2−Vout)RFI=(V2−Vout)RF

I=VinRin−V2Rin=V2RF−VoutRFI=VinRin−V2Rin=V2RF−VoutRF

So,
VinRin=V2×(1Rin+1R)−VoutRFVinRin=V2×(1Rin+1R)−VoutRF

and as, V2=0V2=0
I=(Vin−0)Rin=(0−Vout)RFI=(Vin−0)Rin=(0−Vout)RF

or,
RFRin=−VoutVinRFRin=−VoutVin

The close loop gain (AclAcl) is given by :-

Acl=VoutVin=−RFRinAcl=VoutVin=−RFRin

Output voltage (VoutVout) is given by :-

Vout=−RFRin×VinVout=−RFRin×Vin

54
Non-Inverting Op-Amp

In this configuration of Op-amp the input signal is directly fed to the non inverting terminal
resulting in a positive gain and output voltage in phase with input as compared to inverting Op-
amp where the gain is negative and output voltage is out of phase with input , and to stabalize the
circuit a negative feedback is applied through a resistor(Rf) and the inverting terminal is
grounded witha input resistor(R2).This inverting Op-Amp like layout the at inverting terminal
creates a virtual ground at the summing point make the Rf and R2 a potential divider accross
inverting terminal, Hence determines the gain of the circuit.

Figure: 3

Potential difference V1V1 can be written as

V1=R2(R2+RF)×VoutV1=R2(R2+RF)×Vout

in ideal condition :V1=VinV1=Vin

SO,
Vin=R2(R2+RF)×VoutVin=R2(R2+RF)×Vout

and as we know Gain Acl=VoutVinAcl=VoutVin

Acl=VoutVin=(R2+RF)R2=1+RFR2Acl=VoutVin=(R2+RF)R2=1+RFR2
and Output Voltage (VoutVout) is given by:
Vout=[1+RFR2]∗Vin

Circuits:
Inverting:

55
Non-Inverting:

Readings:
Inverting:

Input Voltage Output Voltage Current

Serial No.
V V mA
1 -15 22.5 -0.0185
2 -13 19.5 -0.0160
3 -11 16.5 -0.0135
4 -9 13.5 -0.0111
5 -7 10.5 -0.00862

56
 6 -5 7.50 -0.00616
7 -3 4.50 -0.00369
8 -1 1.50 -0.00123
9 1 -1.50 0.00123
10 3 -4.50 0.00369
11 5 -7.50 0.00616
12 7 -10.5 0.00862
13 9 -13.5 0.0111
14 11 -16.5 0.0135
15 13 -19.5 0.0160
Non-Inverting:

Input Voltage Output Voltage Current

Serial No.
V V mA
1 -15 -37.5 NaN
2 -13 -32.5 NaN
3 -11 -27.5 NaN
4 -9 -22.5 NaN
5 -7 -17.5 NaN
6 -5 -12.5 NaN
7 -3 -7.50 NaN
8 -1 -2.50 NaN
9 1 2.50 0.00616
10 3 7.50 0.0185
11 5 12.5 0.252
12 7 17.5 0.353
13 9 22.5 0.454
14 11 27.5 0.555
15 13 32.5 0.656

Results:
Inverting:

57
Non-Inverting:

Conclusion:
Hence, we study the op amp as an inverting and non- inverting amplifier.

Precautions:
1. Connect the circuit properly.
2. Check the connection before taking the readings.
3. Take at least 15 to 25 readings to plot the graph properly.

58
 Experiment-8
Objective: To study the op amp as an inverting and non-inverting amplifier.
Software Used: Virtual Labs.
Theory:
Operational Amplifier commonly known as Op-Amp, is a linear electronic device having three
terminals, two high impedance input and one output terminal. Op-Amp can perform multiple
function when attached to different feedback combinations like resistive, capacitive or both.
Generally, it is used as voltage amplifier and the output voltage of the Op-Amp is the difference
between the voltages at its two input terminals.

Op-Amp shows some properties that make it an ideal amplifier, its open loop gain and input
impedance is infinite (i.e., practically very high), Output impedance and offset voltage is
zero(i.e., practically very low) and bandwidth is infinite(i.e., practically limited to frequency
where its gain become unity).

Figure: 1

Inverting Op-Amp

The open loop gain(A0) of the Om-Amp is very high which makes it very unstable, so to make it
stable with a controllable gain, a feedback is applied through some external resistor(Rf) from its
output to inverting input terminal(i.e., also known as negative feedback) resulting in reduced
gain(closed loop gain, Av). So the voltage at inverting terminal is now the sum of the actual
input and feedback voltages, and to separate both a input resistor (Ri) is introduced in the circuit.
The non-inverting terminal of the op amp is grounded, and the inverting terminal behaves like a
virtual ground as the junction of the input and feedback signal are at the same potential.

59
 Figure: 2

Current can be given

I=(Vin−Vout)(Rin+RF)I=(Vin−Vout)(Rin+RF)

or,
I=(Vin−V2)RinI=(Vin−V2)Rin

or,
I=(V2−Vout)RFI=(V2−Vout)RF

I=VinRin−V2Rin=V2RF−VoutRFI=VinRin−V2Rin=V2RF−VoutRF

So,
VinRin=V2×(1Rin+1R)−VoutRFVinRin=V2×(1Rin+1R)−VoutRF

and as, V2=0V2=0
I=(Vin−0)Rin=(0−Vout)RFI=(Vin−0)Rin=(0−Vout)RF

or,
RFRin=−VoutVinRFRin=−VoutVin

The close loop gain (AclAcl) is given by :-

Acl=VoutVin=−RFRinAcl=VoutVin=−RFRin

Output voltage (VoutVout) is given by :-

Vout=−RFRin×VinVout=−RFRin×Vin

60
Non-Inverting Op-Amp

In this configuration of Op-amp the input signal is directly fed to the non inverting terminal
resulting in a positive gain and output voltage in phase with input as compared to inverting Op-
amp where the gain is negative and output voltage is out of phase with input , and to stabalize the
circuit a negative feedback is applied through a resistor(Rf) and the inverting terminal is
grounded witha input resistor(R2).This inverting Op-Amp like layout the at inverting terminal
creates a virtual ground at the summing point make the Rf and R2 a potential divider accross
inverting terminal, Hence determines the gain of the circuit.

Figure: 3

Potential difference V1V1 can be written as

V1=R2(R2+RF)×VoutV1=R2(R2+RF)×Vout

in ideal condition :V1=VinV1=Vin

SO,
Vin=R2(R2+RF)×VoutVin=R2(R2+RF)×Vout

and as we know Gain Acl=VoutVinAcl=VoutVin

Acl=VoutVin=(R2+RF)R2=1+RFR2Acl=VoutVin=(R2+RF)R2=1+RFR2
and Output Voltage (VoutVout) is given by:
Vout=[1+RFR2]∗Vin

Circuits:
Inverting:

61
Non-Inverting:

Readings:
Inverting:

Input Voltage Output Voltage Current

Serial No.
V V mA
1 -15 22.5 -0.0185
2 -13 19.5 -0.0160
3 -11 16.5 -0.0135
4 -9 13.5 -0.0111
5 -7 10.5 -0.00862

62
 6 -5 7.50 -0.00616
7 -3 4.50 -0.00369
8 -1 1.50 -0.00123
9 1 -1.50 0.00123
10 3 -4.50 0.00369
11 5 -7.50 0.00616
12 7 -10.5 0.00862
13 9 -13.5 0.0111
14 11 -16.5 0.0135
15 13 -19.5 0.0160
Non-Inverting:

Input Voltage Output Voltage Current

Serial No.
V V mA
1 -15 -37.5 NaN
2 -13 -32.5 NaN
3 -11 -27.5 NaN
4 -9 -22.5 NaN
5 -7 -17.5 NaN
6 -5 -12.5 NaN
7 -3 -7.50 NaN
8 -1 -2.50 NaN
9 1 2.50 0.00616
10 3 7.50 0.0185
11 5 12.5 0.252
12 7 17.5 0.353
13 9 22.5 0.454
14 11 27.5 0.555
15 13 32.5 0.656

Results:
Inverting:

63
Non-Inverting:

Conclusion:
Hence, we study the op amp as an inverting and non- inverting amplifier.

Precautions:
1. Connect the circuit properly.
2. Check the connection before taking the readings.
3. Take at 15 to 25 readings to plot the graph properly.

64
 Experiment 8
Objective: To study the Drain characteristics and Transfer characteristics of Junction Field
Effect Transistor.

Software Used: Virtual Labs.

Theory:
JFET (Junction Field Effect Transistor) is a three-terminal device (drain, source, gate) similar
to BJT. The difference between them is that the JFET is a voltage-controlled device, whereas
BJT is a current controlled device.

Figure 1: The Junction Field Effect Transistor

Drain Characteristics:
Whereas for BJT the relationship between an output parameter, IC, and an input parameter,
IB, is given by a constant β, the relationship in JFET between an output parameter, iD, and
an input parameter, VGS, is more complex. In the saturation region, there exists a square-law
transfer relationship.

Transconductance Characteristics:
In the transfer characteristics of a two-port network, the input parameter is changed and its
effect on the output parameter is observed. Similarly, JFET can be treated as a two-port
nonlinear network. The transfer characteristics wherein the input parameter is the voltage
across gate and source, and the output parameter is the drain current are called the
transconductance

Procedure:
1) Measuring ID versus VDS (Output Characteristics)

65
 Figure 2. JFET CS- Configuration

b) Obtain the output characteristics i.e. ID versus VDS

c) Set a particular value of voltage for VGS. Vary the voltage across drain (VDS)
from 0 to 8 V with steps of 0.5 V and measure the corresponding drain current
(ID).
d) Repeat the procedure for different values of VGS. (0V, -0.5V, -1V, -1.5V, -2V)
e) Plot the graph.

2) Measuring ID versus VGS (Transconductance Characteristics)

a) For the same circuit, obtain the transconductance characteristics. i.e. ID versus
VGS.
b) Set a particular value of voltage for VDS, i.e. 5V. Start with a gate voltage VGS
of 0 V, and measure the corresponding drain current (ID). Then decrease VGS
in steps of 0.25 V until VGS is -3V. At each step record the drain current.
c) Plot the graph with ID versus VGS using Excel or some other program.
d) Calculate the transconductance parameter from the graph assuming your VGSQ value is
-1 volts.

Experiment Readings:
Drain Characteristic:

66
 VGS Id Vds
1V(Constant) 0 0
3.43 1
4.96 2
5.53 3
5.70 4
5.72 5
5.72 6
5.69 7
5.66 8
2V(Constant) 0 0
1.5 1
1.9 2
2.1 3
2.1 4
2.1 5
2.1 6
2.1 7
2.2 8
3V(Constant) 0 0
0.2 1
0.2 2
0.2 3
0.2 4
0.3 5
0.3 6
0.3 7
0.3 8

Transfer Characteristic
VDS ID (ma) VGS
1.1 0 0
5.49 0.1
5.26 0.2
5.16 0.3
5.05 0.4
4.91 0.5
4.74 0.6
4.63 0.7
4.43 0.8
4.31 0.9
4.16 1
1.71 2.2
0.37 3.0
0.00 4
2.2V 0 0
7.87 0.1

67
 7.71 0.2
7.36 0.3
7.06 0.4
6.91 0.5
6.51 0.6
6.32 0.7
5.92 0.8
5.64 0.9
5.14 1.1
2.43 2.0
0.45 3.0
0.00 4.0

Results:
Output Characteristics of JFET:
1. ID versus VDS

2. ID versus VGS

68
Conclusion:
Hence, we study the drain characteristics and transfer characteristics of Junction Field Effect
Transistor (JFET).

Precautions:
1. Connect the circuit properly.
2. Check the connection before taking the readings.
3. Take at least 15 to 25 readings to plot the graph properly.

69
 Experiment 9
Objective: To verify the truth tables of NOT, OR, AND, NOR, NAND, XOR, XNOR gates.
Software Used: Virtual Labs.
Theory:
Logic gates are the basic building blocks of any digital system. Logic gates are electronic circuits
having one or more than one input and only one output. The relationship between the input and
the output is based on a certain logic. Based on this, logic gates are named as

1) AND gate
2) OR gate
3) NOT gate
4) NAND gate
5) NOR gate
6) Ex-OR gate
7) Ex-NOR gate

1) AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A
dot (.) is used to show the AND operation i.e. A.B or can be written as AB

Y= A.B

Figure-1:Logic Symbol of AND Gate

Figure-2:Truth Table of AND Gate

70
A simple 2-input logic AND gate can be constructed using RTL (Resistor-Transistor-Logic)
switches connected together as shown below with the inputs connected directly to the transistor
bases. Both transistors must be saturated “ON” for an output at Q.

Figure-3:AND Gate through RTL logic

2) OR gate

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are
high. A plus (+) is used to show the OR operation.

Y= A+B

Figure-4:Logic Symbol of OR Gate

Figure-5:Truth Table of OR Gate

71
OR gate can be realized by DRL (Diode-Resistance-Logic) or by TTL (Transistor-Transistor-
Logic). Presently, we will learn how to implement the OR gate using DRL (Diode-Resistance-
Logic). To realise OR gate, we will use a diode at every input of the OR gate. The anode part of
diode is connected with input while the cathode part is joined together and a resistor, connected
with the cathode is grounded. In this case, we have taken two inputs which can be seen in the
circuit below.

When both the inputs are at logic 0 or low state then the diodes D1 and D2 become reverse
biased. Since the anode terminal of diode is at lower voltage level than the cathode terminal, so
diode will act as open circuit so there is no voltage across resistor and hence output voltage is
same as ground. When either of the diodes is at logic 1 or high state then the diode
corresponding to that input is forward bias. Since this time anode is at high voltage than cathode
therefore current will flow through forward biased diode and this current then appears on resistor
causing high voltage at output terminal also. Hence at output we get high or logic 1 or +5V. So,
if any or both inputs are high, the output will be high or “1”.

Figure-6:OR Gate through DRL logic

3) NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the input at its output.
It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A.
This is also shown as A' or A with a bar over the top, as shown at the outputs.

Y= A'

72
 Figure-7:Logic Symbol of NOT Gate

Figure-8:Truth Table of NOT Gate

NOT gate can be realized through transistor. The input is connected through resistor R2 to the
transistor’s base. When no voltage is present on the input, the transistor turns off. When the
transistor is off, no current flows through the collector-emitter path. Thus, current from the
supply voltage (Vcc) flows through resistor R1 to the output. In this way, the circuit’s output is
high when its input is low.

When voltage is present at the input, the transistor turns on, allowing current to flow through the
collector-emitter circuit directly to ground. This ground path creates a shortcut that bypasses the
output, which causes the output to go low.

In this way, the output is high when the input is low and low when the input is high.

Figure-9:NOT Gate through Transistor

73
4) NAND gate

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of
all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small
circle on the output. The small circle represents inversion.

Y= AB

Figure-10:Logic Symbol of NAND Gate

Figure-11:Truth Table of NAND Gate

A simple 2-input logic NAND gate can be constructed using RTL (Resistor-transistor-logic)
switches connected together as shown below with the inputs connected directly to the transistor
bases. Either transistor must be cut-off or “OFF” for an output at Q.

Figure-12:NAND gate through RTL Logic.

74
5) NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all
NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on
the output. The small circle represents inversion.

Y= A+B

Figure-13:Logic Symbol of NOR gate

Figure-14:Truth Table of NOR gate

A simple 2-input logic NOR gate can be constructed using RTL (Resistor-transistor-logic)
switches connected together as shown below with the inputs connected directly to the transistor
bases. Both transistors must be cut-off or “OFF” for an output at Q.

Figure-15:NOR gate through RTL Logic.

75
6) Ex-OR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its two
inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation.

Y= A⊕B

Figure-16:Logic Symbol of Ex-OR gate

Figure-17:Truth Table of Ex-OR gate

Ex-OR gate is created from AND, NAND and OR gates.The output is high only when both the
inputs are different.

Figure-18:Ex-OR gate through RTL Logic.

76
7) Ex-NOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output
if either, but not both of its two inputs are high. The symbol is an EX-OR gate with a small circle
on the output. The small circle represents inversion.

Y= A⊕B

Figure-19:Logic Symbol of Ex-NOR gate

Figure-20:Truth Table of Ex-NOR gate

Ex-NOR gate is created from AND, NOT and OR gates.The output is high only when both the
inputs are same.

Figure-21: Ex-NOR gate through RTL Logic.

77
Experiment and Readings:
1. OR Gate

2. AND Gate

3. NOT Gate

78
4. NOR Gate

5. NAND Gate

79
 6. XOR Gate

7. XNOR Gate

Conclusion:
Hence, we study and verify the truth tables of NOT, OR, AND, NOR, NAND, XOR, XNOR
gates.

Precautions:
1. Connect the circuit properly.
2. Check the connection before taking the readings.
3. Take at least 15 to 25 readings to plot the graph properly.

80
 Experiment 10
Objective: To study Zener diode I-V characteristics and Zener diode as voltage regulator.
Software Used: Virtual Labs.
Theory:
A Zener Diode is a special kind of diode which permits current to flow in the forward direction
as normal, but will also allow it to flow in the reverse direction when the voltage is above the
breakdown voltage or ‘zener’ voltage.
Zener diodes are designed so that their breakdown voltage is much lower - for example just 2.4
Volts.

Figure:1

Figure:2

Function of Zener Diode

1. Zener diodes are a special kind of diode which permits current to flow in the forward
direction.
2. Zener diodes will also allow current to flow in the reverse direction when the voltage is
above a certain value. This breakdown voltage is known as the Zener voltage. In a
standard diode, the Zener voltage is high, and the diode is permanently damaged if a
reverse current above that value is allowed to pass through it.
3. In the reverse bias direction, there is practically no reverse current flow until the
breakdown voltage is reached. When this occurs there is a sharp increase in reverse
current. Varying amount of reverse current can pass through the diode without damaging
it. The breakdown voltage or zener voltage (VZVZ) across the diode remains relatively
constant. 

81
Zener Diode As A Voltage Regulator
A voltage regulator is an electronic circuit that provides a stable DC voltage independent of the
load current, temperature and AC line voltage variations. A Zener diode of break down
voltage VZVZ is reverse connected to an input voltage source VIVI across a load
resistance RLRL and a series resistor RSRS. The voltage across the zener will remain steady at
its break down voltage VZVZ for all the values of zener current IZIZ  as long as the current
remains in the break down region. Hence a regulated DC output voltage V0=VZV0=VZ is
obtained across RLRL, whenever the input voltage remains within a minimum and maximum
voltage. Basically there are two type of regulations such as:
Line Regulation: In this type of regulation, series resistance and load resistance are fixed, only
input voltage is changing. Output voltage remains the same as long as the input voltage is
maintained above a minimum value.
Load Regulation: In this type of regulation, input voltage is fixed and the load resistance is
varying. Output volt remains same, as long as the load resistance is maintained above a
minimum value.

Line Regulation

Figure:3

In Line Regulation, Load resistance is constant and input voltage varies. VIVI must be

sufficiently large to turn the Zener Diode ON.
VL=VZ=VImin×RL(RS+RL)VL=VZ=VImin×RL(RS+RL)

So, the minimum turn-on voltage VIminVImin is :

VImin=VZ×(RS+RL)RLVImin=VZ×(RS+RL)RL

The maximum value of VIVI is limited by the maximum zener current IZmaxIZmax

82
 IRmax=IZmax+ILIRmax=IZmax+IL

ILIL is fixed at :
VZRLSince,VL=VZVZRLSince,VL=VZ

So maximum VIVI is
VImax=VRmax+VZVImax=VRmax+VZ
or
VImax=IRmax×R+VZVImax=IRmax×R+VZ

For VI<VZVI<VZ,
VO=VIVO=VI

For VI>VZVI>VZ,
VO=VI−IS×RSVO=VI−IS×RS

Load Regulation

Figure:4

In Load Regulation , input voltage is constant and Load resistance varies. Too small a Load
Resistance RLRL ,will result in VTh<VZVTh<VZ and Zener Diode will be OFF.
VL=VZ=VImin×RL(RS+RL)VL=VZ=VImin×RL(RS+RL)

83
So the minimum load resistance RLRL
RLmin=VZ×RSVI−VZRLmin=VZ×RSVI−VZ

Any load resistance greater than RLminRLmin will make Zener Diode ON

IS=IL+IZIS=IL+IZ

RLminRLmin will establish maximum ILIL as

ILmax=VLRLmin=VZRLminSince,VL=VZILmax=VLRLmin=VZRLminSince,VL=VZ

VSVSis the voltage drop across RSRS

VS=VImin−VZVS=VImin−VZ

IS=VImin−VZRSIS=VImin−VZRS

For RLRL < RLminRLmin,
VO=VIVO=VI

For RLRL > RLminRLmin,
VO=VI−IS×RS

Circuit Diagram:
1. Zener characteristic

84
2. Line Regulation

3. Line Regulation (Draw Circuit)

4. Load Regulation

85
 5. Load Regulation (Draw Circuit)

Experiment Readings:
1. Zener diode characteristic

Serial No. Zener Voltage(Volt) Current(mAmp)

1 0.120 0.000
2 0.719 0.000

86
 3 1.297 0.000
4 1.841 0.000
5 2.360 0.001
6 2.865 0.001
7 3.362 0.002
8 3.853 0.002
9 4.341 0.003
10 5.100 0.002

2. Zener diode Line Regulation

Unregulated Regulated
Load Zener
Serial supply Output % Voltage
Current(IL) Current(IZ)
No. voltage(VS) Voltage(VO) Regulation
mAmp mAmp
V V
1 0 2.55 0 0 NaN
2 0.6 2.55 0 0.6 NaN
3 1.2 2.55 0 1.2 100
4 1.8 2.55 0 1.8 100
5 2.4 2.55 0 2.4 100
6 3.4 2.55 0 3.4 100
7 4.2 2.55 0 4.2 100
8 5.2 2.55 -2.450 5.10 100
9 5.8 2.55 -1.850 5.10 100
10 6.8 2.55 -0.850 5.10 83.3
11 8.4 2.55 0.750 5.10 62.5
12 9.2 2.55 1.550 5.10 55.6
13 10.2 2.55 2.550 5.10 50.0
14 10.8 2.55 3.150 5.10 50.0
15 12.4 2.55 4.750 5.10 41.7

3. Zener diode Line Regulation (Draw Circuit)

Unregulated Regulated
Load Zener
Serial supply Output % Voltage
Current(IL) Current(IZ)
No. voltage(VS) Voltage(VO) Regulation
mAmp mAmp
V V
1 0 2.55 0 0 NaN
2 0.8 2.55 0 0.8 NaN

87
3 1.8 2.55 0 1.8 100
4 3 2.55 0 3 100
5 3.2 2.55 0 3.2 100
6 4.4 2.55 0 4.4 100
7 5.2 2.55 -2.450 5.10 100
8 6.8 2.55 -0.850 5.10 83.3
9 7.2 2.55 -0.450 5.10 71.4
10 8.4 2.55 0.750 5.10 62.5
11 9 2.55 1.350 5.10 55.6
12 10.4 2.55 2.750 5.10 50.0

4. Zener diode load regulation

Load Load Zener Regulated Output

Serial % Voltage
Resistance(RL) Current(IL) Current(IZ) Voltage(VO)
No. Regulation
Ohm mAmp mAmp V
1 150 34.0 0 6 40.0
2 250 20.4 0 6 28.6
3 350 14.6 0 6 22.2
4 433 11.8 0 6 18.8
5 561 9.09 0 6 15.1
6 625 8.16 0.840 5.10 13.8
7 745 6.85 2.15 5.10 11.8
8 809 6.30 2.70 5.10 11.0
9 910 5.60 3.40 5.10 9.90
10 983 5.19 3.81 5.10 9.23
11 1047 4.87 4.13 5.10 8.72
12 1102 4.63 4.37 5.10 8.32
13 1175 4.34 4.66 5.10 7.84
14 1231 4.14 4.86 5.10 7.51
15 1250 4.08 4.92 5.10 7.41

5. Zener diode load regulation (Draw Circuit)

Regulated
Load Load Zener
Serial Output % Voltage
Resistance(RL) Current(IL) Current(IZ)
No. Voltage(VO) Regulation
Ohm mAmp mAmp
V
1 150 34.0 0 6 40.0
88
2 192 26.6 0 6 34.2
3 273 18.7 0 6 26.8
4 363 14.0 0 6 21.6
5 445 11.5 0 6 18.3
6 542 9.41 0 6 15.6
7 567 8.99 0.00529 5.10 15.0
8 640 7.97 1.03 5.10 13.5
9 746 6.84 2.16 5.10 11.8
10 836 6.10 2.90 5.10 10.7
11 901 5.66 3.34 5.10 9.99
12 974 5.24 3.76 5.10 9.31
13 1039 4.91 4.09 5.10 8.78
14 1121 4.55 4.45 5.10 8.19
15 1162 4.39 4.61 5.10 7.92

Results:
1. Zener Characteristic

2. Line Regulation

89
3. Line Regulation (Draw Circuit)

4. Load Regulation

5. Load Regulation (Draw Circuit)

90
Conclusion:
Hence, we study Zener diode I-V characteristics and Zener diode as voltage regulator.

Precautions:
1. Connect the circuit properly.
2. Check the connection before taking the readings.
3. Take at least 15 to 25 readings to plot the graph properly.

91