ECE467: Introduction to VLSI

Lecture-4

Physical Structure and Fabrication Process of Integrated Circuits

Masud H. Chowdhury
Electrical and Computer Engineering
University of Illinois at Chicago
 Integrated Circuit from Physical Perspectives
– An Integrated Circuit is a collection of patterned material
(semiconductor, metal and insulator) layers
– IC fabrication involves stacking of these material layers in a specific
order to form a three-dimensional structure that collectively act as an
electronic switching network
– Each layer, having its specific conduction and physical properties, is
patterned following specific design rules
• Physical layout of an IC can be understood from two perspectives:
– The cross-section, obtained by slicing the wafer through the middle
of transistor and looking at it edgewise
• Different parts or layers of an IC can be easily defined from this point of
view
– The top view, obtained by looking down on the wafer
• From the top view of an IC a set of masks used to manufacture different
parts can be defined
• The size of transistors and wires is set by the mask dimensions and is
limited by the resolution of manufacturing process
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 The Layers or Parts of Integrated Circuits
• Wafer and substrate:
– The base material of IC fabrication comes in the form of a single-
crystalline, lightly doped wafer with typical diameter of 4 and 12
inches and thickness of 1 mm
– A number of identical ICs are manufactured on to a single wafer
– This bulk semiconductor on which semiconductor devices are
fabricated is called the body or the substrate. It is the lowest layer of
the IC cross-section, and it serves as both
• A mechanical support and
• An electrical common point

Single die

Going up to 12” (30cm)

Wafer

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 The Layers or Parts of Integrated Circuits
• Well: Special regions on the substrate to accommodate both types of
devices in CMOS process
– n-well CMOS process: Here the NMOS devices are fabricated on the
p-type substrate, and the PMOS devices are fabricated on the n-well
– p-well CMOS process: Here the PMOS devices are fabricated on the
n-type substrate, and the NMOS devices are fabricated on the p-well
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

• Diffusions: These are heavily doped regions formed on the substrate or

well as source and drain of the MOSFET device
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 The Layers or Parts of Integrated Circuits
• Channel: The channel is the region or portion of the substrate or well below the
gate and between the source and drain
– The minimum length of this channel defines the technology generation
– In current technology generation ICs below 100 nanometer channel length is
possible
– By 2012 this length can go down to 30 nanometer
• Contact: A contact forms interconnection between metal and active or polysilicon
– There are various contacts in an IC, such as, gate, drain, source, body contacts
– Contacts are provided normally with metals like tungsten or polysilicon
• Insulation Layers: This layers provide physical and electrical separation among
different parts of integrated circuits
– Typically SiO2 is widely used as insulator
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
5
nMOS transistor pMOS transistor
 The Layers or Parts of Integrated Circuits
• Interconnect Lines: These are wires that provide connections among
different terminals of the transistors; internal parts and blocks of the IC;
and the IC and the external environment
– There are multiple layers of interconnect in an IC
– Typically interconnect lines are of polysilicon
at the lowest level, and of aluminum or copper
at the higher levels
• Via: In current ICs there are multiple layers
of interconnect lines are required. Vias
connect metal interconnect lines on
different layers
– Typically Vias are of same metal like the
interconnect lines

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 IC Fabrication Process
Manufacturing Process:
– An operational IC or silicon chip is the outcome of a series of
manufacturing steps
– A set of masks are used to transfer the design of an IC onto silicon by
lithographic process
– Masks and lithographic processes convert an IC from “soft” to “hard”
form
– The resolutions and efficiency of these masks and lithographic
techniques determine the physical constraints imposed on the chip and
circuit designers, as well as the cost of an IC
Photolithography:
– The technique to transfer a pattern to a layer on a chip by selective
masking is called lithography
– In IC fabrication process the masking is optical, and that’s why it is
called photolithography
– In IC fabrication flow the photolithographic process is applied again
and again to develop different patterned layers
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 IC Fabrication Process
• Optical mask:
– In each step a certain area is defined on chip by appropriate masks so
that a desired processing step can be selectively applied to that
particular region.
– Some parts of these masks are transparent and some parts of them are
opaque to prevent UV lights from entering the material under them
– These optical masks forms the central interface between the
manufacturing process and the design that need to be transferred on
the chip.
– The cost and the resolution of these masks often limit maximum speed
and complexity achievable in an IC
• Design Rule:
– The masks define the patterns of different layers of semiconductor
material to form the elements of an IC
– These patterns have to adhere to some constraints, in terms of
minimum dimensions and spacing, for a chip to be functional
– This collection of constraints is called design rules that act as the
contract between the circuit designer and the process engineer
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 The Process Flow of Photolithography
• Oxidation:
– This step deposits a thin layer of SiO2 over the complete wafer by
exposing it to a mixture of high-purity oxygen and hydrogen
– The oxide layer is used as insulation layer and forms transistor gates

• Photoresist Coating:
– A light sensitive layer polymer of 1 micro-meter thickness evenly
applied on the whole wafer
• Negative photoresist: Normally soluble in organic solvent. But become
insoluble when exposed to light.
• Positive photoresist: Normally insoluble in organic solvent. But become
soluble when exposed to light
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 The Process Flow of Photolithography
• Steeper Exposure:
– A glass mask with pre-defined pattern that need to be transferred to the
silicon is placed very closed to the wafer
– The mask is opaque in the regions that we want to process, and
transparent in other regions
– The mask and wafer is then exposed to UV light
– The photoresist under the transparent region becomes insoluble if
negative photoresist used, or soluble if positive photoresist used

• Photoresist development and bake:

– The wafers are developed in either acid or base solution to remove the
non-exposed photoresist
– Once those photoresist are removed, the wafer is “soft baked” in low
temperature to harden remaining photoresist
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 The Process Flow of Photolithography
• Acid Etching:
– In this step materials are selectively
removed from the regions not covered by
photoresist
– The types of acid, base and caustic
solutions used in this step depend on the
nature of the materials to be removed
• Spin, Rinse, and Dry:
– After every processing step the wafer
needs to be cleaned to avoid contamination
and to remove the leftovers from previous
step.
– A special tool named SRD is used to clean
the wafer with deionized water, and dry
nitrogen. A glass mask with pre-defined
pattern that need to be transferred to the
silicon is placed very closed to the wafer
– Ultra clean rooms and robotics are used
for processing and handling of the wafer
• Photoresist Removal or Ashing
– A high-temperature plasma is used to
selectively remove the remaining
photoresist without damaging device
layers
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 Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2 (d) After development and etching of resist,
chemical or plasma etch of SiO
Si-substrate 2

(b) After oxidation and deposition Hardened resist

of negative photoresist SiO
2
Si-substrate
UV-light
Patterned (e) After etching
optical mask

Exposed resist
SiO
2

Si-substrate Si-substrate

(f) Final result after removal of resist

(c) Stepper exposure

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 The Process Flow of Photolithography
• Recurring Process Steps
– After pattering of SiO2 the exposed area can now be subject to a wide
range of process steps
– In these recurring process steps wells, drain, source, and various other
regions on the substrate are defined by appropriate doping; and
necessary gates, contacts and separating insulations are provided by
appropriate depositions
– The recurring process steps are as follows:
• Implantation
– Diffusion
– Ion implantation
• Deposition
• Plasma Etching
• Planarization

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 Recurring Process Steps
• Implantation
– In IC manufacturing process a change in the dopant density is required in
many parts of the materials to create source, drain, well, and substrate
contacts; to dope polysilicon; and to adjust device threshold.
– Two approaches exist for introducing these dopants
• Diffusion
– In this techniques a gas containing dopant is introduced over the
exposed surface at very high temperature. The dopants diffuse into
the exposed surface both horizontally and vertically. The final dopant
concentration is the highest at the surface and decreases gradually
deeper in the material.
• Ion Implantation:
– In this technique atoms are first ionized in a closed chamber. An
accelerated and purified beam of ions is directed over the exposed
semiconductor surface. The first moving ions are literally smashed
into the material at typical energies around 100-200 keV.
– Acceleration of ions determines the depth of ion penetration, while
beam current and exposure time determines the dosage.
– It is more preferable than diffusion, because this technique allow an
independent control of depth and dosage.
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 Recurring Process Steps
• Annealing:
– The damage done during ion implantation is largely recovered by heating the
wafer to around 1000 degree centigrade and then allowed to cool slowly. The
heating step thermally vibrates the atoms, which allows the bond to reform,
and set the dopants into the proper locations within the crystal lattice.
• Deposition:
– Buffer materials deposition
• CVD - Chemical Vapor Deposition
– Insulating layers
• Oxidation
– Conducting layers
• Polysilicon
– Chemical deposition process
• Aluminum interconnect layers
– Sputtering

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 Recurring Process Steps
• Plasma Etching
– After material deposition dry or plasma etching is used to selectively
remove unwanted materials and form patters of interconnect and
contact holes
– It is different from wet etching used to etch SiO2
– It has the advantage of offering well-defined directionality to the
etching action, creating patterns with sharp vertical contours

• Planarization: CMP- Chemical-Mechanical Planarization

– It is essential to have a flat surface to reliably deposit a layer of
material on that surface
– A CMP step is included before depositing each layer of interconnect
on top of SiO2 layer
– CMP process microscopically planes a device layer and reduces the
step heights.

• Photoresist Removal or Ashing:

– A high-temperature plasma is used to selectively remove the
remaining photoresist without damaging device layers

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 Fabrication Steps of a CMOS Inverter

In next 21 slides the complete sequence of CMOS Inverter

fabrication steps are illustrated to recap what we have
discussed so far

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 Inverter Cross-section
VDD
• Typically use p-type substrate for nMOS
transistors
• Requires n-well for body of pMOS
transistors
A Y

A
GND
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

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 Well and Substrate Taps

• Substrate must be tied to GND and n-well to VDD

• Metal to lightly-doped semiconductor forms poor connection called
Shottky Diode
• Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

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 Inverter Mask Set
• Transistors and wires are defined by masks
• Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

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 Detailed Mask Views
n well

• Six masks
– n-well
Polysilicon

– Polysilicon
– n+ diffusion n+ Diffusion

– p+ diffusion p+ Diffusion

– Contact Contact

– Metal

Metal

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 Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

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 Oxidation

• Grow SiO2 on top of Si wafer

– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

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 Photoresist

• Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

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 Lithography

• Expose photoresist through n-well mask

• Strip off exposed photoresist

Photoresist
SiO2

p substrate

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 Etch
• Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

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 Strip Photoresist

• Strip off remaining photoresist

– Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step

SiO2

p substrate

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 n-well
• n-well is formed with diffusion or ion implantation
• Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
• Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2

n well

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 Strip Oxide

• Strip off the remaining oxide using HF

• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

n well
p substrate

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 Polysilicon

• Deposit very thin layer of gate oxide

– < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

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 Polysilicon Patterning

• Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

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 Self-Aligned Process

• Use oxide and masking to expose where n+ dopants should

be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well contact

n well
p substrate

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 N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates because it doesn’t
melt during later processing

n+ Diffusion

n well
p substrate

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 N-diffusion cont.

• Historically dopants were diffused

• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+
n well
p substrate

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 N-diffusion cont.

• Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate

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 P-Diffusion

• Similar set of steps form p+ diffusion regions for pMOS

source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

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 Contacts

• Now we need to wire together the devices

• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+
n well
p substrate

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 Metalization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

M e ta l

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

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