ECE467: Introduction to VLSI

Lecture-3

Properties of MOSFET (Metal Oxide Field

Effect Transistor)

Masud H. Chowdhury
Electrical and Computer Engineering
University of Illinois at Chicago
 Field Effect Transistor (FET)
• The basic idea that underlies the operation of a FET is simple:
– Start with a resistor and add a third terminal (the gate) that somehow
allows modulation of the resistance/conductivity between the other two
terminals (the source and the drain)
– The control is effected by altering the extent of the depletion region or
inducing charge of opposite polarity in the semiconductor
• FET as compared to Bipolar Junction Transistor:
– FETs perform very well as a switch
– FETs have few parasitic effects compared to BJTs
– FETs have relative smaller area per device
– Higher integration density is achievable with FETs
– Fewer processing steps are required for FETs fabrication
– The operation of FETs is relatively simple
– Power gain is the most dominant factor for choosing FETs over BJTs
• Types of FET:
– Junction Field Effect Transistors (JFET)
– Metal Oxide Field Effect Transistor (MOSFET)

M. Chowdhury @ UIC ECE467 @ Fall2005 2

 Basic Features of MOSFET
• MOSFET is a four terminal device
– Gate (G): This terminal controls the conductivity of the channel
– Source (S): This terminal collects the charge carriers that form current
– Drain (D): Charge carriers leave the device through this terminal
– Body or Substrate (B): This terminal serves to modulate the device
characteristics and parameters. It doesn’t directly take part in current
conduction of the device
• Types of MOSFET:
– NMOS (N-channel MOSFET): Built on a p-type body or substrate
– PMOS (P-channel MOSFET): Built on an n-type body or substrate
Source Gate Drain Source Gate Drain
Polysilicon

SiO2

n+ n+ p+ p+
p bulk Si n bulk Si

M. Chowdhury @ UIC ECE467 @ Fall2005 3

 MOSFET as Switches
• We can view MOS transistors as electrically controlled switches
• Voltage at gate controls path from source to drain

g=0 g=1

d d d

nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

M. Chowdhury @ UIC ECE467 @ Fall2005 4

 Operation of a MOSFET
• NMOS Transistor:
– An NMOS transistor consists of two heavily doped n-type regions - source
and drain that comprise the main terminals of the device
– The gate is typically made of metal, but now it is made of polysilicon
– The body is relatively lightly doped as compared to source and drain
– Normally substrate terminal is at the same potential of the source terminal
• Long channel approximation
– By “long channel” we mean “low electric field” across the channel
– The length of the channel is larger as compared to the width of the device
– The current is assumed to be along the channel length from source to drain
– The applied voltage is small enough to ensure low electric field

oBody is commonly tied to ground (0 V)

oWhen the gate is at a low voltage:
oP-type body is at low voltage
oSource-body and drain-body diodes are OFF
oNo current flows, transistor is OFF
M. Chowdhury @ UIC ECE467 @ Fall2005 5
 Operation of a MOSFET

channel or inversion layer

• Depletion: When a low positive is applied to the gate, resulting in some positive
charge on the gate, the holes in the body directly beneath the gate are repelled
downward. With an increasing positive voltage, all the holes are progressively
repelled away from the surface of the substrate, resulting in a depletion region
forming below the gate.
• Threshold Voltage: The gate voltage when the surface becomes completely depleted
of charge is called the threshold voltage (Vt). It depends on
– Doping density of the body
– Thickness of the gate oxide
• Inversion: With further increase on gate voltage beyond Vt electrons from source,
drain and body region gather in the surface region and form a conducting path
(“channel”) from source to drain. Since the property of this channel region becomes
opposite that of the rest of the body region this phenomenon is called inversion, and
the layer of electrons from source to drain is called inversion layer. When gate
voltage is several times of Vt, the device is said to be in strong inversion
M. Chowdhury @ UIC ECE467 @ Fall2005 6
 MOSFET Operation
• Channel Charge Density:
– In previous discussion we assumed that the potential across the semiconductor
surface is constant, that is zero drain-to-source voltage
– With this assumption the induced inversion charge is proportional to the gate
voltage above the threshold voltage, and the induced charge density along the
channel is constant
– If a positive drain-to-source voltage (Vds) is applied, the channel potential
increases from zero at the source end to Vds at the drain-end
– The net voltage available to induce an inversion layer therefore decreases as one
approaches the drain-end of the channel from the source-end.
– The channel charge density thus changes over the channel from the maximum at
the source-end to the minimum at the drain-end

M. Chowdhury @ UIC ECE467 @ Fall2005 7

 MOSFET Operation
• Pinch-off Condition:
– With a positive Vds the net voltage available to induce an inversion layer decreases from the
source-end to the drain-end
– The net voltage available at any point at the surface of the body to induce an inversion layer
is given by Vgs – V(y) - Vt, where V(y) is the voltage at any point y along the channel
– With the increase of Vds the net voltage available to induce an inversion layer becomes zero
at the drain-end at a certain stage when Vgs – Vds – Vt = 0
– At this stage the channel at the drain-end disappears. That is, the channel is pinched off at
the drain-end.
– Beyond this pinched-off point the channel does not completely extend from source to drain
– The drain voltage when pinch-off occurs is called saturation voltage (Vdsat), which is given
by Vdsat = Vgs –– Vt

Channel is pinched-off when Vds = Vdsat = Vgs –– Vt

M. Chowdhury @ UIC ECE467 @ Fall2005 8

 MOSFET Operation
• Gate-Channel Capacitance
Cgc = εoxWL/tox = CoxWL = CpermicronW
Here, Cox is the capacitance per unit area of channel region = εox/tox
εox is the permittivity of silicon di-oxide
tox is the thickness of the oxide

polysilicon
gate C = εA/d
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, εox = 3.9ε0)
p-type body

M. Chowdhury @ UIC ECE467 @ Fall2005 9

 MOSFET Operation
Regions of MSFET Operation:
• Cutoff or subthreshold region: When the gate-source voltage Vgs is smaller than the
threshold voltage Vt , and both the source and the body are connected to ground with
no voltage applied to the drain, the junctions between the body and the source or
drain are reversed biased and there is no conducting channel from source to drain. So
almost no current flows. This mode of operation is called cutoff mode of operation
• Linear or nonsaturation region: When the gate-source voltage Vgs is larger than the
threshold voltage Vt, while the drain voltage is smaller than the drain saturation
voltage Vdsat, a continuous conducting channel from source to drain exists, and a
current Id proportional to Vds flows. This mode of operation is called linear or
resistive mode of operation
• Saturation region: When the gate-source voltage Vgs is larger than the threshold
voltage Vt, while the drain voltage is larger than the drain saturation voltage Vdsat, the
conducting channel disappears from the drain-end. At this stage current Id becomes
almost independent of drain voltage Vds. This mode of operation is called saturation
mode of operation

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 Ideal I-V Characteristics of MOSFET
• To compute currents we need to know the amount of charge in the channel and
the rate at which it moves
• Channel Charge Density: Channel charge density at point y can be given by:
Qy = Cox(Vgc – Vt)

Here, V(y) is the channel potential at position y, amount of voltage attracting

charge to the channel Vgc = Vgs – V(y), where the y-direction is defined along
the channel. The minus sign implies that the charge is made up of electrons in
NMOS
VGS VDS
S
G ID
D
n+ – V(y) + n+ MOS transistor and
its bias conditions
L y

p-substrate
B

M. Chowdhury @ UIC ECE467 @ Fall2005 11

 Ideal I-V Characteristics of MOSFET
• The current between source and drain is the total charge in the channel divided
by the time required to cross the channel: ID = Q/t
• Total Channel Charge: Q = WLQn(y) = - WLCox{[Vgs – V(y)] – Vt}
• The time required to cross the channel: t = L/v
• Here W is the width of the device and L is the length of the channel
• The velocity of the charge carrier at low filed is simply the product of carrier
mobility and electric filed: v = μnE
• Therefore, the current can be given by:

VGS VDS
S
G ID
D
n+ – V(y) + n+ MOS transistor and
its bias conditions
L y

p-substrate
B
M. Chowdhury @ UIC ECE467 @ Fall2005 12
 Ideal I-V Characteristics of MOSFET
S VGS VDS
G ID
D

n+ – V(y) + n+

L y

p-substrate

Drain Current in the Linear (Triode) region:

– Linear region of operation is defined as one in which Vgs is large enough
compared to Vds to guarantee the formation of an inversion layer the whole
distance from source to drain
– Channel charge is zero when:
– The charge density thus first becomes zero at the drain end at some
particular voltage. The boundary for the linear region is defined by:

– As long as Vds is smaller than VDSAT, the device is in linear region

– Therefore, condition for linear operation is Vds < Vgs – Vt = VDSAT
M. Chowdhury @ UIC ECE467 @ Fall2005 13
 Ideal I-V Characteristics of MOSFET
Drain Current in the Linear (Triode) region:
– The current from drain to source is given by:
– The electric field along y-direction is simply (minus) the gradient of the
voltage along the channel. Therefore,

– Now integrating along the channel for y=0 to y=L, and solve for ID we get

– For small Vds the square quantity is even smaller. Hence the relation between
drain current and drain-to-source voltage is nearly linear
– Therefore, a MOSFET in linear region behaves as a voltage control resistor
– The strong sensitivity of drain current to drain voltage is qualitatively similar
to the behavior of vacuum tube triodes, that’s why this region of operation is
also called triode region

M. Chowdhury @ UIC ECE467 @ Fall2005 14

 Ideal I-V Characteristics of MOSFET
Drain Current in the Saturation region:
– In the previous discussion we found that the boundary of linear region of
operation is
– If Vds is large enough so that the channel charge at the drain end is zero,
the inversion layer does not extend all the way from source to drain, then
the channel is said to be “pinched off”.
– In this case the channel charge ceases to increase, causing the total current
to remain constant despite increasing Vds
– The drain voltage at which the current becomes constant or saturated is
called saturation voltage Vdsat as defined by the above boundary condition
– Therefore, the condition for the transistor in saturation region of operation
is Vds >= Vgs – Vt = VDSAT
– By substituting Vdsat for Vds in the current expression we get

– Hence in saturation the drain current has square-law dependence on the

gate-source voltage
– Drain current is independent of drain voltage
M. Chowdhury @ UIC ECE467 @ Fall2005 15
 Summary of NMOS Operation
Cut-off Region:
– When Vgs is smaller than the threshold voltage, no conduction channel is
formed in the MOSFET, and no current flows through the channel
ID = 0 for Vgs ≤ Vt …….. MOSFET is OFF
Linear Region:
– For Vgs > Vt and Vds < (Vgs – Vt) the MOSFET is in linear region of
operation and drain current is given by

Pinch-off Condition:
– For Vgs > Vt and Vds = (Vgs – Vt) = Vdsat the MOSFET is “pinched off”
condition, and is at the boundary between linear and saturation region of
operation
Saturation Region:
– For Vgs > Vt and Vds ≥ (Vgs – Vt) = Vdsat the MOSFET is in saturation
region of operation, and drain current is given by

M. Chowdhury @ UIC ECE467 @ Fall2005 16

 Ideal I-V Characteristics of MOSFET
-4
x 10
6
VGS= 2.5 V

Resistive Saturation
4
VGS= 2.0 V
ID (A)

3 Quadratic
VDS = VGS - VT Relationship
2
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

M. Chowdhury @ UIC ECE467 @ Fall2005 17

 Summary of MOSFET Operation: PMOS
• Similar, but doping and voltages reversed Polysilicon Source Gate Drain

– Body tied to high voltage (VDD) SiO2

– Gate low: transistor ON

– Gate high: transistor OFF p+ p+

n
– Bubble indicates inverted behavior bulk Si

Cut-off Region: When Vsg is smaller than the magnitude of the threshold voltage, no
conduction channel is formed in the MOSFET, and no current can flows through
the channel. For Vsg ≤ |Vt| …….. MOSFET is OFF
Linear Region: For Vsg > |Vt| and Vsd ≤ (Vsg – |Vt|) the MOSFET is in linear region of
operation and drain current is given by
Pinch-off Condition: For Vsg > |Vt| and Vsd = (Vsg – |Vt|) = Vdsat the MOSFET is
“pinched off” condition, and is at the boundary between linear and saturation
region of operation
Saturation Region: For Vsg > |Vt| and Vsd ≥ (Vsg – |Vt|) = Vdsat the MOSFET is in
saturation region of operation, and drain current is given by
M. Chowdhury @ UIC ECE467 @ Fall2005 18
 Problem
• Consider an NMOS transistor in 180 nm process
– W/L = 4/2
– Gate oxide thickness = 40 Å
– Mobility of electrons = 180 cm2/V.s at 700C
– The threshold voltage = 0.4V
– Gate-to-source voltage = 1.8V
Find Ids for Vds= 1.2 and 1.6V

Solution:
– For Vds= 1.2V:
• Vds< Vgs- Vtn= 1.8 – 0.4 = 1.4. The NMOS is in linear region of
operation
– For Vds= 1.6V:
• Vds> Vgs- Vtn= 1.8V – 0.4V = 1.4V. The NMOS is in saturation region
of operation

M. Chowdhury @ UIC ECE467 @ Fall2005 19

 Comparison of NMOS and PMOS transistor
• NMOS is a good pull down device
– Let us consider that the capacitor is holding a logic high value or Vdd initially
– We want to pull down the voltage to logic low or 0 volt through the NMOS device
– To pull down the capacitor voltage the source of the NMOS is connected to ground
– To turn ON the NMOS we have to apply Vdd at the gate
– Initially Vgs = Vdd and Vds = Vdd
– A current Ids flows from drain to source and voltage across the capacitor decreases
gradually. At the same time Vds also decreases
– The current is initially equal to saturation current (Vds > Vgs – Vt), but later current
becomes linear (Vds < Vgs – Vt) and decreases with Vds
– Here, Vgs remains constant at Vdd, therefore the transistor remains ON for the whole
transition (since Vgs > Vt) and the voltage across the capacitor go down all the way to 0
volt or perfect logic low value

Vdd
g Initially Vdd
0 Vgs = Vdd

s d Ids

CL

Vds
M. Chowdhury @ UIC ECE467 @ Fall2005 20
 Comparison of NMOS and PMOS transistor
• NMOS is a bad pull up device
– Let us consider that the capacitor is holding a logic low value or 0 volt initially
– We want to pull up the voltage to logic high or Vdd through the NMOS
– The drain of the NMOS is connected to Vdd to pull up the capacitor voltage
– To turn ON the NMOS we have to apply Vdd at the gate
– Initially Vgs = Vdd and Vds = Vdd
– Ids flows from drain to source, and voltage across the capacitor (VCL) increases gradually.
– Here, both Vds and Vgs decrease gradually as capacitor voltage increases
– The current gradually decreases with the decreases of Vds and Vgs and follow lower curves
– For the transistor to remain ON, Vgs must be greater than Vt. But Vgs decrease gradually
with the increase of the capacitor voltage, since Vgs = Vdd – VCL
– When VCL = Vdd – Vt the transistor becomes OFF, since Vgs = Vdd – VCL = Vdd – (Vdd – Vt)
= Vt. Beyond that point the capacitor voltage can not go up further.
– Therefore, NMOS transistor can pull capacitor voltage up to a maximum level of VCL =
Vdd – Vt . Hence NMOS transistor is a bad pull up device due to threshold voltage loss
2.5
Vdd Vgs = 5

g Initially 0 volt
2
Vdd
1.5 Vgs = 4
Ids (mA)

d s
1
CL Vgs = 3
0.5
Vgs = 2
Vgs = 1
21
0
0 1 2 3 4 5
V
 Comparison of NMOS and PMOS transistor
• PMOS is a good pull up device
– Let us consider that the capacitor is holding a logic low value or 0 volt initially
– We want to pull up the voltage to logic high or Vdd volt.
– To pull up the capacitor voltage the source of the PMOS is connected to Vdd
– To turn ON the PMOS we have to connect the gate to ground or 0 volt
– Initially Vsg = Vdd and Vsd = Vdd
– Ids flows from source to drain, and voltage across the capacitor (VCL) increases gradually.
At the same time Vsd decreases
– The current is initially equal to saturation current (Vsd > Vsg – |Vt|), but later current
becomes linear (Vsd < Vsg – |Vt|), and decreases with Vsd
– Here, Vsg remains constant at Vdd, therefore the transistor remains ON for the whole
transition (since Vsg >|Vt|), and the voltage across the capacitor can go up all the way to
Vdd or perfect logic high value
– Therefore, PMOS is very good pull up device

0 Vsg = Vdd
g VCL = Initially 0 volt
Vdd
Ids

s d
CL
Vsd
22
 Comparison of NMOS and PMOS transistor
• PMOS is a bad pull down device
– Let us consider that the capacitor is holding a logic high value or Vdd initially
– We want to pull down the voltage to logic low or 0 volt.
– To pull down the capacitor voltage the drain of the PMOS is connected to ground or 0 volt
– To turn ON the PMOS we have to connect the gate to ground or 0 volt
– Initially Vsg = Vdd and Vsd = Vdd
– Ids flows from source to drain, and voltage across the capacitor (VCL) decreases gradually.
– Here both Vsg and Vsd decrease gradually with the decrease of the capacitor voltage
– The current gradually decreases with the decreases of Vsd and Vsg and follow lower curves
– For the transistor to remain ON, Vsg must be greater than |Vt|. But Vsg decrease gradually
with the decrease of the capacitor voltage, since Vsg = VCL
– When VCL = |Vt|, the transistor becomes OFF, since Vsg = VCL = |Vt|. Beyond that point the
capacitor voltage can not go down further.
– Therefore, PMOS transistor can pull capacitor voltage down to a minimum level of VCL =
|Vt|. Hence PMOS transistor can not produce perfect logic low value and is a bad pull
2.5
down device due to threshold voltage loss V =5 sg

0 2
g VCL = Initially Vdd 1.5
0 Vsg = 4
Ids (mA)

1
d s Vsg = 3

CL 0.5
Vsg = 2
Vsg = 1
0 23
0 1 2 3 4 5
Vsd
 Dynamic Behavior of MOSFET
• The dynamic response of a MOSFET transistor is solely a function of the time
it takes to charge or discharge the intrinsic parasitic capacitance and the extra
capacitance introduced by the interconnect and load
• Each terminal of an MOS transistor has capacitance to the other terminals
• These capacitances limit the high frequency performance of the circuits
• The intrinsic parasitic capacitances come from three major sources:
– MOS structure
– The channel charge
– The reverse biased pn- junction of source and drain
• Aside from the MOS structure capacitances all capacitances are nonlinear and
vary with applied voltage, which makes them difficult to analyze
G

CGS CGD

S D

CSB CGB CDB

M. Chowdhury @ UIC ECE467 @ Fall2005 B 24

 MOS Structure Capacitance
Gate Capacitance (Cg):
• The gate of a MOSFET is separated from the channel by a thin oxide, which has a
per unit area capacitance equal to Cox = εox/tox
• The total value of this capacitance is the gate capacitance (Cg), which can be
decomposed into two elements
– Intrinsic capacitance (Cgc) between gate and channel, which contributes to
channel charge
– Gate overlap capacitance (Cov): due to overlap with the source and drain
Gate-to-Channel Capacitance:
• The intrinsic capacitance due to MOS gate and channel structure can be
approximated as a simple parallel plate capacitance given by Cgc = CoxWL
• However, the bottom plate of this capacitor depends on the mode of the operation
of the transistor
polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, εox = 3.9ε0)
p-type body

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 MOS Structure Capacitance
Gate-to-channel Capacitance (Cgc):
– This is the most significant MOS parasitic element,
– It varies in both magnitude and in its division, depending on the operation region
and terminal voltage
– The three components are
- Gate-to-body (Cgcb) - Gate-to-source (Cgcs) - Gate-to-drain (Cgcd)
– In the cut-off region when there is no channel, the total capacitance Cgc appears
between gate and body. Hence Cgc = Cgcb = CoxWL
– In linear region a conducting channel from source to drain shields the body from
the gate. Consequently Cgcb = 0. Symmetry dictates that the capacitance is
evenly distributed between drain and source. Hence Cgcs = Cgcd = CoxWL/2
– In saturation the channel is pinched-off at the drain end. The capacitance
between gate and drain is approximately zero, and so is the gate-body
capacitance. All the capacitance is therefore between gate and source, which is
approximately given by: Cgcs = (2/3)CoxWL
G G G

CGC CGC CGC

S D S D S D
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 MOS Structure Capacitance
Gate Overlap Capacitance (Cov):
• Ideally, the source and drain diffusion should end right at the edge of the gate.
In reality, both source and drain tend to extend somewhat below the gate oxide
by an amount xd, called lateral diffusion.
• As a result the effective channel length L is reduced by an amount ΔL = 2xd.
• This overlap of gate with source and drain gives rise to a parasitic capacitance
between gate and source (and drain) that is called overlap capacitance (Cov)
• This capacitance is linear and has a fixed value
• This capacitance is mainly a parallel-plate capacitance. But it is augmented by
fringing
Polysilicon gate C =C =C =C x W
ov gso gdo ox d
Gate oxide
tox
n+ L n+
Source Drain
W
n+ xd xd n+ Cross section

Gate-bulk
Ld
overlap
Top view
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 MOSFET Gate Capacitance
Approximation of Gate-to-Channel Capacitance
Parameter Cutoff Linear Saturation
Cgb CoxWL 0 0
Cgs 0 CoxWL/2 (2/3)CoxWL
Cgd 0 CoxWL/2 0
Cg = Cgb+Cgs+Cgd CoxWL CoxWL (2/3)CoxWL

Approximation of Gate Overlap Capacitance

Cgso Cox.xdW
Cgdo Cox.xdW

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 MOSFET Diffusion or Junction Capacitance
• There are two reverse biased pn-junctions in a MOSFET
– source-body pn junction VGS VDS
S
– drain-body pn junction G
D D
I
• Both junctions contribute capacitance
n+ n+
• These are parasitic capacitance, since
these capacitances are not fundamental
to device operation, but do impact circuit p-substrate
performance.
• Since they arise between the source or drain diffusion and the body, they are
called diffusion capacitance.
• Since they are formed at the pn-junctions of source or drain and body, they are
also called junction capacitance.
• The size of these junctions as well as the value of these capacitance depend on
– The area and perimeter of the source and drain diffusion
– The depth of the diffusion
– The doping level
– The terminal voltages

M. Chowdhury @ UIC ECE467 @ Fall2005 29

 MOSFET Diffusion or Junction Capacitance
• There are two components of junction capacitance, resulting from two
junctions
– Bottom plate junction capacitance
– Sidewall junction capacitance
• To understand the components of the junction capacitance, the structure
and the surroundings of source or drain region must be examined in
detail
• Drain and source junctions are similar from structural point of view.
Therefore, calculation of junction capacitances for any of these two pn
junctions is sufficient Channel-stop implant
N A+

Side wall
Source
W
ND
Bottom

xj Side wall
Channel 30
LS Substrate N A
 MOSFET Diffusion or Junction Capacitance
• The bottom plate junction is formed between the source with doping ND and
the substrate with doping NA. Cj is the unit junction capacitance per unit area.
The area of the bottom plate is LS.W
• The side-wall junction, formed by the source region and the p+ channel-stop
implant with doping NA+. Cjsw is the capacitance per unit perimeter.
• In the calculation of sidewall perimeter, the fourth side is not counted, as this
side represents the conducting channel Channel-stop implant
NA+

Side wall
Source
W
ND
Bottom

xj Side wall
Channel
LS Substrate N A

31
 Threshold Voltage

Here, VT0 = threshold voltage for VSB = 0

VSB = source-to-body voltage
γ = body effect coefficent
φF = Fermi Potential

Typically VT is positive for NMOS and negative for PMOS transistor

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