GF10x/11x Design Ove

erview

2011.2.21
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Agenda
Schematic Design Overview
PCI-Express
Memory Controller Interface
Display Interface
MIO(SLI)
I2C
GPIO
Straps
Power
Others

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Schematic Design
n Overview

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PCI-Expre
ess

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PCI-Express
Ensure PEX_RST* and PEX_RE EFCLK are connected.
PEX TSTCLK OUT should be tterminated with a 200 ohm resistor
PEX_TSTCLK_OUT
and made easily accessible forr probing, default can be unstuffed.
PEX_TEMP is used for internal calibration,, pull-down
p this signal
g
with a 2.49Kohm 1% resistor.
PEX_CLK_REQ* is an open-dra ain bi-directional signal, by default
it should have a 10Kohm pull-u
up to 3.3V, This signal is an active
low signal.
F default
For d f lt and
d production,
d ti DT
PD tM d tto G
TestMode Gndd with
ith 10K
10K.
PCI-Express
Interface Power Rails
PEX_IOVDD/Q – PEX_VDD
PEX_PLLVDD – PEX_VDD
PEX_SVDD_3V3 – 3.3V
PEX PLL HVDD - 3.3V
PEX_PLL_HVDD 3 3V
PCI-Express

Routing Layers: Top, Bottom

Reference: GND
Trace Impedance: 90Ω Diff.
Termination: On die.
Place the caps within 0.3 inches
s from the connector and void the
GND plane underneath.

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PCI-Express

Plane voiding beneath AC coup pling capacitor

Plane voiding beneath PCI exprress edge fingers (only for signal
pads is for thickness considera
p ation))
PCB thickness and alignment a affecting edge finger contact

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M
Memory Controller
C t ll Interface
I t f

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Memory Controller Interfa
ace
To improve performance, Fermi GPUs s divide the frame buffer interface into
Channels, These channels are 32bits slices made up of 4 bytes, each channel
can be
b implemented
i l t d with
ith a single
i l 32b
bit wide
id DRAM componentt or with ith two
t
16bit wide parts.
Every channel can issue different commaands
Every channel can read/write to independ
dent addresses.
Each channel contains a fully indepenndent memory controller.
All memories within a channel share tthe same command bus and the address
bus.
The different channels in a GPU are coompletely Asynchronous to each other
O l B
Only BL88 is
i supported.
d
Support both x32 and x16 GDDR5 and d DDR3 DRAM modes of operation.
Memory Controller Interfa
ace

Memory Voltage Reference

Use GPIO10 for Vref Ctrl

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Memory Controller Interfa
ace

Memory Voltage Reference (Vre

ef)
Internal Vref is applied in Fermi G
GPUs so external Vref provision is not
required, the Vref pin on GPU can n be left unconnected.
GDDR5 memory components als so have internal Vref for DQ and DBI
signals, external Vref is recomme ended.
Memory y Voltage
g Reference Switc chingg
Voltage Name Un‐terminated Terminated
FBVREF at RAM 50% 70%

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Memory Controller Interfa
ace

FBVREF Maximum Switching Time

Rail Maximum Switching Time

FBVREF X=20uS

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Memory Controller Interfa
ace

GPU Driver Calibration

Default GPU Driver Calibration for Frame Buffer Interface

Memory  FBVDDQ  FB_CAL_PU_GND  FB_CAL_PD_VDDQ  FB_CAL_TERM_GND
GDDR5  1.5 V  40.2 Ω 40.2 Ω 60.4 Ω

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Display Intterface

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Display Interface

Digital Displays
DVI-I
HDMI
DisplayPort
Analog Displays
DAC A
DAC B

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 Display Interface

Digital Display
DVI is only supported on Links AA,B,E and F, Dual-Links DVI is supported
on links A/B and E/F.
For I2C/DDC lines, because the IFFPx_AUX_I2Cx lines are not 5V tolerance,
a Level Shifter must be used to s
support I2C.DDC.
For unused IFP Marco,, pull-down
p n IFPxyIOVDD
y and IFPxy
y_PLLVDD with a
10Kohm resistor, the other IO pin
ns can be left not connected (NC).
gital Display Link IFPA(LinkA) IFPB(LinkB) IFPC(L
LinkC) IFPD(LinkD) IFPE(LinkE) IFPF(LinkF)

DVI √ (Dual
(D l Link
Li k with
ith IFPB)√ (Dual Link
(D l Li k with
ith IFPA) x x √(Dual
√(D l Link ith IFPF) √ (Dual
Li k with (D l Link
Li k with
ith
HDMI √ x √ √ √ x
Mini-HDMI √ x √ √ √ x
Display Port x x √ √ √ x
Mini-DP x x √ √ √ x
Display Interface
DVI connection at IFPAB

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Display Interface

HDMI at IFPx
AC Coupling Caps
499 ohm PD
I2C 3V3 to 5V LevelShift

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Display Interface - Display
yPort

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Display Interface - Display
yPort

AUX Link in native mode

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Display Interface

Digital Display Interface Power Rails

TMDS Power Rails
Power Rails Voltage Maximum Current Draw
IFPA IO: 300mA
IFPA_IO: 300mA
IFPx_IOVDD 3.3V±5% IFPB_IO: 200mA
IFPx_PLLVDD 1.05V±5% 200mA
HDMI Power Rails
Power Rails Voltage Maximum Current Draw
IFPx_IOVDD 1.05V±5% 285mA
IFPy_PLLVDD 3.3V±5% 200mA

Display Port Power Rails

Power Rails Voltage Maximum Current Draw
IFPx_IOVDD 1.05V±5% 300mA
IFPy_PLLVDD 3.3V±5% 200mA
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Display Interface

Analog Displays

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Display Interface

Analog Display
The D12x GPUs feature two RGB DACss that support legacy connectors. The two
DACs are named DAC A and DAC B B. There is no Macrovision support in this
family GPUs
GPUs.
DAC VREF requires 0.1uF decoupling ccapacitor.

DAC Analog RGB M
Microvision
DAC A
DAC A S
Supported
t d N t
Not supported
t d

DAC B Supported N
Not supported
Display Interface

Analog Display Interface Power R

Rails

Power Rails Voltage Maximum Current Draw

DACx_VDD 3.3V±5% 120mA

Display Interface

VGA Signal Terminations

Use a 37.5 Ω ± 2% trace impedance between the GPU and the first 150 Ω resistor (R1) if the trace length is
not short.
short The trace length should not exceed 6 600 mil
mil. Next,
Next use a 50Ω ± 2% trace impedance between the
resistor R1 and the resistor R2. The trace lengtth should not exceed 6000 mil.
Place the filter after the second termination res
sistor, R2. The trace length should not exceed120 mil and
have an impedance of 50 Ω.
The trace length (75 Ω trace) between the filter and the connector should not exceed 600 mil.

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Display Interface

Analog Display
If the DAC interface is not requ uired, it should be disabled by:
Adding a pull-down
pull down to the D
DACx VDD with a 10 kΩ resistor to
DACx_VDD
GND.
Unused DDC clock and data signals g should be connected to a
5 V pull-up.
All other I/O pins (including
g DACx_VREF and DACx_RSET)
can be left unconnected (N NC)
MULTI-USE I/O (M
MIO) AND SLI

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MULTI-USE I/O (MIO) AND
D SLI

MIO(SLI)
( )

MIOA/B Calibration Resistors

MIO CAL PD VDDQ
MIOx_CAL_PD_VDDQ MIO CAL PU GND
MIOx_CAL_PU_GND
Calibration Resistor DDQ 50 ohm 1% 0402 tied to GND
50 ohm 1% 0402 tied to MIOx_VD
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MULTI-USE I/O (MIO) AND
D SLI

Interface Power Rails.

Power Rails Voltage MaximumCurrent Draw

120mA
A/non‐SLI,
33
VDD33 3.3V±5%
3.3 5% 285mA
85 A/SLI
/S

Unconnected Signals(NC)
For unused MIOS interfaces
interfaces, MIOx
MIOx__VDDQ
VDDQ must be powered with 3.3V
3 3V for
compatible designs (For GF104, mu ust connect to 3V3 even it’s no use) or pulled
down to GND.
For each unused MIO interface thatt is powered by 3.3V, provide one 0.1uF
capacitor. For MIO interfaces that h
have MIOx_VDDQ that are pulled down to
p
GND that capacitor is not needed.
MIOxCLKIN signals should have 10K Kohm pull-down resistors.
I2C
C

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I2C

I2C Specification
Parameter Specificatioin Notes
A two‐write(SCL and SDA) I/OO BUS for 
i ll hi chip 
miscellaneous chip to c hi
Overview communication
Standard Mode: Up to 10 00KHz
p g q y
Operating Frequency Fast Mode: 400KHz
Single‐ended
Topology Bi‐directional
2.2Kohm pull‐up resistor onn I2C CLK 
Termination and DATA
and DATA
Max Capacitive Load for  Standard mode: 400p
pF
BUS Line(CL) Fast Mode: 100pF

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I2C

I2C Availability
BUS ID Signal Name Type Application Associated Display Link Voltage Tolerance
I2CA_SDA
A I2CA_SCL Bus Master DDC DAC A‐CRT 5V
I2CB SDA
I2CB_SDA
B I2CB_SCL Bus Master DDC DAC B‐CRT 5V
I2CC_SDA DDC and External 
C I2CC_SCL Bus Master Devices IFPA, IFPB‐LVDS 5V
I2CS SDA
I2CS_SDA
S I2CS_SCL Slave Inteernal Thermal Sensor 5V
IFPC_AUX_I2CW_SDA_N,
W IFPC_AUX_I2CW_SCL Bus Master AUX/DDC IFPC 3.3V
IFPC_AUX_I2CX_SDA_N,
X IFPC_AUX_I2CX_SCL Bus Master AUX/DDC IFPD 3.3V
IFPC_AUX_I2CY_SDA_N,
Y IFPC AUX I2CY SCL
IFPC_AUX_I2CY_SCL Bus Master
Bus Master AUX/DDC IFPE 3.3V
IFPC_AUX_I2CZ_SDA_N,
Z IFPC_AUX_I2CZ_SCL Bus Master AUX/DDC IFPF 3.3V
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I2C

Please don’t
don t connect SMBus to
o I2C unless the PU in SMBus is
not from standby power.

Unconnected Signals (NC)

For unused dedicated (Non-AUX)) I2C pins, pull up both the I2Cx_SCL,
I2C SDA to 3
I2CxSDA 3.3V
3V using
i 2
2.2Kohm
2K h resistors.
i

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GENERAL PURPO
OSE I/O (GPIO)

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GENERAL PURPOSE I/O (GPIO)

The D12x family of GPUs uses u up to 25 General Purpose I/O

(GPIO) pins to control and monitor GPU status. Some of these
pins are available to partners fo
or custom functions, while some
built-in functions are accessible
e through the NVAPI software
interface.

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GENERAL PURPOSE I/O (GPIO)

Pin description
GPIOx Pin  Function  I/O Type  Description
GPIO[0]  HPD‐AB  Input  Hot‐Plug Detect for Link A/B
GPIO[1]  HPD‐C  Input  Hot‐Plug Detect for Link C
GPIO[2]  GPU_VID[2]  Output  GPU Voltage Control
GPIO[3] RASTER SYNC A
RASTER_SYNC_A Input/Output
Input/Output  SLI Control
SLI Control
GPIO[4] FAN_TACH Input Fan Tachometer
GPIO[5] GPU_VID[3] Output GPU Voltage Control
GPIO[6]  GPU_VID[4] Output GPU Voltage Control
GPIO[7]  GPU_VID[5] Output GPU Voltage Control
GPIO[8] THERM_OVERT Input Thermal Shutdown
GPIO[9] THERM ALERT
THERM_ALERT Inp t
Input Thermal Slo do n
Thermal Slowdown
GPIO[10]  MEM_VREF Output Memory VREF Control Switch
GPIO[11]  RASTER_SYNC _B Input/Output SLI Control
GPIO[12] NVVDD_PSI Output NVVDD Phase Shed Control
GPIO[13]  NVRESERVED_0 Input/Output Reserved for NVIDIA Use
GPIO[14]  NVRESERVED_1 Input/Output Reserved for NVIDIA Use
GPIO[15] HPD‐E Input Hot‐Plug Detect for Link E
GPIO[16] FAN_PWM Output Programmable Fan Control
GPIO[17] GPU_VID[1] Output GPU Voltage Control
GPIO[18]  GENERAL_PURPOSE_0 Input/Output Reserved for Customer Use
GPIO[19] HPD‐D Input Hot‐Plug Detect for Link D
GPIO[20]  GENERAL_PURPOSE_1 Input/Output Reserved for Customer Use
GPIO[21]  HPD‐F Input Hot‐Plug Detect for Link F
GPIO[22]  SWAP_READY Input/Output SLI Control
GPIO[23] MEM_VDD_CTL Output Memory Voltage Switch
GPIO[24]  FAN_SELECT Output Fan Control Source Select
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GENERAL PURPOSE I/O (GPIO)

Unconnected Signals (NC)

Unused GPIOs may be left as NC
C or floating on the board design.

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GENERAL PURPOSE I/O (GPIO)

Electrical Guideline -HPD

HPD

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Strap
ps

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Straps

Fermi GPUs support two differe

ent strapping modes: Mult
Mult-Level
Level
Strapping Mode & Binary Produuction Strapping Mode.
Strap
p Mode Selection

Multi_Strap_Ref1_GND Multi_Strrap_Ref0_GND Strapping Resistor Value 

Mode for other strap pins
Binary Production 40.2K 1% to GND NC 10K 5%

Multi‐Level 40.2K 1% to GND % to GND

40.2K 1% See Multi‐Level Straps

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Straps

Multi-Level
Multi Level Straps

Physical Strapping Pin Power Rail Logical Strapping Bit 3 Logical Strapping Bit 2 Logical Strapping Bit 1 Logical Strapping Bit 0

ROM_SO
ROM SO VDD33 XCLK_417
XCLK 417 FB 0 BAR SIZE
FB_0_BAR_SIZE SMB_ALT_ADDR
SMB ALT ADDR VGA DEVICE
VGA_DEVICE
ROM_SCLK VDD33 PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
ROM_SI VDD33 RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
STRAP2 VDD33 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVCID[1] PCI_DEVCID[0]
STRAP1 VDD33 3GIO_PAD_CFG_ADR[3]
[ ]3GIO_PAD_CFG_ADR[2]3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[
[ ] [ ] [
STRAP0 VDD33 USER[3] USER[2] USER[1] USER[0]

Resistor Values Pull‐uip to VDD Pull‐down to GND

5K 1000 0000
10K 1001 0001
15K 1010 0010
20K 1011 0011
25K 1100 0100
30K 1101 0101
35K 1110 0110
45K 1111 0111 NVIDIA CONFIDENTIA
Straps

Binary Mode Straps

Physical Strapping Pin Power Rail Namme

ROM SO
ROM_SO VDD33 PCI_DEVID_EXT
PCI_ DEVID EXT
ROM_SCLK VDD33 XCLLK_417
ROM_SI VDD33 PCI__DEVID[3]
STRAP2 VDD33 RAMMCFG[2]
STRAP1 VDD33 RAMMCFG[1]
STRAP0 VDD33 RAMMCFG[0]

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Straps
Sub_Vendor, 0 : no VBIOS, 1 : VBIOS rom is present (default)
RAMCFG, memory strapping table
XCLK_417, Internal PCI-E Clock, 0 : 27 77MHz (default)
FB_0_BAR_Size, SysFB aperture size e used by GPU, 0 : 256MB (default)
PCI DEVID determine DID bit [4:0]
PCI_DEVID,
User Straps, It’s use for panel selectio
on
3GIO_PADCFG, determine the PCI-E s signal swing, 0 : default (high swing)
PEX_PLL_EN_Term, used to set PCI-E E PLL Term, 1 : Enable, 0 : Disable
(default)
SLOT CLK CFG 1 : GPU & MCH sharre a common PCI-E reference clock
SLOT_CLK_CFG, clock.
SMBus_ALT_Addr, 0 : 0x9E (default), 1 : 0x9C (Multi-GPU)
VGA_Device, 0 : 3D device , 1 : VGA d device (default)

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Powe
er

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Power

MVS ((Multi-Voltage
g Set Point))
Must be compatible with VRM11.
NVVDD Voltage Switching Requireme
ent

Constraint Parameter  Requirement  Notes

N
A
Applies to any voltage switching; measured from 
c
controlling GPIO assertion to when the power supply is 
Voltage ramp time  < 192 us  stabilized at the desired voltage level.
T is measured from the target nominal voltage level
This
This is measured from the target nominal voltage level 
u
up or down. Target voltage is the resulting NVVDD 
Positive/Negative overshoot < 30 mV  v
voltage after the switch.
T
This is measured from the target nominal voltage level 
u
up or down. Target voltage is the resulting NVVDD 
d T l i h l i NVVDD
Positive/Negative overshoot < 30 mV  v
voltage after the switch.
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Power

NVVDD Settling Time

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Power

Power Sequencing
Power Up/Down States
This section discusses power se
equencing considerations. The following
power sequencing rules must bee satisfied at all times:
Cold boot
Resuming g from a suspend
p state
Entering a suspend state
Power off

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Power

Power Sequencing Recommend

dations
dations

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Power

Power sequencing Violation

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Power
Note
3V3 includes all rails that uses 3.3V (DAC
CVDD, IFPVDD, MIO, etc…)
PEXVDD includes all rails that share it (P
PLLs, etc.)
FBVDD and FBVDDQ can be combined
From IOSI perspective, the GPU has no s sequencing requirements. So these are only
recommendations for notebook GPU des signs Although deviations from this should be
signs.
documented and approved.
NVVDD -> FBVDD/Q: was historically required due to an issue with IO glitch during startup
that caused some memories to go into Te estMode. But should be Optional today
PEXVDD: There are concerns from GT21x x that PEXVDD must follow NVVDD due to issue
with state machine init in the PEX block oon GT21x. It's unknown if GF1xx will have this
issue.
IFP_IOVDD follows NVVDD for IFPABIOV VDD only in the cases of LVDS, we have seen in
notebook designs that IFPABIOVDD would glitch of it ramped before NVVDD, to avoid this
glitch we thus have to ramp IFPABIOVDD D after NVVDD.

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Otherrs

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Others

INFO ROM (Can be removed at CDP project)

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Others

Thermal Shutdown and Backdrive Pre

evention

Reserving a weak pull-down 100Kohm

m for (GPU_BUFRST*) is recommended.
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Others

Fan Control –False

False safe mecha
mechanism
nism

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Thanks & Qu
uestion

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