Single Chip Wireless

Power Transmitter IC for TX-A1

Product Datasheet
IDTP9030
Features Description
 Single-Chip 5W Solution for Wireless Power The IDTP9030 is a highly-integrated single-chip WPC-compliant
Consortium (WPC)-compliant power transmitter wireless power transmitter IC for power transmitter design A1. The
device operates with a 19V (±1V) adapter, and supplies an integrated
design A1 half-bridge inverter for DC/AC conversion. It controls the transferred
 Conforms to WPC specification version 1.1 power by modulating the switching frequency of the half-bridge inverter
specifications from 110kHz to 205kHz at a fixed 50% duty cycle specified by the WPC
 19±1V Operating Input Voltage specification for an “A1” transmitter. It contains logic circuits required to
demodulate and decode WPC-compliant message packets sent by the
 Integrated Half-Bridge Inverter mobile device to adjust the transferred power.
 Closed-Loop Power Transfer Control between Base
Station and Mobile Device The IDTP9030 is an intelligent device that periodically pings the area
surrounding the base station to detect a mobile device for charging
 Demodulates and Decodes WPC-Compliant while minimizing idle power. Once the mobile device is detected and
Message Packets authenticated, the IDTP9030 continuously monitors all communications
 5V Regulated DC/DC Converter from the mobile device, and adjusts the transmitted power accordingly
 Integrated RESET Function by varying the switching frequency of the half-bridge inverter.
 Proprietary Back –Channel Communication The IDTP9030 features a proprietary back-channel communication
 I2C Interface mode which enables the device to communicate to IDT’s wireless
 Open-Drain LED Indicator Outputs power receiver solutions (e.g. IDTP9020). This feature enables
additional layers of capabilities relative to standard WPC requirements.
 Over-Temperature/Voltage/Current Protection
 Security and encryption up to 64 bits This device also features optional security and encryptions to securely
 Foreign Object Detection (FOD) for safety authenticate the receiver before transferring power. This feature is
available when an IDTP9020 is used for the receiver.
The device includes over-temperature/voltage/current protection and a
Applications Foreign Object Detection (FOD) method to protect the base station and
 WPC-Compliant Wireless Charging Base Stations mobile device from overheating in the presence of a metallic foreign
object. It manages fault conditions associated with power transfer and
controls status LEDs to indicate operating modes.

Typical Application Circuit

Wireless
Base Station Interface Mobile Device
Transmitter(s) Receiver
Control
Control System Control System
Input Power

Output Load

Comm
Cont Comm Comm Cont
Load
Sensing DeMod Reflection Sensing
Control Mod
Control

Power Generation Power Pick-Up

IN Out
PWR Induction PWR

Package: 6x6-48 TQFN (See page 27)

Ordering Information (See page 28)

Revision 1.0.2 1 © 2012 Integrated Device Technology, Inc.

IDTP9030
Product Datasheet

IDTP9030
ADAPTOR IN SW
WPC TX-A1
88uF
(4x22uF) 1
100nF VO
PGND
(3x33nF)
250V
1.5K
GPIO_1
22nF 20K
VOSNS 1
REG_IN 4.7nF 47K
10K
1
1.2nF
1uF
10K 20K
ISNS
2.2nF
BUCK5VT_IN
1 1
3.3nF 1.8nF
10uF HPF

LDO5V LDO5V
BUCK5VT 1uF
` LDO2P5V_IN
LDO2P5V
LDO2P5V
1uF
BUCK5VT 1uF/25V
BUCK5VT_SNS
4.7uH
LX

BST 47nF
EN 10uF
EN
RESET RESET
GPIO_4 Buzzer
1uF 47K
SCL SCL
SDA SDA 3
GPIO_2 5.1K
GPIO_3 RTOP
47K
RNTC
2 5.1K
GND
GPIO_0
EP
REFGND AGND DGND LEDA LEDB

Figure 1. IDTP9030 Simplified Application Schematic

Note 1: NPO/C0G-type ceramic capacitor.
Note 2: For PCB layout, use single-point reference (“star” ground), refer to design schematic in Figure 15).
Note 3: In circuit at GPIO_2, RTOP is required to linearize the temperature range of the thermistor, RNTC. Please contact IDT for a spreadsheet calculator to guide thermistor
selection.

Revision 1.0.2 2 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet

ABSOLUTE MAXIMUM RATINGS

These absolute maximum ratings are stress ratings only. Stresses greater than those listed below (Table 1 and Table 2) may
cause permanent damage to the device. Functional operation of the IDTP9030 at absolute maximum ratings is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect long-term reliability.
Table 1. Absolute Maximum Ratings Summary. All voltages are referred to ground, unless otherwise noted.

MAXIMUM
PINS UNITS
RATING

BUCK5VT_IN, IN, REG_IN. THESE PINS MUST BE CONNECTED TOGETHER AT ALL TIMES. -0.3 to 24 V

, LX, SW5 -0.3 to 24 V

BST5 -0.3 to 29 V

LDO2P5V, XTAL/CLK_IN, XTAL/CLK_OUT -0.3 to 2.75 V

AGND, DGND, PGND, REFGND -0.3 to +0.3 V

BUCK5VT_SNS, BUCK5VT, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, HPF,
-0.3 to +5.5 V
ISNS, LDO2P5V_IN, LDO5V, RESET, SCL, SDA, VOSNS

Table 2. Package Thermal Information

MAXIMUM
SYMBOL DESCRIPTION UNITS
RATING

JA Thermal Resistance Junction to Ambient (NTG48 - TQFN) 30.8 C/W

JC Thermal Resistance Junction to Case (NTG48 - TQFN) 14.6 C/W

JB Thermal Resistance Junction to Board (NTG48 - TQFN) 0.75 C/W

TJ Junction Temperature -40 to +150 C

TA Ambient Operating Temperature -40 to +85 C

TSTG Storage Temperature -55 to +150 C

TLEAD Lead Temperature (soldering, 10s) +300 C

Note 1:The maximum power dissipation is PD(MAX) = (TJ(MAX) - TA) / θJA where TJ(MAX) is 125°C. Exceeding the maximum allowable power dissipation will
result in excessive die temperature, and the device will enter thermal shutdown.
Note 2: This thermal rating was calculated on JEDEC 51 standard 4-layer board with dimensions 3” x 4.5” in still air conditions.
Note 3: Actual thermal resistance is affected by PCB size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables.
Note 4: For the NTG48 package, connecting the 4.1 mm X 4.1 mm EP to internal/external ground planes with a 5x5 matrix of PCB plated-through-hole
(PTH) vias, from top to bottom sides of the PCB, is recommended for improving the overall thermal performance.
Note 5: If the voltage at VIN is less than 24V, limit the voltages on , LX, SW to V(VIN)+0.3V and the voltage on BST to V(VIN)+5V.

Revision 1.0.2 3 © 2012 Integrated Device Technology, Inc.

IDTP9030
Product Datasheet
Table 3. ESD Information

TEST MAXIMUM
PINS UNITS
MODEL RATINGS

All, except IN ±1000

HBM V
Only IN (37, 38 and 39) ±800

CDM All ±500 V

Revision 1.0.2 4 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet

BLOCK DIAGRAM

Figure 2. IDTP9030 Internal Functional Block Diagram

Revision 1.0.2 5 © 2012 Integrated Device Technology, Inc.

IDTP9030
Product Datasheet

ELECTRICAL CHARACTERISTICS
= RESET = 0V, IN = REG_IN = BUCK5VT_IN = 19V. TA = -40 to +85C, unless otherwise noted. Typical values are at
25C, unless otherwise noted.

Table 4. Device Characteristics

SYMBOL DESCRIPTION CONDITIONS MIN TYP MAX UNITS

Half-Bridge Inverter
Input Supply
VIN Operating Voltage 18 20 V
Range1
After power-up sequence complete.
Standby Input No coil, no load at SW, LDO5V,
IIN_A 8 15 mA
Current LDO2P5V, LX. (No wireless power
IIN2 transfer to battery.)
Sleep Mode Input
IIN_S = 5V to VIN 750 µA
Current
FSW_LOW Switching Frequency WPC Operating Range, in 110 kHz
FSW_HIGH at SW compliance with WPC requirements 205 kHz
RDS(ON)_HS Between IN and SW 175 mΩ
RDS(ON)_LS Between SW and PGND 130 mΩ
UVLO and Inverter OCP
VIN rising 10.3
Under-Voltage V
VIN_UVLO VIN falling 9.0
Protection Trip Point
Hysteresis 625 mV
Over-Current VIN = 20V, cycle-by-cycle
IIN_OCP 1.8 2.4 A
Protection Trip Point protection.
DC-DC Converter (For Biasing Internal Circuitry Only)3
Input Voltage
VBUCK5VT_IN 18 20 V
Range1
VBUCK5VT Output Voltage External ILoad = 25mA 4.5 5.5 V
IOUT External Load4 80 mA
Switching Frequency
FSW 3 MHz
at LX
Low Drop Out Regulators (For Biasing Internal Circuitry Only)3
LDO2P5V3
VLDO2P5V_IN Input Voltage Range Supplied from BUCK5VT 5 V
VLDO2P5V Output Voltage ILoad = 2mA 2.5 V
IOUT External Load 5 mA
LDO5V3
VREG_IN Input Voltage Range See Note 1. 18 20 V
VLDO5V Output Voltage ILoad = 2mA 5 V

Revision 1.0.2 6 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet

ELECTRICAL CHARACTERISTICS
= RESET = 0V, IN = REG_IN = BUCK5VT_IN = 19V. TA = -40 to +85C, unless otherwise noted. Typical values are at
25C, unless otherwise noted.
Table 5. Device Characteristics, Continued

SYMBOL DESCRIPTION CONDITIONS MIN TYP MAX UNITS

Thermal Shutdown
Temperature Rising Threshold 140
TSD Thermal Shutdown C
Temperature Falling Threshold 110

VIH 900 mV
VIL 550 mV
VEN
¯¯ = 5V 7.5 μA
IEN
¯¯ EN
¯¯ input current
VEN
¯¯ = VIN = 20V 56 μA
General Purpose Inputs / Outputs (GPIO)
VIH Input Threshold High 3.5 V
VIL Input Threshold Low 1.5 V
ILKG Input Leakage -1 +1 µA
VOH Output Logic High IOH=-8mA 4 V
VOL Output Logic Low IOL=8mA 0.5 V
IOH Output Current High -8 mA
IOL Output Current Low 8 mA
RESET
VIH Input Threshold High 3.5 V
VIL Input Threshold Low 1.5 V
ILKG Input Leakage -1 +1 µA
SCL, SDA (I2C Interface)
EEPROM loading, Step 1,
fSCL Clock Frequency 100 kHz
IDTP9030 as Master
EEPROM loading, Step 2,
fSCL Clock Frequency 300 kHz
IDTP9030 as Master
fSCL Clock Frequency IDTP9030 as Slave 0 400 kHz
Hold Time
tHD;STA (Repeated) for 0.6 μs
START Condition
CBUS-compatible masters 5 μs
tHD;DAT Data Hold Time
I2C-bus devices 10 ns
tLOW Clock Low Period 1.3 μs
tHIGH Clock High Period 0.6 μs
Set-up Time for
tSU;STA Repeated START 100 ns
Condition

Revision 1.0.2 7 © 2012 Integrated Device Technology, Inc.

IDTP9030
Product Datasheet

ELECTRICAL CHARACTERISTICS
= RESET = 0V, IN = REG_IN = BUCK5VT_IN = 19V. TA = -40 to +85C, unless otherwise noted. Typical values are at
25C, unless otherwise noted.

Table 6. Device Characteristics, Continued

SYMBOL DESCRIPTION CONDITIONS MIN TYP MAX UNITS

Bus Free Time
TBUF Between STOP and 1.3 μs
START Condition
Capacitive Load for
CB 100 pF
Each Bus Line
SCL, SDA Input
CBIN 5 pF
Capacitance5
VIL Input Threshold Low 1.5 V
When powered by device 5V
VIH Input Threshold High 3.5 V
ILKG Leakage Current -1.0 1.0 µA
Output Logic Low
VOL IPD= 2mA (Note 1) 0.5 V
(SDA)
IOH Output Current High -2 mA
IOL Output Current Low 2 mA
Analog-to-Digital Converter
ADC Conversion
N 12 Bit
Resolution
fSAMPLE Sampling Rate 62.5 KSPS
Number of Channels
Channel 8
at ADC MUX input
ADC Clock
ADCCLK 1 MHz
Frequency
Full-Scale Input
VIN_FS 2.5 V
Voltage
Microcontroller
FCLOCK Clock Frequency 40 MHz
VIN Input Voltage 2.5 V
Note 1: BUCK5VT_IN, IN, REG_IN. These pins must be connected together at all times.
Note 2: This current is the sum of the input currents for IN, REG_IN and BUCK5VT_IN.
Note 3: DC-DC BUCK5VT, LDO2P5V and LDO5V are intended only as internal device supplies and must not be loaded externally except for the EEPROM,
thermistor, LED, buzzer and pull up resistor loads (up to an absolute maximum of 25mA), as recommended in Figure 15 WPC “Qi” Compliance Schematic
and Table 6 WPC “Qi” Compliance Bill of Materials.
Note 4: Any external load at the output of the DC/DC converter must not inject noise onto the output node, and care must be taken with parasitic
inductance and capacitance.
Note 5: Guaranteed by design.

Revision 1.0.2 8 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet

PIN CONFIGURATION

TQFN-48L

ISNS
GND

HPF
NC

NC

NC

NC

NC

NC

IN

IN

IN
48 47 46 45 44 43 42 41 40 39 38 37

GPIO_6 1 36 NC

GPIO_5 2 35 SW

GPIO_4 3 34 SW

GPIO_3 4 33 SW

GPIO_2 5 32 PGND

GPIO_1 6 31 NC
EP (Center Exposed Pad)
GPIO_0 7 30 PGND

SCL 8 29 PGND

SDA 9 28 PGND

XTAL/CLK_IN 10 27 VOSNS

XTAL/CLK_OUT 11 26 LX

RESET 12 25 BUCK5VT_SNS

13 14 15 16 17 18 19 20 21 22 23 24
REG_IN

LDO5V

BUCK5VT

BST

NC

BUCK5VT_IN
REFGND

LDO2P5V

LDO2P5V_IN

AGND

DGND
EN

Figure 3. IDTP9030 Pin Configuration (NTG48 TQFN-48L 6.0 mm x 6.0 mm x 0.75 mm, 0.4mm pitch)

Revision 1.0.2 9 © 2012 Integrated Device Technology, Inc.

IDTP9030
Product Datasheet

PIN DESCRIPTION
Table 7. IDTP9030 NTG48 Package Pin Functions by Pin Number ()
PIN NAME TYPE DESCRIPTION

1 GPIO_6 I/O General purpose input/output 6

2 GPIO_5 I/O General purpose input/output 5

3 GPIO_4 I/O General purpose input/output 4

4 GPIO_3 I/O General purpose input/output 3

5 GPIO_2 I/O General purpose input/output 2

6 GPIO_1 I/O General purpose input/output 1

7 GPIO_0 I/O General purpose input/output 0

8 SCL I/O I2C clock

9 SDA I/O I2C data

10 XTAL/CLK_IN I Crystal or clock input. If not used, must be connected to GND.

11 XTAL/CLK_OUT O Crystal or clock output. If not used, must be left unconnected.

Active-high chip reset pin. A 1µF ceramic capacitor must be connected between this pin
12 RESET I
and LDO5V, and a 100kΩ resistor to G D.

Active-low enable pin. Device is suspended and placed in low current (sleep) mode when
13 I
pulled high. Tie to GND for stand-alone operation.

14 REFGND - Signal ground connection. Must be connected to AGND.

A 1µF ceramic capacitor must be connected between this pin and GND. This pin must be
15 REG_IN1 I
connected to pins 37, 38, and 39.

16 LDO5V2 O A 1µF ceramic capacitor must be connected between this pin and GND.

17 LDO2P5V2 O 2.5V LDO output. A 1µF ceramic capacitor must be connected between this pin and GND.

2.5V LDO input. The LDO2P5V_IN input must be connected to BUCK5VT. A 1µF ceramic
18 LDO2P5V_IN I
capacitor must be connected between this pin and GND.

19 BUCK5VT2 I Power and digital supply input to internal circuitry.

Revision 1.0.2 10 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet

Table 7. IDTP9030 NTG48 Package Pin Functions by Pin Number ()

PIN NAME TYPE DESCRIPTION

20 BST I Bootstrap pin for BUCK converter top switch gate drive supply.

21 AGND - Analog ground connection. Connect to signal ground. Must be connected to REFGND.

22 DGND - Digital ground connection. Must be connected to GND.

23 NC NC Not internally connected.

Buck converter power supply input. Connect 0.1uF and 1µF ceramic capacitors between
24 BUCK5VT_IN1 I
this pin and PGND.. This pin must be connected to pins 37, 38, and 39.

25 BUCK5VT_SNS I Buck regulator feedback. Connect to the high side of the buck converter output capacitor.

26 LX O Switch Node of BUCK converter. Connects to one of the inductor’s terminals.

27 VOSNS I TX-A1 coil voltage sense input.

28 PGND - Power ground.

29 PGND - Power ground.

30 PGND - Power ground.

31 NC NC Not internally connected.

32 PGND - Power ground.

33 SW O
Pins 33, 34, and 35 must be connected together. Inverter switch node. Must be connected
34 SW O
to capacitor in series with TX-A1 coil.
35 SW O

36 NC NC Not internally connected.

37 IN1 I
Inverter power supply input. Connect at least four 22µF x 25V ceramic capacitors and a
38 IN1 I 0.1μF capacitor between this pin and ground, as close to the pin as possible. Connect all
three pins (37, 38, 39) in parallel.
39 IN1 I

40 ISNS O ISNS output signal

Revision 1.0.2 11 © 2012 Integrated Device Technology, Inc.

IDTP9030
Product Datasheet

Table 7. IDTP9030 NTG48 Package Pin Functions by Pin Number ()

PIN NAME TYPE DESCRIPTION

41 HPF I High pass filter input

42 NC Internal connection, must be connected to GND.

43 GND - Ground

44 NC Internal connection, must be connected to GND.

45 NC Internal connection, must be connected to GND.

46 NC Internal connection, must be connected to GND.

47 NC Internal connection, must be connected to GND.

48 NC Internal connection, do not connect.

EP is on the bottom of the package and must be electrically tied to GND. For thermal
Center Exposed performance, solder to a large copper pad embedded with a pattern of plated through-hole vias.
EP Thermal The die is not electrically bonded to the EP, and the EP must not be used as current-carrying
Pad
electrical connection.

Note 1: IN, REG_IN, BUCK5VT_IN. These pins must be connected together at all times.
Note 2: DC-DC BUCK5VT, LDO2P5V, and LDO5V are intended only as internal device supplies and must not be loaded externally except for the EEPROM,
thermistor, LED, buzzer and pull up resistor loads (up to an absolute maximum of 25mA), as recommended in Figure 15 WPC “Qi” Compliance Schematic
and Table 6 WPC “Qi” Compliance Bill of Materials.

Revision 1.0.2 12 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet

TYPICAL PERFORMANCE CHARACTERISTICS

, IN = BUCK5VT_IN = REG_IN = 19V, TA = 25oC. Unless otherwise noted.
System Efficiency versus RX Output Power: TX Input to RX Output
(IDTP9030 "Qi" TX-A1 Evaluation Kit and IDTP9020 CSP Engineering Sample PCB V1.0)
80.00%

70.00%

60.00%
Efficiency

50.00%

40.00%

30.00%

20.00%

10.00%
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
RX Output Power (W)

Figure 4. Efficiency vs. RX Output Power with IDTP9020 Receiver

Efficiency versus RX Output Power: TX DC-to-AC

(IDTP9030 "Qi" TX-A1 Evaluation Kit and AVID Technologies, Inc., Qi Receiver
Simulator)

0.9

0.8

0.7
Efficiency

0.6

0.5

0.4

0.3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
RX Output Power (W)

Figure 5. Spacing between TX and RX coils is 2 mm

Revision 1.0.2 13 © 2012 Integrated Device Technology, Inc.

IDTP9030
Product Datasheet

SYSTEMS APPLICATIONS DIAGRAM

Inverter Cs Modulation Modulation

+ Cp Load Cm Rm
Lp Ls Cd C
- Power

IDTP9030
ADAPTOR IN SW EN EN IDTP9020
WPC TX-A1 10K 330nF
88uF
ZREF_P
(4x22uF) 1 22nF
100nF VO ACM_P
PGND REC_OUT
(3x33nF) 183nF IN_P REC_OUT REC_OUT
250V IN_P REC_OUT 40uF
IN_P
1.5K
GPIO_1
22nF 20K 11.4uH 2nF
VOSNS 1 PGND
4.7nF 47K IN_M
REG_IN 10K
1 IN_M
1.2nF
IN_M
1uF
10K 20K
ACM_M
ISNS 22nF
ZREF_M
2.2nF 330nF
BUCK5VT_IN USB/ADP_IN USB_IN USB_OUT
1 1
3.3nF 1.8nF
10uF HPF BUCK5VR_IN BUCK5VR_SNS
4.7uF
REC_OUT BUCK5VR_IN LX
LDO5V_T 10uF BUCK5VR_IN LX BUCK5VR
LDO5V
BUCK5VT 1uF LX
47nF 10uF
` LDO2P5V_IN
LDO2P5V_T GND BST
LDO2P5V
1uF
BUCK5VT 1uF/25V REC_OUT REG_IN
BUCK5VT_SNS ISNS
4.7uH 1uF
47nF
LX

BST 47nF LDO2P5V_IN LDO2P5V_IN

_T EN 10uF LDO5V LDO5V
1uF
RESET_T RESET 1uF
GPIO_4 Buzzer
1uF 47K BUCK5VR BUCK5VR
LDO2P5V LDO2P5V
SCL_T SCL
SDA_T SDA 3
1uF
GPIO_2 5.1K 100
GPIO_3 RTOP LDO5V GPIO_6
47K RESET GPIO _6
RNTC RESET GPIO_5 5K
2 5.1K GPIO _5
GND 100K
GPIO_0 5K
EP GPIO_4
GPIO _4
REFGND AGND DGND LEDA LEDB LDO5V 5K
GPIO_3
2.7K 2.7K GPIO _3
5K
SCL SCL GPIO_2
SDA SDA GPIO _2
100nF
GPIO_1
REFGND GPIO _1
5K
AGND GPIO_0
DGND GPIO _0
5K

Figure 6. IDTP9030/IDTP9020 Simplified Systems Application Diagram

Revision 1.0.2 14 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet

THEORY OF OPERATION
The IDTP9030 is a highly-integrated WPC1 (Wireless UNDER VOLTAGE LOCKOUT (UVLO)
Power Consortium)-compliant wireless power charging IC
solution for the transmitter base station. It can deliver The IDTP9030 has a built-in UVLO circuit that monitors
more than 5W of power to the receiver when used with the the input voltage and enables normal operation, as shown
IDTP9020 or 5W in WPC “Qi” mode using near-field in Figure 7.
magnetic induction as a means to transfer energy. It is the UVLO exit event
industry’s first single-chip WPC-compliant solution
designed to drive a WPC-compliant Type-A1 transmitter

VCOIL (10V/div)
coil.
OVERVIEW 0V

Figure 2 shows the block diagram of the IDTP9030.

When the VIN_UVLO block detects that the voltage at IN,
REG_IN, and BUCK5VT_IN (all connected together
externally) is above the Vin_rising threshold and EN
¯¯ is at VIN (5V/div)
a logic LOW, the Enable Sequence circuitry activates the
voltage reference, the 5V and 2.5V LDOs, the 5V buck VIN=10V
switching regulator, and the Driver Control for the output
inverter.
The voltages at the outputs of the LDOs and the buck 0V
regulator are monitored to ensure that they remain in Time (1s/div)
regulation, and the adapter voltage, coil current, and Figure 7. VIN versus UVLO threshold with /EN low.
internal temperature are monitored .
The Driver Control block converts a PWM signal from the OVER-CURRENT/VOLTAGE/TEMPERATURE
MCU to the gate drive signals required by the output PROTECTION
inverter to drive the external resonant tank.
The current in the inverter is monitored by an analog
Communication packets from the receiver in the mobile Current Limit block. If the instantaneous coil current
device are recovered by the Demodulator and converted exceeds 2A, the chip is shut down. VIN_OVP monitors the
to digital signals that can be read by the MCU. voltage applied to the IDTP9030 by the external AC
Several internal voltages and the external thermistor adapter and shuts the part down if the adapter voltage
voltage (through GPIO2) are converted to their digital rises above 24V, to protect against excessive power
representations by the ADC and supplied to the MCU. transfer to the receiver. The internal temperature is also
monitored, and the part is temporarily deactivated if the
Five GPIO ports are available to the system designer for temperature exceeds 140°C and reactivated when the
measuring an external temperature (ambient or inductor, temperature falls below 110°C.
for example) and driving LEDs and a buzzer.
DRIVER CONTROL BLOCK and INVERTER
The clock for the MCU and other circuitry is generated by
either an external crystal or an internal RC oscillator. The Driver Control block contains the logic, shoot-through
protection, and gate drivers for the on-chip power FETs.
I2C SDA and SCL pins permit communication with an The FETs are configured as a very large inverter that
external device or host. switches the SW pin between the voltage at IN and
Note 1 - Refer to the WPC specification at ground at a rate set by the MCU.
http://www.wirelesspowerconsortium.com/ for the most current information
Revision 1.0.2 15 © 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet

19V 100 nF
DEMODULATOR Driver

Power is transferred from the transmitter to the receiver 24 H A1 Coil

through their respective coils: a loosely-coupled
Fsw
transformer. How much power is transferred is
determined by the transmitter’s switching frequency
(110kHz-205kHz), and is controlled by the receiver Figure 8. Half Bridge inverter TX Coil Driver.
through instructions sent back through the coils to the
transmitter to change its frequency, end power transfer, or Figure 8 shows the resonant tank configuration from the
do something else. The instructions take the form of data WPC specification. IDT has found that the circuit of
packets, which are capacitively coupled into the Figure 9 is preferred for lower noise in the demodulation
IDTP9030’s Demodulator through the HPF pin. channel.
Recovering the data packets is the function of the
Demodulator. Understanding the packets is up to the
MCU.
OUTPUT VOLTAGE SENSE
The voltage at the junction of the external inductor and 19V 24 H
capacitor that comprise the resonant tank is monitored by Driver
the VOSNS block, digitized by the ADC, and fed to the A1 Coil
digital control logic. The control algorithm also requires
knowledge of the voltage across the inverter, so that 100 nF
voltage is also processed by the ADC and sent to the Fsw
digital block.
MICRO-CONTROLLER UNIT (MCU) Figure 9. Half Bridge inverter TX Coil Driver.
The IDTP9030’s MCU processes the algorithm,
commands, and data that control the power transferred to EXTERNAL CHIP RESET and EN
¯¯
the reciever. The MCU is provided with RAM and ROM,
The IDTP9030 can be externally reset by pulling the
and parametric trim and operational modes are set at the
RESET pin to a logic high above the VIH level.
factory through the One-Time Programming (OTP) block,
read by the MCU at power-up. Communication with The RESET pin is a dedicated high-impedance active-high
external memory is performed through I2C via the SCL digital input, and the effect is similar to the power-up reset
and SDA pins. function. Because of the internal low voltage monitoring
scheme, the use of the external RESET pin is not
APPLICATIONS INFORMATION mandatory. A manual external reset scheme can be
The recommended applications schematic diagram is added by connecting 5V to the RESET pin through a
shown in Figure 15. The IDTP9030 operates with a 19VDC simple switch. When RESET is HIGH, the
(±1V) input. The switching frequency varies from 110kHz microcontroller’s registers are set to the default
to 205kHz. At the 205kHz limit the duty cycle is also configuration. When the RESET pin is released to a LOW,
variable. The power transfer is controlled via changes in the microcontroller starts executing the code from the boot
switching frequency. The base or TX-side has a series address. If the application is in a noisy environment, an
resonance circuit made of a WPC Type-A1 coil (~24H) external RC filter is recommended (see Figure 10 for
and a series resonant capacitor (~100nF) circuit driven by reference)
a half-bridge inverter, as shown in Figure 8.

Revision 1.0.2 16 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet

LDO5V chip RC oscillator is provided to the input of a PLL to

generate the system clock. IDT recommends using the
internal oscillator.
PUSH
BUTTON C2
SWITCH 1F
RESET SYSTEM FEEDBACK CONTROL (WPC)
The IDTP9030 contains logic to demodulate and decode
error packets sent by the mobile device (Rx-side), and
C1 R adjusts power transfer accordingly. The IDTP9030 varies
0.1F 10K ~ 100K
the switching frequency of the half bridge inverter between
110kHz to 205 kHz. to adjust power transfer. The mobile
device controls the amount of power transferred via a
communication link that exists from the mobile device to
the base station. The mobile device (IDTP9020 or another
Figure 10. External Pushbutton Reset Circuit. WPC-compliant receiver) communicates with the
IDTP9030 via communication packets. Each packet has
the following format:
When the EN¯¯ pin is pulled high, the device is suspended
and placed in low current (sleep) mode. If pulled low, the Table 5 – Data Packet Format.
device is active. Preamble Header Message Checksum

EN\ rising edge function The overall system behavior between the transmitter and
receiver follows the state machine diagram below:
Buck 5VOUT (2.5V/Div)

0V
EN\ (5V/Div)

0V
Time (1ms/div)
Figure 11. /EN Function.
The current into EN
¯¯ is about

,
or close to zero if V(EN
¯¯) is less than 2V.
XTAL_CLK/IN and XTAL_CLK/OUT Figure 12. System state machine diagram

A 32.768kHz crystal connected between the The IDTP9030 performs four phases: Selection, Ping,
XTAL/CLK_IN and XTAL/CLK_OUT pins establishes a Identification & Configuration, and Power Transfer.
precise time base. Either that clock or the output of an on- START (SELECTION) PHASE
Revision 1.0.2 17 © 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet

In this phase, the IDTP9030 operates in a low power Also, the IDTP9030 must correctly receive the following
mode to determine if a potential receiver has been placed sequence of packets without changing the operating point
on the coil surface prior to the PING state. Twice a second, (175 kHz @ 50% duty cycle):
the IDTP9030 applies a brief ac signal to its coil and
listens for a response. 1. Identification Packet (0x71)
2. Extented Identification (0x81)
PING PHASE 3. Up to 7 optional configuration Packets
In this phase, the IDTP9030 applies a power signal at 175 from the following set:
kHz with a fixed 50% duty cycle and attempts to establish a. Power Control Hold-Off Packet
a communication link with a mobile device. (0x06)
Required packet(s) in PING: b. Proprietary Packet (0x18 –
0xF2)
1. Signal strength packet (0x01)
c. Reserved Packet
4. Configuration Packet (0x51)
The mobile device must send a Signal Strength Packet
within a time period specified by the WPC, otherwise the If the IDTP9030 does not detect the start bit of the header
power signal is terminated and the process repeats. byte of the next Packet in the sequence within a WPC-
specified time after receiving the stop bit of the checksum
The mobile device calculates the Signal Strength Packet byte of the preceding Signal Strength Packet, then the
value, which is an unsigned integer value between 0-255, Power Signal is removed within after a delay. If a correct
based on this formula: control packet in the above sequence is received late, or if
control packets that are not in the sequence are received,
the IDTP9030 removes the Power Signal after a delay.
POWER TRANSFER PHASE
where U is a monitored variable (i.e. rectified
voltage/current/power) and Umax is a maximum value of In this phase, the IDTP9030 adapts the power transfer to
that monitored variable expected during the digital ping the receiver based on control data it receives in control
phase at 175 kHz. error packets.
If the IDTP9030 does not detect the start bit of the header Required packet(s) in Power Transfer:
byte of the Signal Strength Packet during the Ping Phase,
1. Control Error Packet (0x03)
it removes the power signal after a delay. If a signal
strength packet is received, the IDTP9030 goes to the 2. Rectified Power Packet (0x04)
Identification and Configuration Phase. If the IDTP9030 For this purpose, the IDTP9030 may receive zero or more
does not move to the Identification and Configuration of the following Packets:
Phase after receiving the signal strength packet, or if a
packet other than a signal strength packet is received, 1. Control Error Packet (0x03)
then power is terminated. 2. Rectified Power Packet (0x04)
IDENTIFICATION AND CONFIGURATION (ID & Config) 3. Charge Status Packet (0x05)
4. End Power Transfer Packet (0x02)
In this phase, the IDTP9030 tries to identify the mobile 5. Any Proprietary Packet
device and collects configuration information.
6. Any reserved Packets
Required packet(s) in ID & Config:
If the IDTP9030 does not correctly receive the first Control
1. Identification packet (0x71) Error Packet in time, it removes the Power Signal after a
2. Extended Identification packet (0x81)* delay. Because Control Error Packets come at a regular
3. Configuration packet (0x51) interval, the IDTP9030 expects a new Control Error
Packet after receiving the stop bit of the checksum byte of
* If Ext bit of 0x71 packet is set to 1. the preceding Control Error Packet. If that does not

Revision 1.0.2 18 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet

happen, then the IDTP9030 removes the Power Signal.

Similary, the IDTP9030 must receive a Rectified Power
Packet within a WPC-specified time after receiving the
stop bit of the checksum byte of the Configuration Packet
(which was received earlier in the identification and
configuration phase). Otherwise, it removes the Power
Signal.
Upon receiving a Control Error value, the IDTP9030
makes adjustments to its operating point after a delay to
enable the Primary Coil current to stabilize again after
communication.
If the IDTP9030 correctly receives a Packet that does not
comply with the sequence, then it removes the Power
Signal.
FOREIGN OBJECT DETECTION (FOD)
In addition to over-temperature protection, the IDTP9030
employs a proprietary FOD technique for safety which
detects foreign objects placed on the base station. The
FOD algorithm is multi-layered and issues warnings
depending on the severity of the warning.
The FOD warning comes on during the PING phase
indicating the presence of a smaller object and larger
object respectively. The FOD warning is asserted during
the Power Transfer phase, indicating presence of a
foreign object. With this warning ON, the IDTP9030 stops
power transfer, goes back to the PING phase, and stays
there until the surface is cleared and the process starts
over again.

Revision 1.0.2 19 © 2012 Integrated Device Technology, Inc.

IDTP9030
Product Datasheet

APPLICATIONS INFORMATION
1
AC Adapter 2
3 C2 + C4 VIN VIN
J3 82uF/25V OSCON
0.1uF C6 C7 C10 C13 C14
LDO2P5_OUT 0.1uF 22uF/25V 22uF/25V 22uF/25V 22uF/25V

LEDA R69
NP
D1 RED R7 5.1K

D2

5.1k

48

47

46

45

44

37

38

39
GREEN R8 R70
LEDB 47k 7
GPIO_0 SW
35

NC

NC

NC

NC

NC

IN

IN

IN
4
GPIO_3 SW
34 C20, C23, C25 L1,
LDO2P5_OUT 2 33 (2x47nF/250V, C0G or WPC TX-A1 COIL,
GPIO_5 SW
3x33nF/250V, C0G) 24uH
LEDC R72 1
GPIO_6 C25 33nF/250V VO
NP
D3 NP R9 NP 3 32
GPIO_4 PGND
D6
C23 33nF/250V
5 30
GPIO_2 PGND
D4 200V Diode
36 29
NC PGND C20 33nF/250V
NP R31
NP R10 R71 LDO2P5_OUT 31
NC U1 PGND
28
LEDD NP C27 22n/50V 1.5K
R21 23
NC IDTP9030 VOSNS
27
R20 NP
BZ1 R30 20K
422 10 6 D5 C19 R27
XTAL_CLK_IN GPIO_1
1
R28 R29 C28
11 4.7n 47K
XTAL_CLK_OUT
2 R22
20K 10K 1.2nF/100V
47k 21
AGND
40
ISNS
PS1240P02CT3 14
REFGND
2.2n C15 10K R26
43
GND

Th1 C5 49 41
EP HPF
100n
C24
R17 10K 22 C18 3.3n
DGND
J1 10K 1.8nF

1 SCL 8 24 VIN
SCL BUCK5VT_IN

2 SDA 9 C16 C21

SDA
0.1u/50V 10u/25V
3 VIN
25
BUCK5VT_SNS
4 LDO5_OUT
20
BST
5 EN 13 C17
EN
L2 4.7uH
47nF
+5V
I2C connector

6 12 26
RESET LX
1u C29
7 RESET

LDO2P5V_IN

BUCK5VT
C22 C26

LDO2P5V
LDO2P5_OUT
REG_IN

LDO5V

8 0.1uF 10uF/6.3V
R18 R24
9 WP LDO2P5_OUT NC

100K 10K
15

16

42

17

18

19
10 +5V

VIN LDO5_OUT LDO2P5_OUT

C1 R16 R19 R23
0.1uF 10K 2.7K 2.7K

C8 C9 C11 C12
U2
1u 1u 1u 1u
1 8
A0 VCC
2 7
A1 WP
3 6
A2 SCL
4 5
VSS SDA

24LC64

Figure 15. IDTP9030 WPC “Qi” Compliance Schematic (See IDTP9030 valuation Kit User Manual for complete details)

Revision 1.0.2 20 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet
Table 6. IDTP9030 WPC “Qi” Compliance Bill of Materials
Item # Qty Ref Design Description Manufacturer Part # PCB Footprint
1 3 C2,C16,C22 CAP CER 0.1UF 50V 10% X7R TDK C2012X7R1H104K/0.85 805
3 C20,C23,C25 Option 1 CAP CER 0.033UF 250V 5% NP0/C0G1 TDK C4532C0G2E333JT 1812
2
2 C20,C23 Option 2 CAP CER 0.047UF 250V 5% NP0/C0G1 TDK C4532C0G2E473JT 1812
3 5 C8,C9,C11,C12,C29 CAP CER 1UF 25V 10% X7R Taiyo Yuden TMK107B7105KA-T 0603
4 4 C7, C10, C13, C14 CAP CER 22UF 25V 10% X7R Taiyo Yuden TMK325B7226MM-TR 1210
5 1 C4 OSCON 82UF 25V 20% 105DEGC Panasonic 25SVPF82M E7
5 1 C17 CAP CER 0.047UF 16V 10% X7R Murata GRM188R71C473KA01D 0603
6 1 C21 CAP CER 10UF 25V 10% X5R TDK C2012X5R1E106K 0805
7 1 C15 CAP CER 2200PF 16V 10% X7R AVX 0603YC222KAT2A 603
8 1 C6 CAP CER 0.1UF 50V 10% X7R Murata GRM188R71H104KA93D 0603
9 1 C26 CAP CER 10UF 6.3V 10% X7R Taiyo Yuden JMK212B7106KG-T 805
10 1 C18 CAP CER 3300PF 50V 5% NP0/C0G1 Murata GCM1885C1H332JA16D 0603
11 1 C24 CAP CER 1800PF 50V 5% NP0/C0G1 Murata GRM1885C1H182JA01D 0603
12 1 C27 CAP CER 0.022UF 100V X7R 10% TDK C1608X7R2A223K 0603
12 1 C28 CAP CER 1200PF 100V 5% NP0/C0G1 TDK C1608C0G2A122J 0603
13 1 C19 CAP CER 4700PF 50V 5% NP0/C0G1 TDK CGJ3E2C0G1H472J 0603
14 1 D6 DIODE SWITCH 200V 250MW Diodes Inc BAV21W-7-F SOD123
15 1 D5 DIODE SWITCH 75V 300mA Micro Comm Co 1N4148W-TP SOD123
16 1 L2 4.7uH 20% 580mA Coilcraft XPL2010-472ML 2ML
E&E Y31-60014F
17 1 L1 24uH Transmitter Coil WPC TX-A1 TDK TTx-52-T2V 53mmx53mm
Toko X1387
18 1 R18 RES 100K OHM 1/16W 1% Yageo RC0402FR-07100KL 402
19 2 R28,R30 RES 20.0K OHM 1/10W 1% Panasonic ERJ-3EKF2002V 0603
20 1 R31 RES 1.50K OHM 1/10W 1% Panasonic ERJ-3EKF1501V 0603
20 1 R24 RES 10.0K OHM 1/16W 1% Yageo RC0402FR-0710KL 402
21 1 R29 RES 10.0K OHM 1/10W 1% 0603 SMD Panasonic ERJ-3EKF1002V 603
22 1 R27 RES 47K OHM 1/10W 5% Panasonic ERJ-2GEJ473X 402
23 1 U1 IC EEPROM 64KBIT 400KHZ Microchip 24AA64T-I/MNY 8TDFN
24 1 U2 IC Wireless Power Transmitter IDT IDTP9030 6x6x0.8-48TQFN
WPC "Qi" Compliance Components
1 1 D1 LED SMARTLED 630NM RED OSRAM L29K-G1J2-1-0-2-R18-Z 0603_LED
2 1 D2 LED SMARTLED GREEN 570NM OSRAM LG L29K-G2J1-24-Z 0603_LED
19 2 R7, R8 RES 4.9K OHM 1/10W 5% Panasonic ERJ-2RKF4991X 402
20 3 R16,R17,R24 RES 10.0K OHM 1/16W 1% Yageo RC0402FR-0710KL 402
21 1 R20 RES 422 OHM 1/10W 1% Panasonic ERJ-2RKF4220X 402
22 2 R19,R23 RES 2.7K OHM 1/10W 5% Panasonic ERJ-2GEJ272X 402
23 2 C1,C5 CAP CER 0.1UF 50V 10% X7R Murata GRM188R71H104KA93D 0603
24 1 TH1 THERMISTOR NTC 10K OHM 1% RAD TDK B57551G0103F000 Through-hole
25 1 BZ1 BUZZER PIEZO 4KHZ PC MNT TDK PS1240P02CT3 12.2mmx3.5mm

Note 1: Recommended capacitor temperature/dielectric and voltage ratings:

250V capacitors are recommended because 200Vp-p voltage levels may appear I2C Communication
on the resonance capacitors as stated in the WPC specification. C0G/NPO-type
capacitor values stay relatively constant with voltage while X7R and X5R The IDTP9030 includes an I2C block which can support
ceramic capacitor values de-rate from 40% to over 80%. The decision to use either I2C Master or I2C Slave operation. After power-on-
lower voltage 100V capacitors or other type temperature/dielectric capacitors is reset (POR), the IDTP9030 will initially become I2C Master
left to the end user.
for the purpose of uploading firmware from an external
memory device, such as an EEPROM. The I2C Master
External Components mode on the IDTP9030 does not support multi-master
mode, and it is important for system designers to avoid
The IDTP9030 requires a minimum number of external any bus master conflict until the IDTP9030 has finished
components for proper operation (see the BOM in Table any firmware uploading and has released control of the
10). A complete design schematic compliant to the WPC bus as I2C Master. After any firmware uploading from
“Qi” standard is given in Figure 19. It includes WPC “Qi” external memory is complete, and when the IDTP9030
LED signaling, buzzer, thermistor circuit, and EEPROM for begins normal operation, the IDTP9030 is normally
loading IDTP9030 firmware. configured by the firmware to be exclusively in I2C Slave
mode.

Revision 1.0.2 21 © 2012 Integrated Device Technology, Inc.

IDTP9030
Product Datasheet

For maximum flexibility, the IDTP9030 tries to  GPIO5 LEDC and GPIO6 LEDD are for future
communicate with the first address on the EEPROM at development, and are currently not defined.
100kHz. If no ACK is received, communication is
attempted at the other addresses at 300kHz.

EEPROM LED FUNCTIONS

The IDTP9030 uses an external EEPROM which contains Two GPIOs are used to drive LEDs which indicate,
either standard or custom TX firmware. The external through various on/off and illumination options, the state of
EEPROM memory chip is pre-programmed with a charging and some possible fault conditions.
standard start-up program that is automatically loaded
when 19V power is applied. The IDTP9030 uses I2C slave A red L D indicates various Fault and FOD (“Foreign
address 0x52 to access the EEPROM. The IDTP9030 Object Detection”) states. The green L D indicates
slave address is 0x39. The EEPROM can be Power Transfer and Charge Complete state information.
reprogrammed to suit the needs of a specific application Upon power up, the two LEDs together may optionally
using the IDTP9030 software tool (see the IDTP9030-Qi indicate the Standby State and remain in this state until
Demo Board User Manual for complete details). The IC another of the defined Operational States occurs
will look initially for an external EEPROM and use the
firmware built into the IC ROM only if no custom firmware As shown in Figure 16, one or two resistors configure the
is found. A serial 8Kbyte (8Kx8 64Kbits) external defined LED option combinations. The DC voltage set in
EEPROM is sufficient. this way is read one time during power-on to determine
the LED configuration. To avoid interfering with the LED
If the standard default/built-in firmware is not suitable for operation, the useful DC voltage range must be limited to
the application, custom ROM options are possible. Please not greater than 1Vdc.
contact IDT sales for more information. IDT will provide
the appropriate image in the format best suited to the LDO2P5V_OUT
application.
IDTP9030

Overview of Standard GPIO Usage Ra

There are 7 GPIO’s on the IDTP9030 transmitter IC, of

which five are available for use as follows: GPIO3

 GPIO0: Red LED_A to indicate standby, fault Resistor To ADC

conditions, and FOD warnings; see table 7. to set Rb
options
 GPIO2: Temperature sensor input. Contact IDT
for a spreadsheet facilitating selection and use of LED Mode Resistor Configuration
thermistors.
Figure 16. IDTP9030 LED Resistor Options.
 GPIO3: Green LED_B to indicate standby, power
transfer, and power complete. Table 7 lists how LED Pattern Operational Status Definitions:
the red and green LEDs can be used to display Blink Slow: 1s ON, 1s OFF, repeat.
information about the IDTP9030’s operating
modes. The table also includes information Blink Fast: 400ms ON, 800ms OFF, 400ms ON, 800ms
about external resistors or internal pull up/down OFF, repeat.
options to select LED modes. Eight of the ten The red FOD warning LED is synchronized with the
LED modes (those associated with advanced buzzer (if implemented) such that a 400ms tone
charging modes) are currently designated as corresponds with the FOD red LED illumination and
“Future” modes. 800ms of silence corresponds with the LED being off.
 GPIO4: AC or DC buzzer (optional) with resistor During the 30s that the buzzer is off, the FOD LED must
options for different buzzer configurations. continue to blink.

Revision 1.0.2 22 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet

Table 7 – IDTP9030 LED Resistor Optioning (Not all options supported, shaded rows are for future development).
LED Control LED Select LED #/ Operational Charge
Power Status Fault FOD
Option Resistor Value Description Color Standby Transfer Complete Condition Warning
LED1- Green ON BLINK SLOW ON OFF OFF
1 Pull Down Standby LEDs ON LED2- Red ON OFF OFF ON BLINK FAST
LED1- Green ON BLINK SLOW ON OFF OFF
2 R1 Standby LEDs ON plus LED2- Red ON OFF OFF ON BLINK FAST
LED1- Green ON BLINK SLOW ON OFF OFF
3 R2 Standby LEDs ON plus LED2- Red ON OFF OFF ON BLINK FAST
LED1- Green ON BLINK SLOW ON OFF OFF
4 R3 Standby LEDs ON plus LED2- Red ON OFF OFF ON BLINK FAST
LED1- Green ON BLINK SLOW ON OFF OFF
5 R4 Standby LEDs ON plus LED2- Red ON OFF OFF ON BLINK FAST
LED1- Green OFF BLINK SLOW ON OFF OFF
6 Pull Up Standby LEDs OFF LED2- Red OFF OFF OFF ON BLINK FAST
LED1- Green OFF BLINK SLOW ON OFF OFF
7 R5 Standby LEDs OFF plus LED2- Red OFF OFF OFF ON BLINK FAST
LED1- Green OFF BLINK SLOW ON OFF OFF
8 R6 Standby LEDs OFF plus LED2- Red OFF OFF OFF ON BLINK FAST
LED1- Green OFF BLINK SLOW ON OFF OFF
9 R7 Standby LEDs OFF plus LED2- Red OFF OFF OFF ON BLINK FAST
LED1- Green OFF BLINK SLOW ON OFF OFF
10 R8 Standby LEDs OFF plus LED2- Red OFF OFF OFF ON BLINK FAST
R1-R8 are created using combination of two 1% resistors.
Designates Future Option

Buzzer Function
An optional buzzer feature is supported on GPIO4. The For 30 seconds: 400ms ON, 800ms OFF, repeat
default configuration is an “AC” buzzer. The signal is Next 30 seconds: Off/silence (but no change to LED
created by toggling GPIO4 active-high/active-low at a on/off patterns)
2KHz frequency. The pattern is repeated while the error condition exists

Buzzer Action: Power Transfer Indication The buzzer is synchronized with the FOD LED such that
The IDTP9030 supports audible notification when the the 400ms on tone corresponds with the Red LED
device operation successfully reaches the Power Transfer illumination and 800ms off (no sound) corresponds with
state. The duration of the power transfer indication sound Red LED being off.
is 400ms.

The latency between reaching the Power Transfer state

Decoupling/Bulk Capacitors
and sounding the buzzer does not exceed 500ms. As with any high-performance mixed-signal IC, the
Additionally, the buzzer sound is concurrent within IDTP9030 must be isolated from the system power supply
±250ms of any change to the LED configuration indicating noise to perform optimally. A decoupling capacitor of
the start of power transfer. 0.1μF must be connected between each power supply and
the PCB ground plane as close to these pins as possible.
Buzzer Action: No Power Transfer due to Foreign For optimum device performance, the decoupling
Object Detected (FOD) capacitor must be mounted on the component side of the
When a major FOD situation is detected such that, for PCB. Avoid the use of vias in the decoupling circuit.
safety reasons, power transfer is not initiated, or that Additionally, medium value capacitors in the 22μF range
power transfer is terminated, the buzzer is sounded in a must be used at the VIN input to minimize ripple current
repeating sequence: and voltage droop due to the large current requirements of
the resonant half Half-Bridge driver. At least four 22μF

Revision 1.0.2 23 © 2012 Integrated Device Technology, Inc.

IDTP9030
Product Datasheet

capacitors must be used close to the IN pins of the device. together to minimize any DC regulation errors caused by
Since the operating voltage is 18V to 20V, the value of the ground potential differences.
capacitors will decrease due to voltage derating The bootstrap pin requires a small capacitor; connect a
characteristics. For example, a 22μF X7R 25V capacitor’s 47nF bootstrap capacitor rated above 25V between the
value is actually 6μF when operating at 20V. BST pin and the LX pin.
There must also be an 82μF to 100μF bulk capacitor The output-sense connection to the feedback pins must
connected at the node where the input voltage to the be separated from any power trace. Connect the output-
board is applied. A 25V Oscon-type or aluminum sense trace as close as possible to the load point to avoid
electrolytic must be connected between the input supply additional load regulation errors. Sensing through a high-
and ground as shown in Figure 20. Oscon capacitors have current load trace will degrade DC load regulation.
much lower ESR than aluminum electrolytic capacitors
The power traces, including PGND traces, the SW or OUT
and will reduce voltage ripple.
traces and the VIN trace must be kept short, direct and
ADC Considerations wide to allow large current flow. The inductor connection
to the SW or OUT pins must be as short as possible. Use
The GPIO pins are connected internally to a successive several via pads when routing between layers.
approximation ADC with a multiplexed input. The GPIO
pins that are connected to the ADC have limited input LDOs
range, so attention must be paid to the maximum VIN
Input Capacitor
(2.5V). 0.01μF decoupling capacitors can be added to the
GPIO inputs to minimize noise. The input capacitors must be located as physically close
as possible to the power pin (LDO2P5V_IN) and power
WPC TX-A1 Coil ground (GND). Ceramic capacitors are recommended for
their higher current operation and small profile. Also,
The SW pin connects to a series-resonance circuit
ceramic capacitors are inherently more capable than are
comprising a WPC Type-A1 coil (~24H) and a series tantalum capacitors to withstand input current surges from
resonant capacitor (~100nF), as shown in Figures 8 and 9. low impedance sources such as batteries used in portable
The inductor serves as the primary coil in a loosely- devices. Typically, 10V- or 16V-rated capacitors are
coupled transformer, the secondary of which is the required. The recommended external components are
inductor connected to the power receiver (IDTP9020 or shown in Table 10.
another receiver).
Output Capacitor
The TX-A1 power transmitter coil is mounted on a ferrite For proper load voltage regulation and operational stability,
shield to reduce EMI. The coil assembly can be mounted a capacitor is required on the output of each LDO
next to the IDTP9030. Either ground plane or grounded (LDO2P5V and LDO5V). The output capacitor must be
copper shielding can be added beneath the ferrite shield placed as close to the device and power (PGND) pins as
for added reduction in radiated electrical field emissions. possible. Since the LDOs have been designed to function
The coil ground plane/shield must be connected to the with very low ESR capacitors, a ceramic capacitor is
IDTP9030 ground plane by a single trace. recommended for best performance.
Resonance Capacitors
The resonance capacitors must be C0G type dielectric
and have a DC rating to 250V. The highest-efficiency PCB Layout Considerations
combination is three 33nF in parallel to get the lowest - For optimum device performance and lowest output
ESR. Using a single 100nF or two 47nF capacitors is also phase noise, the following guidelines must be
an option. The part numbers are shown in Table 6. observed. Please contact IDT for Gerber files that
contain the recommended board layout.
Buck Converter
- As for all switching power supplies, especially those
The input capacitors (CIN) must be connected directly providing high current and using high switching
between the power VIN and power PGND pins. The output frequencies, layout is an important design step. If
capacitor (COUT) and power ground must be connected layout is not carefully done, the regulator could show

Revision 1.0.2 24 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet

instability as well as EMI problems. Therefore, use results, use large area PCB patterns with
wide and short traces for high current paths. wide and heavy (2 oz.) copper traces, placed
on the top layer of the PCB.
- The 0.1μF decoupling capacitors must be mounted on
2. In cases where maximum heat dissipation is
the component side of the board as close to the VDD
required, use double-sided copper planes
pin as possible. Do not use vias between decoupling
connected with multiple vias.
capacitors and VDD pins. Keep PCB traces to each
3. Thermal vias are needed to provide a
VDD pin and to ground vias as short as possible.
thermal path to the inner and/or bottom
- To optimize board layout, place all components on layers of the PCB to remove the heat
the same side of the board and limit the use of vias. generated by device power dissipation.
Route other signal traces away from the IDTP9030. 4. Where possible, increase the thermally
For example, use keepouts for signal traces routing conducting surface area(s) openly exposed
on inner and bottom layers underneath the device. to moving air, so that heat can be removed
- The NQG48 6.0 mm x 6x0 mm x 75mm 48L package by convection (or forced air flow, if
has an inner thermal pad which requires blind available).
assembly. It is recommended that a more active flux 5. Do not use solder mask or place silkscreen
solder paste be used such as Alpha OM-350 solder on the heat-dissipating traces/pads, as they
paste from Cookson Electronics increase the net thermal resistance of the
(http://www.cooksonsemi.com). Please contact IDT mounted IC package.
for Gerber files that contain recommended solder Power Dissipation/Thermal Requirements
stencil design.
The IDTP9030 is offered in a TQFN-48L package. The
- The package center exposed pad (EP) must be maximum power dissipation capability is 2W, limited by
reliably soldered directly to the PCB. The center land the die’s specified maximum operating junction
pad on the PCB (set 1:1 with EP) must also be tied to temperature, Tj, of 125°C. The junction temperature rises
the board ground plane, primarily to maximize thermal with the device power dissipation based on the package
performance in the application. The ground thermal resistance. The package offers a typical thermal
connection is best achieved using a matrix of PTH resistance, junction to ambient (JA), of 31°C/W when the
vias embedded in the PCB center land pad for the PCB layout and surrounding devices are optimized as
NTG48. The PTH vias perform as thermal conduits to described in the PCB Layout Considerations section. The
the ground plane (thermally, a heat spreader) as well techniques as noted in the PCB Layout section need to be
as to the solder side of the board. There, these followed when designing the printed circuit board layout,
thermal vias embed in a copper fill having the same as well as the placement of the IDTP9030 IC package in
dimensions as the center land pad on the component proximity to other heat generating devices in a given
side. Recommendations for the via finished hole-size application design. The ambient temperature around the
and array pitch are 0.3mm to 0.33mm and 1.3mm, power IC will also have an effect on the thermal limits of
respectively. an application. The main factors influencing θJA (in the
- Layout and PCB design have a significant influence order of decreasing influence) are PCB characteristics,
on the power dissipation capabilities of power die/package attach thermal pad size, and internal package
management ICs. This is due to the fact that the construction. Board designers should keep in mind that
surface mount packages used with these devices rely the package thermal metric θJA is impacted by the
heavily on thermally conductive traces or pads to characteristics of the PCB itself upon which the TQFN is
transfer heat away from the package. Appropriate PC mounted. For example, in a still air environment, as is
layout techniques must then be used to remove the often the case, a significant amount of the heat that is
heat due to device power dissipation. The following generated (60 - 85%) sinks into the PCB. Changing the
general guidelines will be helpful in designing a board design or configuration of the PCB changes impacts the
layout for lowest thermal resistance: overall thermal resistivity and, thus, the board’s heat
1. PC board traces with large cross sectional sinking efficiency.
areas remove more heat. For optimum

Revision 1.0.2 25 © 2012 Integrated Device Technology, Inc.

IDTP9030
Product Datasheet

Implementation of integrated circuits in low-profile and state ambient temperature (TA) of 85°C. Therefore, the
fine-pitch surface-mount packages typically requires maximum recommended power dissipation is:
special attention to power dissipation. Many system-
PD(Max) = (150°C - 85°C) / 30°C/W 2 Watt
dependant issues such as thermal coupling, airflow,
added heat sinks, and convection surfaces, and the Thermal Overload Protection
presence of other heat-generating components, affect the The IDTP9030 integrates thermal overload shutdown
power-dissipation limits of a given component. circuitry to prevent damage resulting from excessive
thermal stress that may be encountered under fault
Three basic approaches for enhancing thermal
conditions. This circuitry will shut down or reset the device
performance are listed below:
if the die temperature exceeds 140°C. To allow the
1. Improving the power dissipation capability of the
maximum load current on each regulator and resonant
PCB design
transmitter, and to prevent thermal overload, it is important
2. Improving the thermal coupling of the component
to ensure that the heat generated by the IDTP9030 is
to the PCB
dissipated into the PCB. The package exposed paddle
3. Introducing airflow into the system
must be soldered to the PCB, with multiple vias evenly
First, the maximum power dissipation for a given situation distributed under the exposed paddle and exiting the
must be calculated: bottom side of the PCB. This improves heat flow away
PD(MAX) = (TJ(MAX) - TA)/θJA from the package and minimizes package thermal
gradients.
Where:
Special Notes
PD(MAX) = Maximum Power Dissipation (W)
NQG TQFN-48 Package Assembly
θJA = Package Thermal Resistance (°C/W) Note 1: Unopened Dry Packaged Parts have a one year
TJ(MAX) = Maximum Device Junction Temperature (°C) shelf life.
TA = Ambient Temperature (°C) Note 2: The HIC indicator card for newly opened Dry
The maximum recommended junction temperature (TJ(MAX)) Packaged Parts should be checked. If there is any
for the IDTP9030 device is 150°C. The thermal resistance moisture content, the parts must be baked for minimum of
of the 48-pin NQG package (NGQ48) is optimally 8 hours at 125˚C within 24 hours of the assembly reflow
θJA=30°C/W. Operation is specified to a maximum steady- process.

Revision 1.0.2 26 © 2012 Integrated Device Technology, Inc.

 IDTP9030
Product Datasheet

PACKAGE OUTLINE DRAWING

REVISIONS
DCN REV DESCRIPTION DATE APPROVED
00 INITIAL RELEASE 3/16/10

POD IN BOTTOM VIEW

DAP SIZE 4.5x4.5

37 48

36 1

C0.35

25 12

24 13

IDT
TOLERANCES 6024 SILVER CREEK
UNLESS SPECIFIED VALLEY ROAD. SAN JOSE,
POD IN SIDE VIEW DECIMAL ANGULAR
TM
CA 95138
X± .1 ±1° PHONE: (408) 284-8200
XX± .05
XXX± .030
www.IDT.com FAX: (408) 284-3572

APPROVALS DATE TITLE NT/NTG48 PACKAGE OUTLINE

DRAWN PKP 12/04/09 6.0 x 6.0 mm BODY
CHECKED 0.4 mm PITCH TQFN
SIZE DRAWING No. REV

C PSC-4294 00
DO NOT SCALE DRAWING SHEET 1OF 1

Figure 17. IDTP9030 Package Outline Drawing (NTG48 TQFN-48L 6.0 mm x 6.0 mm x 0.75 mm48L, 0.4mm pitch)

Revision 1.0.2 27 © 2012 Integrated Device Technology, Inc.

VPAxxxx
Preliminary Product Data

ORDERING GUIDE
Table 8. Ordering Summary
PART AMBIENT TEMP. SHIPPING
MARKING PACKAGE QUANTITY
NUMBER RANGE CARRIER
P9030-0NTGI P9030NTG NTG48 - TQFN-48 6x6x0.75mm -40°C to +85°C Tape or Canister 25
P9030-0NTGI8 P9030NTG NTG48 - TQFN-48 6x6x0.75mm -40°C to +85°C Tape and Reel 2,500

www.IDT.com

6024 Silver Creek Valley Road

San Jose, California 95138
Tel: 800-345-7015
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All
information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the
described products are determined in the independent state and are not guaranteed to perform the same way when installed in c ustomer products. The information contained herein is provided
without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of
merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT
or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly
affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the
property of IDT or their respective third party owners.

© Copyright 2012. All rights reserved.