Memory Management PDF

Memory Management
Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013
Contiguous Allocation
Main memory must support both OS and user processes
Limited resource, must allocate efficiently
Contiguous allocation is one early method
Main memory usually into two partitions:
Resident operating system, usually held in low memory with
interrupt vector
User processes then held in high memory
Each process contained in single contiguous section of
memory
Operating System Concepts – 9th Edition 8.2 Silberschatz, Galvin and Gagne ©2013
Contiguous Allocation (Cont.)
Relocation registers used to protect user processes from each
other, and from changing operating-system code and data
Base register contains value of smallest physical address
Limit register contains range of logical addresses – each
logical address must be less than the limit register
MMU maps logical address dynamically
Can then allow actions such as kernel code being transient
and kernel changing size
Multiple-partition allocation
Multiple-partition allocation
Degree of multiprogramming limited by number of partitions
Variable-partition sizes for efficiency (sized to a given process’ needs)
Hole – block of available memory; holes of various size are scattered
throughout memory
When a process arrives, it is allocated memory from a hole large enough to
accommodate it
Process exiting frees its partition, adjacent free partitions combined
Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
First-fit: Allocate the first hole that is big enough
Best-fit: Allocate the smallest hole that is big enough; must

search entire list, unless ordered by size
Produces the smallest leftover hole
Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole
First-fit and best-fit better than worst-fit in terms of speed and storage
utilization
Fragmentation
External Fragmentation – total memory space exists to
satisfy a request, but it is not contiguous
Internal Fragmentation – allocated memory may be slightly
larger than requested memory; this size difference is memory
internal to a partition, but not being used
First fit analysis reveals that given N blocks allocated, 0.5 N
blocks lost to fragmentation
1/3 may be unusable -> 50-percent rule
Fragmentation (Cont.)
Reduce external fragmentation by compaction

Shuffle memory contents to place all free memory together
in one large block
Compaction is possible only if relocation is dynamic, and is
done at execution time
I/O problem
 Latch job in memory while it is involved in I/O
 Do I/O only into OS buffers
Now consider that backing store has same fragmentation
problems
Segmentation
Memory-management scheme that supports user view of memory
A program is a collection of segments
A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
User’s View of a Program
Logical View of Segmentation
4
1
3 2
4
user space physical memory space
Segmentation Architecture
Logical address consists of a two tuple:
<segment-number, offset>,
Segment table – maps two-dimensional physical addresses; each

table entry has:
base – contains the starting physical address where the
segments reside in memory
limit – specifies the length of the segment
Segment-table base register (STBR) points to the segment

table’s location in memory
Segment-table length register (STLR) indicates number of

segments used by a program;
segment number s is legal if s < STLR
Segmentation Hardware
Paging
Physical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is
available
Avoids external fragmentation
Avoids problem of varying sized memory chunks
Divide physical memory into fixed-sized blocks called frames
Size is power of 2, between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size called pages
Keep track of all free frames
To run a program of size N pages, need to find N free frames and
load program
Set up a page table to translate logical to physical addresses
Backing store likewise split into pages
Still have Internal fragmentation
Address Translation Scheme
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit
page number page offset

p d
m -n n
For given logical address space 2m and page size 2n
Paging Hardware
Paging Model of Logical and Physical Memory
Paging Example
n=2 and m=4 32-byte memory and 4-byte pages
Paging (Cont.)
Calculating internal fragmentation

Page size = 2,048 bytes
Process size = 72,766 bytes
35 pages + 1,086 bytes
Internal fragmentation of 2,048 - 1,086 = 962 bytes
Worst case fragmentation = 1 frame – 1 byte
On average fragmentation = 1 / 2 frame size
But each page table entry takes memory to track
Process view and physical memory now very different
By implementation process can only access its own memory
Free Frames
Before allocation After allocation
Implementation of Page Table
Page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the page
table
In this scheme every data/instruction access requires two
memory accesses
One for the page table and one for the data / instruction
The two memory access problem can be solved by the use of
a special fast-lookup hardware cache called associative
memory or translation look-aside buffers (TLBs)
Implementation of Page Table (Cont.)
Some TLBs store address-space identifiers (ASIDs) in each
TLB entry – uniquely identifies each process to provide
address-space protection for that process
Otherwise need to flush at every context switch
TLBs typically small (64 to 1,024 entries)
On a TLB miss, value is loaded into the TLB for faster access
next time
Replacement policies must be considered
Some entries can be wired down for permanent fast
access
Associative Memory
Associative memory – parallel search

Page # Frame #
Address translation (p, d)

If p is in associative register, get frame # out
Otherwise get frame # from page table in memory
Paging Hardware With TLB
Effective Access Time
Associative Lookup =  time unit
Can be < 10% of memory access time
Hit ratio = 
Hit ratio – percentage of times that a page number is found in the
associative registers; ratio related to number of associative
registers
Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
Effective Access Time (EAT)
EAT = (1 + )  + (2 + )(1 – )
=2+–
Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
EAT = 0.80 x 100 + 0.20 x 200 = 120ns
Consider more realistic hit ratio ->  = 99%,  = 20ns for TLB search,
100ns for memory access
EAT = 0.99 x 100 + 0.01 x 200 = 101ns
Memory Protection
Memory protection implemented by associating protection bit
with each frame to indicate if read-only or read-write access is
allowed
Can also add more bits to indicate page execute-only, and
so on
Valid-invalid bit attached to each entry in the page table:
“valid” indicates that the associated page is in the
process’ logical address space, and is thus a legal page
“invalid” indicates that the page is not in the process’
logical address space
Or use page-table length register (PTLR)
Any violations result in a trap to the kernel
Valid (v) or Invalid (i) Bit In A Page Table
Structure of the Page Table
Memory structures for paging can get huge using straight-
forward methods
Consider a 32-bit logical address space as on modern
computers
Page size of 4 KB (212)
Page table would have 1 million entries (232 / 212)
If each entry is 4 bytes -> 4 MB of physical address space /
memory for page table alone
 That amount of memory used to cost a lot
 Don’t want to allocate that contiguously in main memory
Hierarchical Paging
Hashed Page Tables
Inverted Page Tables
Two-Level Page-Table Scheme
Two-Level Paging Example
A logical address (on 32-bit machine with 1K page size) is divided into:
a page number consisting of 22 bits
a page offset consisting of 10 bits
Since the page table is paged, the page number is further divided into:
a 12-bit page number
a 10-bit page offset
Thus, a logical address is as follows:
where p1 is an index into the outer page table, and p2 is the

displacement within the page of the inner page table
Known as forward-mapped page table
Address-Translation Scheme
64-bit Logical Address Space
Even two-level paging scheme not sufficient

If page size is 4 KB (212)
Then page table has 252 entries
If two level scheme, inner page tables could be 210 4-byte entries
Address would look like
Outer page table has 242 entries or 244 bytes

One solution is to add a 2nd outer page table
But in the following example the 2nd outer page table is still 234 bytes in
size
 And possibly 4 memory access to get to one physical memory
location
Three-level Paging Scheme
Inverted Page Table
Rather than each process having a page table and keeping track
of all possible logical pages, track all physical pages
One entry for each real page of memory
Entry consists of the virtual address of the page stored in that
real memory location, with information about the process that
owns that page
Decreases memory needed to store each page table, but
increases time needed to search the table when a page
reference occurs
Use hash table to limit the search to one — or at most a few —
page-table entries
TLB can accelerate access
But how to implement shared memory?
One mapping of a virtual address to the shared physical
address
Inverted Page Table Architecture
Virtual Memory
Virtual memory – separation of user logical memory from
physical memory
Only part of the program needs to be in memory for execution
Logical address space can therefore be much larger than physical
address space
Allows address spaces to be shared by several processes
Allows for more efficient process creation
More programs running concurrently
Less I/O needed to load or swap processes
Background (Cont.)
Virtual address space – logical view of how process is
stored in memory
Usually start at address 0, contiguous addresses until end of
space
Meanwhile, physical memory organized in page frames
MMU must map logical to physical
Virtual memory can be implemented via:
Demand paging
Virtual Memory That is Larger Than Physical Memory
Demand Paging
Could bring entire process into memory
at load time
Or bring a page into memory only when
it is needed
Less I/O needed, no unnecessary
I/O
Less memory needed
Faster response
More users
Similar to paging system with swapping
(diagram on right)
Page is needed  reference to it
invalid reference  abort
not-in-memory  bring to memory
Lazy swapper – never swaps a page
into memory unless page will be needed
Swapper that deals with pages is a
pager
Basic Concepts
With swapping, pager guesses which pages will be used before
swapping out again
Instead, pager brings in only those pages into memory
How to determine that set of pages?
Need new MMU functionality to implement demand paging
If pages needed are already memory resident
No difference from non demand-paging
If page needed and not memory resident
Need to detect and load the page into memory from storage
 Without changing program behavior
 Without programmer needing to change code
Valid-Invalid Bit
With each page table entry a valid–invalid bit is associated
(v  in-memory – memory resident, i  not-in-memory)
Initially valid–invalid bit is set to i on all entries
Example of a page table snapshot:
During MMU address translation, if valid–invalid bit in page table

entry is i  page fault
Page Table When Some Pages Are Not in Main Memory
Page Fault
If there is a reference to a page, first reference to that page will

trap to operating system:
page fault
1. Operating system looks at another table to decide:
Invalid reference  abort
Just not in memory
2. Find free frame
3. Swap page into frame via scheduled disk operation
4. Reset tables to indicate page now in memory
Set validation bit = v
5. Restart the instruction that caused the page fault
Steps in Handling a Page Fault
Performance of Demand Paging (Cont.)
Three major activities
Service the interrupt – careful coding means just several hundred
instructions needed
Read the page – lots of time
Restart the process – again just a small amount of time
Page Fault Rate 0  p  1
if p = 0 no page faults
if p = 1, every reference is a fault
Effective Access Time (EAT)
EAT = (1 – p) x memory access
+ p (page fault overhead
+ swap page out
+ swap page in )
Demand Paging Example
Memory access time = 200 nanoseconds
Average page-fault service time = 8 milliseconds
EAT = (1 – p) x 200 + p (8 milliseconds)
= (1 – p x 200 + p x 8,000,000
= 200 + p x 7,999,800
If one access out of 1,000 causes a page fault, then
EAT = 8.2 microseconds.
This is a slowdown by a factor of 40!!
If want performance degradation < 10 percent
220 > 200 + 7,999,800 x p
20 > 7,999,800 x p
p < .0000025
< one page fault in every 400,000 memory accesses
First-In-First-Out (FIFO) Algorithm
Reference string: 7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1
3 frames (3 pages can be in memory at a time per process)
15 page faults
Can vary by reference string: consider 1,2,3,4,1,2,5,1,2,3,4,5
Adding more frames can cause more page faults!
 Belady’s Anomaly
How to track ages of pages?
Just use a FIFO queue
FIFO Illustrating Belady’s Anomaly
Optimal Algorithm
Replace page that will not be used for longest period of time
9 is optimal for the example
How do you know this?
Can’t read the future
Used for measuring how well your algorithm performs
Least Recently Used (LRU) Algorithm
Use past knowledge rather than future
Replace page that has not been used in the most amount of time
Associate time of last use with each page
12 faults – better than FIFO but worse than OPT

Generally good algorithm and frequently used
But how to implement?
LRU Algorithm (Cont.)
Counter implementation
Every page entry has a counter; every time page is referenced
through this entry, copy the clock into the counter
When a page needs to be changed, look at the counters to find
smallest value
 Search through table needed
Stack implementation
Keep a stack of page numbers in a double link form:
Page referenced:
 move it to the top
 requires 6 pointers to be changed
But each update more expensive
No search for replacement
LRU and OPT are cases of stack algorithms that don’t have
Belady’s Anomaly
Use Of A Stack to Record Most Recent Page References
Thrashing
If a process does not have “enough” pages, the page-fault rate is
very high
Page fault to get page
Replace existing frame
But quickly need replaced frame back
This leads to:
 Low CPU utilization
 Operating system thinking that it needs to increase the
degree of multiprogramming
 Another process added to the system
Thrashing  a process is busy swapping pages in and out
Thrashing (Cont.)

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Memory Management

First-fit: Allocate the first hole that is big enough

Best-fit: Allocate the smallest hole that is big enough; must

Reduce external fragmentation by compaction

user space physical memory space

Segment table – maps two-dimensional physical addresses; each

Segment-table base register (STBR) points to the segment

Segment-table length register (STLR) indicates number of

page number page offset

For given logical address space 2m and page size 2n

n=2 and m=4 32-byte memory and 4-byte pages

Calculating internal fragmentation

Before allocation After allocation

Associative memory – parallel search

Address translation (p, d)

Thus, a logical address is as follows:

where p1 is an index into the outer page table, and p2 is the

Even two-level paging scheme not sufficient

Outer page table has 242 entries or 244 bytes

During MMU address translation, if valid–invalid bit in page table

If there is a reference to a page, first reference to that page will

12 faults – better than FIFO but worse than OPT

Thrashing  a process is busy swapping pages in and out

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