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Thunderbird Tail Light Project: ECEN 2350 Digital Logic Fall 2018

The document describes a project to design a finite state machine (FSM) to control the turn signal lights of a 1965 Ford Thunderbird using a DE10 board. The tasks are to: 1) Design the FSM state diagram and table; 2) Implement the FSM in SystemVerilog; 3) Create a clock module to trigger the FSM; and 4) Combine the FSM and clock modules into a top-level Thunderbird module. The deliverables are a report describing each task and the SystemVerilog code.

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360 views2 pages

Thunderbird Tail Light Project: ECEN 2350 Digital Logic Fall 2018

The document describes a project to design a finite state machine (FSM) to control the turn signal lights of a 1965 Ford Thunderbird using a DE10 board. The tasks are to: 1) Design the FSM state diagram and table; 2) Implement the FSM in SystemVerilog; 3) Create a clock module to trigger the FSM; and 4) Combine the FSM and clock modules into a top-level Thunderbird module. The deliverables are a report describing each task and the SystemVerilog code.

Uploaded by

Salma Saleem
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ECEN 2350 Digital Logic Fall 2018

11-12-18 P. Mathys

Thunderbird Tail Light Project


The goal of this project is to design and implement (on the DE10 board) a finite state machine
(FSM) that controls the tail lights of a 1965 Ford Thunderbird, shown in the picture below.

There are three lights on each side that light up in sequence to indicate the turn direction.
Labeling the lights from left to right as Lc, Lb, La, Ra, Rb, Rc, a left turn is indicated by
turning on La first, then La and Lb, followed by all three, La, Lb, Lc, turned on, and then
turning all three L lamps off. This cycle repeats for as long as the left turn switch is on.
The left turn sequence is illustrated graphically in the figure below.

Lc Lb La Ra Rb Rc

Left Turn Idle


L1
L2
L3

Similarly, the right turn sequence of idle → Ra → Ra, Rb → Ra, Rb, Rc, → idle → . . . is
shown graphically in the next figure.

Lc Lb La Ra Rb Rc
Right Turn Idle
R1
R2
R3

1
In addition, there is also an emergency flasher or “hazard” mode in which all six lights flash
on and off simultaneously as indicated graphically in the following figure.

Lc Lb La Ra Rb Rc

Hazard Idle
LR3

Your Tasks:

Task 1. The FSM for the Thunderbird tail lights has three inputs, “left turn”, “right
turn”, and “hazard”, and it has six outputs, lamps La, Lb, Lc, and Ra, Rb, Rc. Design
a state diagram and a state table for a FSM that controls the tail lights in the prescribed
fashion. The “hazard” setting has to override all other settings. If both the left and right
turn switches are on the FSM should default to the hazard setting. Minimize the number of
states used.
Task 2. Implement the FSM you designed in task 2 in SystemVerilog. Compile it in Quartus
Prime and run it on the DE10 board. Use switches SW2, SW1, SW0 for “hazard”, “left
turn”, and “right turn”, respectively. Use LEDR9, LEDR8, LEDR7 for Lc, Lb, La, and
LEDR2, LEDR1, LEDR0 for Ra, Rb, Rc. Use KEY0 for the (manual) clock of the FSM.
Test that the FSM makes the correct state transitions for all possible inputs.
Task 3. To make the tail lights flash automatically (rather than using KEY0 manually), a
continuous clock signal is needed. The DE10 board has a 50 MHz clock (with two outputs,
P11 and N14). Write a SystemVerilog module that divides this clock down to a frequency
suitable for the Thunderbird tail lights. Generate a 50% duty cycle clock and test your clock
module on the DE10 board, e.g., by letting an LED turn on and off.
Task 4. Combine the FSM from task 2 with the clock from task 3 for the complete Thun-
derbird tail light control module. Call this (top-level) module Thunderbird. Test the func-
tioning of all possible modes (left turn, right turn, hazard and any combination of the three
switches). Adjust the clock frequency as necessary to get the timing of the signals right.

Deliverables. You need to write and turn in a short report that consists of a separate
paragraph for each task and the Verilog code you wrote for the final Thunderbird module
in task 4 (including the code for all submodules). The paragraphs have to address the
questions asked (if any) for a given task and any insights, difficulties, and successes that
you encountered. You also need to assess to which degree your completion of each task was
successful. Submit your report, all sv files and the final sof file Thunderbird.sof of your
project and submit them to Canavas.
Variations for Coolness Points.

2012–2018,
c P. Mathys. Last revised: 11-12-18, PM.

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