International Journal of Engineering Trends and Technology (IJETT) – Volume 52 Number 3 October 2017

A Simulation Study of an Elevator Control

System using Digital Logic
Md. Mohsinur Rahman Adnan#1, Md. Zunaid Sikder#2 , Mohammed Mushfiquzzoha#3, Mahdi
Zulfikar#4
#1
Department of EEE, Shahjalal University of Science and Technology, Sylhet-3114, Bangladesh
#2,3,4
Department of EEE, Bangladesh University of Engineering and Technology, Dhaka-1000, Bangladesh

Abstract—This work presents a simulation study of elevator stopping and passengers getting in or out at
elevator control of an eight storied building. The that floor, will be available only at those specified
total system was built using digital logic Integrated numbers. Let the number in display be 0 (Initial
Circuits (ICs). The probable flow of events Condition, can be varied). This means the elevator is
associated with movement of an elevator had been now at Ground Floor (GF). Let a call occurs at some
inspected and used to create a flow chart for the i-th floor. As soon as the call occurs the lift will start
events. This flow chart had been used to create the upward counting 0-1-2-3-4-5 -.... –N till it reaches
logic to control the elevator and finally had been that i-th floor. Now let‟s assume as soon as the
transformed into a digital electronic circuit. This elevator has served the call at i, calls have occurred
electronic circuit consisted of several sub circuits at i-j and i+j floors simultaneously. If the lift has
which carried out sub routine tasks to ensure smooth been going upward it will go on moving to i+j- th
operation of the elevator as per the flow chart. floor, serve the call, and then change its direction to
Simulation had been carried out in Proteus software. come back at i-j-th floor to serve call. For initially
The proposed algorithm is easily scalable to “N” downward moving elevator, i-j th floor‟s call serving
floor elevator system. will happen first. After all the calls had been served,
if no more call occurs, the elevator will be waiting
Keywords— Elevator, Control, Digital Logic, at its last served floor and will be searching both
Proteus (ISIS Professional version 7.8 SP2). way(up/down) for new calls.
I. INTRODUCTION III. OPERATION PRINCIPLE
Multi-storied buildings now-a-days generally have The operation principle can be described in
elevator systems with them. These elevator systems following steps. The system should first collect the
need precise control to carry out the task assigned to current i-th floor‟s position relative to the building
them. Some previous research papers have already structure. Then the elevator should check if there is
addressed this problem [1][2][3]. But those control any call at current i-th floor. If there is, the elevator
approaches have used Programmable Logic Circuit should serve this call and flush memory for the call
(PLC) or microcontroller based logic control. Very to avoid double serving. Then, depending on the
few works had been carried out that created logic ongoing movement direction i.e. upward or
equations to be implemented by basic gates and downward, the elevator will search for calls in
available Integrated Circuits (ICs) in a digital logic higher (i++) or lower (i--) floors. If no call is found
circuit [4]. In this work such an approach had been in current movement direction it should change its
taken; no PLC or microcontroller based coding were moving direction and search for calls in opposite
incorporated, rather the total system was built using way. But if there is call found in already moving
digital logic ICs. Moreover focus had been given to direction, the elevator should increase floor count by
develop an algorithm for elevator control system 1 and search for call in the i+1-th floor (in case of
which can be used to implement an arbitrary “N” upward movement) or should decrease floor count
floor building‟s elevator control. For demonstration by 1 and search for call in the i-1-th floor (in case of
purpose, “N” had been taken equal to 8 in this work. downward movement) and thus go on repeating till
So, calculations of only 3 bits, denoting from 7th the highest or lowest floor with a call is reached and
Floor (111) to ground floor (000), had been served. Then the elevator should change direction
necessary to control the operation. and start moving the opposite way serving calls.
Continuous direction change and searching for calls
II. PROBLEM DEFINITION will happen if at any moment of system‟s operation
A system had to be designed that will count form the elevator has no more call to serve. The total
0 to N and N to 0 in an up-down manner process can be seen in the flow chart of fig 1.
continuously. But there will be a time delay at some
numbers taken as system inputs; these numbers will
indicate the floors where there are calls for the
elevator. A special time delay, which indicates

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 52 Number 3 October 2017

Fig 2: Up Counter Logic Circuit.

B. Down Counter
It has the operation principle of subtracting 1 to its
input. The truth table should look like this:

Table II: Truth Table for Down Counter

Current I3 I2 I1 Next O3 O2 O1
Floor Floor
(Input) (Output)
Fig 1: Flowchart for Controlling Elevator System. 7th 1 1 1 6th 1 1 0
6th 1 1 0 5th 1 0 1
IV. DESIGNING SUB-CIRCUITS 5th 1 0 1 4th 1 0 0
A. Up Counter 4th 1 0 0 3rd 0 1 1
It has the operation principle of adding 1 to its 3rd 0 1 1 2nd 0 1 0
input. The truth table should look like this: 2nd 0 1 0 1st 0 0 1
1st 0 0 1 GF 0 0 0
Table I: Truth Table for Up Counter

Inspecting the truth table we get the bitwise input

Current I3 I2 I1 Next O3 O2 O1
output relationships:
Floor Floor
𝑂1 = 𝐶 ∗ 𝐼1 + 𝐶 ∗ 𝐼1; Where C=0.
(Input) (Output)
𝑂2 = 𝐶 + 𝐼1 ∗ 𝐼2 + 𝐶 + 𝐼1 ∗ 𝐼2; Where C=0.
GF 0 0 0 1st 0 0 1
𝑂3 = 𝐶 + 𝐼1 + 𝐼2 ∗ 𝐼3 + 𝐶 + 𝐼1 + 𝐼2 ∗ 𝐼3;
1st 0 0 1 2nd 0 1 0
Where C=0.
2nd 0 1 0 3rd 0 1 1
3rd 0 1 1 4th 1 0 0 The circuit is given in fig 3.
4th 1 0 0 5th 1 0 1
5th 1 0 1 6th 1 1 0
C. Multiplexer 1 and 2
6th 1 1 0 7th 1 1 1
The multiplexers (MUXes) work as the decider
between the present floor and the next floor. After
Inspecting the truth table we get the bitwise input the binary value of current i’th and i+1’th and i-1’th
output relationships: floors had been calculated, there are three types of
𝑂1 = 𝐶 ∗ 𝐼1 + 𝐶 ∗ 𝐼1; Where C=1. action that could be carried out:
𝑂2 = 𝐶 ∗ 𝐼1 ∗ 𝐼2 + 𝐶 ∗ 𝐼1 ∗ 𝐼2; Where C=1.
𝑂3 = 𝐶 ∗ 𝐼1 ∗ 𝐼2 ∗ 𝐼3 + 𝐶 ∗ 𝐼1 ∗ 𝐼2 ∗ 𝐼3; Where
C=1.

The circuit is given in fig 2.

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 52 Number 3 October 2017

For the first multiplexer, three of the AND gates

have the bits of i+1-th floor at one of the inputs and
other three AND gates have the bits of i-1-th floor at
their inputs. The AND gates with i+1-th floor‟s bits
as input have the directional selector bit as the other
input, while the ones with i-1-th floor‟s bits have
the NOT of the directional selector bit as one of the
inputs. When the selector has value 1, i+1-th floor‟s
bits will emerge as is, but the i-1-th floors bits will
all become 0. If we bitwise OR these results using
OR gates, we finally have the i+1-th floors bits at
output. In reverse scenario, i-1-th floor‟s bits will be
the output of this multiplexer.

For the second multiplexer, three of the AND gates

have the bits of i-th floor at one of the inputs and
other three AND gates have the output bits of the
first MUX as their inputs. The AND gates with
Fig 3: Down Counter Logic Circuit.
outputs of first MUX have the call memory bit as the
i) Deciding to stay at same floor as no call is there to other input, while the ones with i-th floor‟s bits
serve. In this case the i’th floor should be chosen have the NOT of the call memory bit as one of the
inputs. When the call memory bit has value 1, first
instead of i+1’th or i-1’th floor.
MUX‟s bits will emerge as is, but the i-th floors bits
ii) Deciding to move upward as a higher floor has a will all become 0. If we bitwise OR these results
call to serve. In this case the i+1’th floor should be using OR gates, we finally have the first MUX‟s bits
chosen instead of i’th or i-1’th floor. at output. In reverse scenario, i-th floor‟s bits will be
the output of this multiplexer.
iii) Deciding to move downward as a lower floor has
a call to serve. In this case the i-1’th floor should be D. Shift Registers as Delay/Storage Elements
chosen instead of i’th or i+1’th floor.
The four bit directional universal shift register IC
74194 had been used to store the bits of the outputs
So, two multiplexers had been used to decide
and inputs of the previously described sub circuits.
between these options. The first multiplexer takes
The 74194 IC has four inputs with four outputs and
the i+1 and i-1 floor values as inputs and depending
have been used in our system to have a synchronous
on directional selector decides to move up or down
parallel input parallel output operation with
from the present floor i. This MUX gives either
capability of „HOLD‟. The operation was just like
i+1-th floor or i-1-th floor value as output. The
some sluice gate. Till it has a clock input bit HIGH it
second multiplexer works as a decider between the
will do nothing and hold the already present value of
old floor (i-th) and the new floor (i+1-th /i-1-th)
the output. But as soon as a HIGH occurs at the
values and depending on call memory decides
clock input, the four bits at input will be transferred
whether to keep the floor unchanged or to move on
to output bits and will hold them as output bits till
to next floor with new value obtained as a result
next clock HIGH bit occurs. Thus at each clock
from the first multiplexer.
HIGH bit, input values will be loaded at output and
the IC will be holding them indefinitely at output till
The logic used for a single bit is:
next clock HIGH occurs. Fig 4 shows the opeartion.
𝑂 = 𝐶 ∗ 𝐼1 + 𝐶 ∗ 𝐼2; Where
C= Directional Selector (1st MUX)/ Call Memory
(2nd MUX) bit
I1= i-1-th floor (1st MUX)/ present floor (2nd
MUX)‟s bit
I2= i+1-th floor (1st MUX)/ next floor (2nd MUX)‟s
bit
O=Output bit

The logic is quite easy to implement. Each of the

multiplexers could be made using basic logic gates:
six 2-input AND gates, three NOT gates and three 2-
Fig 4a: CLK is LOW, so input 010 is not passed to output, output
input OR gates. holds the previous value.

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 52 Number 3 October 2017

present floor‟s bits had been compared to B2B1B0

bits of the fixed floor‟s value. Eight such
comparators were used to denote eight floors from
000 to 111. The basic logic equation followed to
compare any two “parallel” bits (suppose A0 and
B0) and generate the three results:

i) 𝐴0 > 𝐵0: 𝑄1 = 𝐴0 ∗ 𝐵0
ii) 𝐴0 < 𝐵0: 𝑄2 = 𝐴0 ∗ 𝐵0
iii) 𝐴0 = 𝐵0: 𝑄3 = 𝐴0 ∗ 𝐵0 + 𝐴0 ∗ 𝐵0

This single bit operation can be implemented with

Fig 4b: CLK is HIGH, so input 010 is passed to output. basic logic gates as in fig 6.
The first 74194 IC (top one in fig 5) was used as the
supplier of input of Up counter and Down counter. It
took its input from the output of MUX#2 and
supplies this value as current i-th floor to the
counters with 10 second pulse at clock. Thus it
works in a feedback loop. The second 74194 IC
works as the supplier of floor number to comparator
sub circuit (bottom one in fig 5). Every second it
passes on the present floor value (output of MUX#2)
to the comparators to help them compare and find if
there is a new call at any floor.

Fig 6: Greater-Equal-Lesser Comparator for a single bit.

Similarly bitwise relation of A1, B1 and A2, B2

could be found. The final result is A=A2*A1*A0
and B=B2*B1 *B0. In this case A denotes the fixed
floor of the IC 7485 and B denotes current floor,
output of the bottom 74194 IC. The full eight floor
comparator circuit can be seen in fig 7.

F. Call Memory/Directional Selector

The call memory sub circuit uses eight 4 bit
synchronous counter IC 74190 as its main
component. This IC has the characteristic to count
up/down from a predefined value controlled by the
clock input synchronously. With each HIGH at clock
Fig 5: Counter->MUX->Storage/Delay Elements. The first part of
input the counter will change the output bits and can
elevator control circuit. count from 0000 to 1111 and vice versa. This idea
had been used to create the call memory and
E. Floor Comparator directional selector. The least significant bit of the
The four bit magnitude comparator IC 7485 has output will change between 0 and 1 with each HIGH
eight inputs and three outputs. It can compare two pulse at input. Whenever there is a call for a floor
inputs namely A3A2A1A0 with B3B2B1B0 and tell the counter associated with that floor will have a
whether A=B or A>B or A<B. HIGH pulse at clock and will make the LSB equal to
1. But as soon as the call is served a new HIGH
This idea had been used to compare the present floor pulse to the clock will be sent and LSB will become
value with a fixed value which denotes a floor and to 0. Same thing happens for directional selector.
deduce if the fixed input floor is below or equal or Whenever we need to change direction we just
above to present floor. Thus all floors above i’th change the LSB of the counter to get a direction
floor (i++) and all floors below i’th floor (i--) could change i.e. 0 means downward and 1 means upward
be identified. The A3 and B3 bits had always been movement. The operation of this IC in our circuit
grounded and only the A2A1A0 bits comprising can be seen in fig 8.

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 52 Number 3 October 2017

Fig 7: Connection diagram with eight 7485 IC for greater than, equal or less than comparison for finding relative position of all floors
compared to current floor. Some external LEDs and gates were used to check perfect working.
IC of each floor is connected to a two input
G. Interconnectors XOR gate. The other input is that floor‟s
1) Call and Distance Checker: Three outputs call switch. The output of this XOR gate
of a comparator IC 7485 (gives a floor‟s goes to clock input of the counter IC 74190
position with respect to current floor in the of that floor. When the switch is pressed
building structure) is fed to three 2-input one of the inputs of XOR is 1 while as the
AND gates and the other three inputs of A=B is 0 (as current floor is different than
these AND gates is the LSB of the call floor) so XOR output will be 1
associated counter IC 74190 (tells if there is meaning 74190 CLK is now HIGH. Then
a call at this floor). So three AND gates are 74190 LSB will become 1, indicating call
doing this: they are telling if this floor has a has occurred. Now if we remove the call
call and also telling the relative distance switch‟s 1 the 74190 LSB will still hold
between this floor and current floor. If the onto 1 even though the clock input has gone
AND gate with A<B input gives 1 means low because XOR output will now go to
present floor is above this floor with call, zero. As soon as A=B happens, the second
A>B input AND gate‟s 1 output will denote XOR input will be 1 while as the switch is
present floor is below this floor with call not pressed the first input holds 0 value. So,
and finally, A=B input AND gate‟s 1 output XOR output will be 1 which will set 74190
means the current floor and this 7485‟s clock input HIGH so the call will be
floor is the same one and also with call. If cancelled. Delay components can be used
all AND gates give zero that means no call in between XOR output and clock input so
is associated with this floor. that the elevator gets sometime between
reaching the floor with call and cancelling
2) Call Generator and Flusher: Eight basic the call by flushing memory; which we
switches have been used to generate calls at could say the serving time. The operation
a floor; if they are pressed there is call at can be seen in the following table III.
that specific floor. Actually they connect
the call memory bit generator‟s input to a 3) MUX Selector Generator: All eight
power supply if pressed. To cancel calls by comparator‟s outputs had been grouped into
flushing memory the A=B output of 7485 three final outputs of A>B, A<B and A=B

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 52 Number 3 October 2017

using three eight input OR gates. A>B

OR‟s output 1 means call in any above
floor and A<B‟s OR output 1 means call in
any below floor. These outputs had been
given to a two input AND gate. The output
of this AND is the selector of the second
MUX#2. If the AND output is 1 then there
is call in either above or below floor so the
new floor value that came from up/down
counter must be chosen instead of staying
at same floor. This same bit can be used to
change direction when no call is found at
above or below floors. This AND output 0
means no call in above or below floor,
which is a signal to stay on same floor and
keep on sweeping for new calls by Fig 8a: CLK is HIGH, LSB is made HIGH
changing direction. The A>B OR‟s output
can be used as selector of first MUX#1; if it
is 1 that means we have call at higher floor
so we take the Up counter‟s result. Same
could be done using A<B OR‟s output for
Down counter. When both OR has 1, we
need to go in the same direction as the
elevator was moving previously, so a
memory element needs to be introduced
which will denote the already going on
movement direction. This had been
implemented again by a 74194 IC. Till the
clock input is HIGH, the IC will not pass
the input to output, which has already been
shown in fig 4. The complete view is in fig Fig 8b: CLK is LOW, LSB is still HIGH
9.

Table III: Truth Table for Call Generator and Flusher.

7485 IC‟s Call XOR 74190 74190

A=B Output Switch Gate IC‟s IC‟s
Output CLK LSB

1=
1=Reached 1=Call Call
Floor Needs
0=No To Be
0=Not Yet Call Served
Reached
0=Call Fig 8c: CLK is HIGH, LSB is made LOW
Has
Been
Served
0 1 1 1 1
0 0 0 0 1
1 0 1 1 0
1 1 0 0 0

The total view of the interconnectors is as in fig 10.

Fig 8d: CLK is LOW, LSB is still LOW

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 52 Number 3 October 2017

Fig 9: A visual representation of eight 7490 IC checking for calls at all floors. These results had been unified using OR and AND gates to
create the selectors of MUX#1 and MUX#2.

Fig 10: Connection diagram with floor comparator, call memory/directional selector and interconnector sub circuits. The 2 nd part of the
elevator system.

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 52 Number 3 October 2017

Fig 11: Connection diagram of complete elevator circuit.

V. COMPLETE CIRCUIT
The complete elevator control circuit can be seen in between. Thus the whole system connects together
fig 11. The outputs of up and down counter have to control the elevator system.
been sent to MUX#1, which selects between their
outputs depending on directional selector bit. The VI. CONCLUSION
MUX#1 output and input of up and down counter is A digital logic based elevator control system for an
sent to MUX#2 which selects between them using eight storied building had been proposed in this
the call memory bit. The output of MUX#2 is again paper. Considering the events that occur during the
sent back to the inputs of up and down counter after movement of an elevator, a working flowchart had
a certain time delay via a delay element (shift been created. This flowchart was used to come up
register). Again another shift register is used to send with the functions that needed to be performed to
the MUX#2 output to the eight 7485 IC for control the elevator. Then these functions had been
comparing with their built in values and decide translated into logic equations and were
whether the built in values are above, below or same implemented using basic logic gates and available
to the output of MUX#2. At the same time, the call digital logic ICs into sub circuits. Combining these
switches are used to create call using 74190 IC‟s sub circuits the full control circuit had been created
LSB. This value together with 7485 outputs decides [5].
whether the elevator should move up, down or stay Acknowledgment
at the same floor. The interconnectors produce the The simulation of this work was done by using
directional selector bit and call memory bit using software 'Proteus' (ISIS Professional version 7.8
basic logic gates from the outputs of 7485 and 74190 SP2).
ICs, which are then used as selectors in MUX#1 and
MUX#2 with proper delay and storage elements in

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 52 Number 3 October 2017

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[2] K. M. K. S. Bandara, S. G. Aberathne, and S. D.
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[3] S. Huseinbegovic, S. Kreso, and O. Tanovic, “Design and
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[4] Monzurul Islam Dewan, Md. Arafat Mahmud, Md. Tashfiq
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[5] Youtube Channel of Md. Zunaid Sikder (2014) [Online].
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https://www.youtube.com/watch?v=eDzSo_VpeCQ

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