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Design of LNA using On-Chip Inductor for

Ku-Band Application
Vijay Sharma #1 and M.S.Hashmi #2
Email Id: {#1 vijays, #2 mshashmi} @iiitd.ac.in
Electronics and Communication, IIIT Delhi, Delhi, India

Abstract— A simple LNA design scheme operating at Ku-Band mitigate the effect of parasitic capacitance at the input of the
(17 GHz) is presented in this paper. The concept has been LNA.
validated in 0.09 ȝm CMOS process using on-chip inductors. It has
been shown that the on-chip inductor technique reduces the TABLE I: COMPARISON BETWEEN DIFFERENT LNA TOPOLOGIES [6]
contribution of spectral noise current due to inductor series Topology Advantages Disadvantages
resistance and also provides a good matching at the LNA input and
output at Ku-Band. The on-chip inductor also allows fine control Resistive termination Good input match Large NF
and adjustment of resonance frequency.
Common gate Better input match High NF
Keywords— Low Noise Amplifier; On-chip inductors; Noise; Series shunt Broadband i/o match Not stable
Ku-Band; feedback
Current reuse High gain External matching
I. INTRODUCTION required
Inductor Good output Stability issues
The first active amplification component of a receiver is a neutralization matching
Low Noise Amplifier (LNA) and its main function is to amplify
signal and suppress the noise of subsequent stages. In addition, /ŶĚƵĐƚŽƌ 'ŽŽĚDĂƚĐŚŝŶŐ >ĂƌŐĞƌĞĂ
ĚĞŐĞŶĞƌĂƚŝŽŶ
it should add as low noise as possible in the receiver. It is
accepted that the LNA regulates the overall performance of RF
receiver. Earlier, bipolar and GaAs were frequently used in the The paper is organized as follows. The next section presents
design of LNA due to their inherent gain and low noise figure the modular analysis of inductive source degenerated analysis.
characteristics. However, integration of these technologies on Subsequently, design and analysis of a rectangular spiral
the chip is extremely challenging. This has led to the wide inductor are presented in section-III. The section-IV provides
acceptance of CMOS based LNAs for on-chip applications. The details about the design and analysis of on-chip source
CMOS devices also possess low noise figure and higher gain degenerated LNA whereas section-V evaluates the design at
apart from its easy integration. There have been numerous 17GHz and compare with existing LNAs. Finally, section-VI
interesting reports of CMOS based LNA designs [1]- [8] with concludes the paper.
extremely good noise and gain performance.
The inductive source degenerated LNA [2] [3] provides II. LNA CIRCUIT DESCRIPTION AND ANALYSIS
extremely good noise performance and gain, but these operate
over a narrow band of frequencies. The distributed amplifiers
[4] addresses this concern to some extent, but consumes a large
DC current. On the other hand, the resistive shunt feedback [5]
and common gate [6] topologies are capable of operating over
a wide-band with good performance, but suffers from increased
noise figure due to substantial noise contribution from resistor.
Furthermore, shunt-series [7] and current resuse [8] topologies
offer good performance but suffer from stability issues and
large input/output impedance issues respectively. The Table-I
lists the limitations and advantages of the common LNA
topologies.
It is apparent that the inductive source degeneration topology
can provide relatively better matching, low noise figure, higher
stability, and higher gain among the usual topologies. It also
facilitates the control on frequency tuning to meet the
specifications. Keeping these aspects in perspectives, inductive
source degenerated LNA topology has been considered for Ku-
Band (17 GHz). In the design, the source degeneration and the Fig. 1: Inductive source degeneration LNA with Buffer
series inductors have been replaced by on-chip inductors. The
on-chip inductor has the potential to reduce the contribution of A two-transistor inductive source degenerated LNA topology
spectral noise current due to series resistance [9]. It also could is shown in Fig. 1. It utilizes two transistors to achieve desired

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low noise at the output. It is clear that the transistor M1 is in the It can be seen in Fig. 1 that there are two noise sources in
common source mode and M2 is in the common gate mode. The the input ie., the tunable inductor (Lg), and the input transistor
cascade configuration helps in achieving the high frequency (M1). The noise of the inductor can be reduced by improving Q
response and the high input impedance. The inductor Ls of the inductors. In general, off-chip inductor (Lg) possess
provides negative feedback and helps in obtaining a high higher Q as compared to on-chip inductor (Ls). However, Ls
stabilized gain. Buffer stage at the output helps in output will still add significant noise figure in the design. Input
matching and in driving the output. Inductors are replaced by transistor has the thermal noise of its drain and gate. The
on-chip inductors. It is important to mention here that the extra mathematical formulation relating the contributions in the total
components (inductors and capacitors) in this design leads to noise figure, F, is given in (3) [11].
slightly increased noise figure and area [10].
2 Ls 1 1
The key aspect in the design of LNA is the input impedance F = 1+ + *(1 + 2 ) (3)
matching. The input equivalent of the inductive source 3* Q * Rs 15* g m * Rs Q
degenerated LNA is given in Fig. 2 while the input impedance
of the transistor in series with Inductors is given in (1). It will Where Q is defined in (4).
be shown in a later section that the noise performance of the 1
LNA improves significantly once the impedance matching at Q= (4)
the input is achieved. g m 1* ω * Ls

The filter is the key component in this LNA for biasing

purposes. Here, Chebyshev configuration [12], depicted in Fig.
4, is used for realizing band pass filter in Ku-band as it
minimizes the error between the ideal and actual filter
characteristic over the range of the filter. These are sharper than
the other filters and show fewer ripples over the entire band.
The impedance of the filter should be matched to the source
impedance. Values of different components of Chebyshev band
pass filter are tabulated in Table II and the bandwidth of the
Fig. 2: Input equivalent of a modified raw device band-pass filter is around 5GHz (from 14.30 GHz to 19.30
ͳ ݃௠ ‫ܮ‬௦ GHz) as shown in Fig. 5 (a). The impedance of the filter is also
ܼ௜௡ ൌ ݆߱൫‫ܮ‬௦ ൅ ‫ܮ‬௚ ൯ ൅ ൅ ሺͳሻ matched to source impedance as shown in Fig. 5 (b).
݆߱‫ܥ‬௚௦ ‫ܥ‬௚௦

For matching, the imaginary part in (1) gets cancelled at the

resonance frequency and the input matching needs to equal the
source impedance (generally 50 Ÿ ). For the purpose of
understanding the gain parameter, the inductive source
degenerated LNA is depicted in Fig. 3.

Fig. 4. Chebyshev band-pass filter

TABLE II: VALUES OF COMPONENTS OF BAND PASS FILTER

Component Value
L1 1.34 nH
L2 0.92 nH
C1 69.5 fF
Fig. 3. Inductive source degeneration LNA gain stage
C2 113.6 fF

It is imperative to understand that the gain of this topology is

dependent on the equivalent transconductance given in (2) [10].
Apparently, the equivalent transconductance is dependent on
the unity current gain frequency ft and therefore the eventual
gain of the inductive source degenerated LNA is also dependent
on ft and not on the transconductance (gm) of the input stage
transistor (M1).

ωt
Gm = (2)
2 * s * Rs
(a) (b)
Fig. 5. (a) Bandwidth (b) Impedance of Chebyshev band pass filter


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III. ON-CHIP INDUCTOR The inductance for an on-chip inductor is expressed in (5)
[13], where μ 0 is the permeability of air, n is the number of
A simple on-chip spiral shaped inductor model is depicted in
turns, davg is the average diameters of the outer (dout) and inner
Fig. 6. It has the ability to reduce the contribution of spectral
turns (din), ρ is the fill factor defined as ρ = (dout-din)/ (dout+ din).
noise current due to the inductor series resistance and provide a
The coefficients C1, C2, C3 and C4 are given as 1.27, 2.07, 0.18,
good matching at the LNA input and output. It enhances the
and 0.13 respectively, for the rectangular spiral inductor. The
reliability and efficiency of silicon integrated RF cells. It also
design procedure of an on-chip inductor is [13]:
helps in reducing the effect of the parasitic capacitance at the
input of the LNA due to MOSFET used in design. The quality • Determine the values of L used in the design
factor of on-chip inductor is also high because of the less • Choose a value for ρ <1
resistance and parasitic. • Calculate the davg using (5).
• Determine dout and din
• Choose a constant value for spacing, s, between the
windings.

One thing to be noted here is that the value of inductance

increases, the length of the on-chip inductor increases for
constant no of turns.
Rectangular spiral inductor realization is easier than circular,
hexagonal, and octagonal spiral inductors. Square and
rectangular shaped inductors are more area efficient, like as an
example, if these utilizes 100% area of the wafer, whereas
Fig. 6. On-Chip inductor hexagonal, octagonal and circular shapes use 65%, 82.8 %, and
In ADS, the on-chip inductor is made with the micro-strip 78.5% respectively [14]. The rectangular inductor can
line. The parameters, depicted in Fig. 6, used in the on-chip accommodate more metal lines in the same area, having larger
inductor for Ku-band performance is given in Table III. For the inductance.
design of the inductor, at first, the resonant frequency is
IV. LNA DESIGN USING ON-CHIP INDUCTOR
decided. The resonant frequency of the inductor is dependent
on the value of the inductor and ft (unity gain bandwidth) of the In the modified design, shown in Fig. 8, the values calculated
system. A general inductor impedance characteristic is shown for the Chebyshev filters and the on-chip inductors are
in Fig. 7. It shows a negative impedance profile above 29 GHz incorporated. The chosen transistor is BSIM model [15] and is
(the resonant frequency) i.e., the inductor starts behaving like a used in ADS simulation. It is a compact model based on new
capacitor. It is important to mention here that the resonance MOSFET physics. It is chosen since it uses an enhanced version
frequency can be tuned through appropriate design approach. of the Ids equation from the LEVEL 2 models. It is an accurate
model of intrinsic input impedance for analog, digital, and RF
TABLE III: PARAMETERS OF ON-CHIP INDUCTOR
Name Description
applications. It also contributes less gate and thermal noise.
Subst Substrate instance name
N Number of turns
L1=dout Length of second outermost segment
L2=din Length of outmost segment
W Conductor Width
S Conductor spacing

Fig. 8. Inductive source degeneration LNA schematic with on-chip inductor

For the on-chip inductor, it is important to take care regarding

Fig. 7. Inductor properties over frequency the fabrication issues with respect to PCB fabrication
parameters. For simulation purpose, each segment of the spiral
is modeled as a lumped C-L-C ʌ-section with mutual inductive
C1
L = 0.5* μ0 * n 2 * d avg * C1 * (ln( ) + C2 + C4 ρ 2 ) (5) coupling to all other parallel segments including those of an
ρ


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image spiral. The inductive calculations include the end-effects dB at the operating frequency of 17 GHz. Furthermore, the
and differing lengths of coupled segments. The capacitive Noise Figure of the system is 2.6 dB at 17 GHz as shown in Fig.
components account for capacitance to ground, coupling to the 10. A comparison of simulated on-chip inductor LNA with
parallel adjacent segments, and the coupling to the next parallel existing LNA is given in Table I. Table I shows that the
segments beyond the adjacent on both sides. simulated on-chip inductor LNA has the better performance as
The frequency dependence of the skin effect is included in the compare to [17], [18].
conductor loss calculation. A smooth transition is provided Table I. Comparison of on-chip inductor LNA with exiting LNAs
from DC resistance to resistance due to skin effect at high LNAs Operating Gain Noise Figure
frequencies. Dielectric loss is also included in the loss Frequency (Simulated) (Simulated)
calculation. In layout, the number of turns is rounded to the [17] 11 GHz 12 dB 3 dB
nearest quarter-turn [16]. The connection will align at the inside
edge at pin 1 and the outside edge at pin 2, unless W1 (width of [18] 13 GHz 10 dB 4.86 dB
the line that connects to pin 1) < W or W2 (width of the line that This paper 17 GHz 21 dB 2.616 dB
connects to pin 2)>W, in which case the conductors are
centered. VI. CONCLUSION
V. RESULTS Firstly, the LNA and other important blocks such as filter, and
Source degeneration LNA with on-chip inductor schematic the on-chip inductor are explained in detail. In this context, a
shown in Fig. 8 has been designed in 0.09 μm CMOS new input matching topology for tunable narrowband LNA has
technology. The W/L ratio of M1 is 80.16 μm/0.09 μm. The been discussed and a fully tunable LNA has been designed in
LNA is designed at 17 GHz in Ku-band by proper selection of 0.09 μm technology. The design has been validated through the
on-chip inductor parameters. All the on-chip inductor has 2 ADS RF simulation tool. The simulations show good results in
turns and a rectangular shape. The value of resistor present in terms of gain, bandwidth, and noise figure at 17 GHz. In future,
the load is 6Ÿ and the values of Lg, Ls and L are 864 pH, 12 power saving mechanisms can be explored by trading-off with
pH, and 614 pH respectively. the usual design parameters.

Fig. 10. Noise figure of the LNA

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௙ Circuits, vol. 45, no. 3, pp. 502–509, Mar. 2010.
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'௙


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