IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO.

12, DECEMBER 2006 2641

A 20-mW 640-MHz CMOS Continuous-Time

61
ADC With 20-MHz Signal Bandwidth,
80-dB Dynamic Range and 12-bit ENOB
Gerhard Mitteregger, Member, IEEE, Christian Ebner, Member, IEEE, Stephan Mechnig, Member, IEEE,
Thomas Blon, Member, IEEE, Christophe Holuigue, and Ernesto Romani, Member, IEEE

Abstract—A wide bandwidth continuous-time sigma-delta ADC, ADCs exhibit an inherent anti-alias filter function, enabling the
operating between 20 and 40 MS/s output data rate, is imple- design of alias-free ADCs. Thus, high-order anti-alias filters,
mented in 130-nm CMOS. The circuit is targeted for applications which are either power-hungry in the case of active filters or
that demand high bandwidth, high resolution, and low power, such
occupy considerable board space in the case of highly linear
61
as wireless and wireline communications, medical imaging, video,
and instrumentation. The third-order continuous-time mod- passive filters, can be avoided. These unique features are partic-
ulator comprises a third-order RC operational-amplifier-based ularly important for mobile applications (e.g., wireless, instru-
loop filter and 4-bit internal quantizer operating at 640 MHz. A mentation and measurement), since these are battery powered
400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, and limited in available space.
61
generating the low-jitter clock for the jitter-sensitive contin-
uous-time ADC from a single-ended input clock between 13.5 To realize a practical general-purpose CT ADC IC, sev-
and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero eral changes are applied with respect to conventional topolo-
(NRZ) DAC pulse shaping is used. The excess loop delay is set to gies. First, the CT modulator has to be able to operate over a
half the sampling period of the quantizer and the degradation of wide sampling range, e.g., 20–40 MS/s. Second, the ADC has to
61
modulator stability due to excess loop delay is avoided with a new comprise a PLL to generate all the high-speed low-jitter clocks
architecture. The ADC achieves 76-dB SNR, 78-dB THD,
from an external reference clock. Third, all tuning and calibra-
61
and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at
an OSR of 16. The power consumption of the CT modulator tion functions have to be performed automatically during power
itself is 20 mW and in total the ADC dissipates 58 mW from the up.
1.2-V supply. This paper describes the design and system considerations of
the CT modulator and LC-PLL of a general-purpose CT
61
Index Terms—Analog-to-digital conversion, CMOS analog inte-
grated circuits, continuous-time modulation, continuous-time ADC. The paper is organized as follows. Section II describes the
filters, delta-sigma modulation, low-pass filter, low power design, system architecture of the modulator and the LC-PLL. The cir-
low-voltage design, multibit internal quantization, sigma-delta cuit implementation is discussed in Section III, and Section IV
modulation.
presents the measurement results. Finally, Section V concludes
the paper.
I. INTRODUCTION
II. SYSTEM ARCHITECTURE

T ODAY’S discrete high-speed, high-resolution analog-to-

digital conversion (ADC) ICs are based on pipeline conver-
sion technology. These Nyquist-rate ADCs are the core building
A. CT Modulator Architecture
As the maximum possible sampling frequency is limited by
blocks of analog receive front-ends. Significant effort has to be technology, architectures with low over-sampling ratios (OSRs)
put into the signal conditioning preceding Nyquist-rate ADCs are preferable for a signal bandwidth of 20 MHz. To suppress
and the generation of both voltage and time references. Over- quantization noise sufficiently for 14-bit performance, multibit
quantization and at least a third-order noise-transfer function
sampling ADCs trade digital signal processing complexity
for relaxed requirements on the analog components compared (NTF) are essential.
to Nyquist-rate ADCs [1]. Recently, the popularity of contin- The proposed CT modulator architecture is shown in Fig. 1.
uous-time ADCs has been growing for application-specific The modulator comprises a 4-bit internal quantizer, operating
at 640 MHz with an oversampling ratio of 16, and a third-order
ICs [2]–[4]. Moreover, continuous-time implementation of
ADCs extends the input frequency range from a few 100 kHz up single-loop filter. In order to save power and maintain a good
to a few 10 MHz and proves to be very power efficient [5]–[7]. alias filter characteristic, a combination of feedforward and
Owing to the nonsampling input stage (sampling takes place feedback stabilized loop filter is implemented [2] (see Fig. 1).
after the continuous-time loop filter), continuous-time (CT) The 4-bit quantizer, including the NRZ feedback DAC, is
connected to the output of the loop filter. The quantizer delay is
set to half of the sampling period. This large delay is compen-
Manuscript received April 10, 2006; revised August 21, 2006. sated exactly by an additional feedback path (see Fig. 1).
The authors are with the Xignal Technologies AG, Munich, Germany (e-mail:
[email protected]; [email protected]). Therefore, placement of NTF poles is not limited by the nega-
Digital Object Identifier 10.1109/JSSC.2006.884332 tive effect of quantizer delay on loop stability. A maximum NTF
0018-9200/$20.00 © 2006 IEEE
2642 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 12, DECEMBER 2006

Using the “d2d” (discrete-to-discrete) function of the

MATLAB Control System Toolbox [8] an equivalent transfer
function in is derived:

In this representation, the half sample delay (i.e., ) of

the quantizer can be easily incorporated by removing a factor
of from the loop transfer function, or in other words by
multiplying with , as shown in the equation at
Fig. 1. Continuous-time 61 modulator architecture. the bottom of the page.
As shown above, after multiplication by , a constant
term can be split off from the resulting transfer function
of the loop filter. This is the direct feedback
path . The transfer function is then
converted to continuous time using the “d2c” (discrete-to-con-
tinuous) function of the MATLAB Control System Toolbox. In
our case of an NRZ feedback DAC, using the “zoh” (zero order
hold) method of this function already accounts for the feedback
pulse shape.

B. Clock Jitter Sensitivity

In discrete-time modulators, clock jitter has an influence on

the sampling of the input signal only, as the feedback signal is
processed in discrete time. Therefore, clock jitter only modu-
lates the input signal, but has no influence on the quantization
noise present in the feedback signal. In continuous-time modu-
Fig. 2. Noise-transfer function (NTF) plot. lators, the situation is different, as the sampling jitter of the in-
ternal ADC is suppressed by the loop gain, while the feedback
DAC modulates both signal and shaped quantization noise with
noise gain of approximately 12 dB can be realized as the quan- the clock jitter. This has different effects, depending on the jitter
tizer is multibit; hence, the resulting overload range just slightly frequency. Wideband jitter modulating both the signal and the
reduces the dynamic range. The chosen NTF is shown in Fig. 2. shaped quantization error fills the signal band with white noise,
The following outlines the procedure used to determine the thus reducing the achievable SNR. Fortunately, this jitter can
direct feedback coefficient such that quantizer delay is canceled be suppressed by the integrated LC-PLL and by using multibit
exactly. First, an NTF in the z-domain is chosen. From this, the NRZ feedback. Low-frequency jitter does not have the effect of
loop transfer function is derived: downconverting quantization noise, but it creates, as in a dis-
crete-time modulator, sidebands around the input signal, which
may not be tolerable in applications processing close to carrier
signals. Here, apart from reducing flicker noise generation in the
PLL and clock tree by using steep transitions, the ADC IC relies
on the performance of the external clock.
MITTEREGGER et al.: A 20-mW 640-MHz CMOS CONTINUOUS-TIME ADC 2643

Fig. 3. Four-bit continuous-time 61 modulator.

Fig. 4. Realization of the zero order quantizer feedback path. Top: direct feed-
back path. Center: direct feedback path is shifted before last integrator by intro-
III. IMPLEMENTATION duction of a derivator. Bottom: CT derivator is replaced by DT derivator.

A. Continuous-Time Modulator
Fig. 3 shows a block diagram of the 4-bit CT modulator
including the excess loop delay compensation. The third-order
loop filter is realized as an active-RC operational-amplifier filter.
The trimming of these integrator time constants is accomplished
by switching binary-weighted capacitor units into the integrator
feedback. Thereby, process-dependent RC time constant varia-
tions are minimized. A large stability margin of the NTF would
be required otherwise as the RC time constant variation is the
dominant source of NTF pole variation.
DAC1 realizes the first feedback (see Fig. 1). DAC2
is used to realize the second feedback , and together with
DAC3 it is used to realize the direct feedback path around the
4-bit quantizer , as will be explained later. The digital input
Fig. 5. Generation of the RZ pulse shaped time-discrete differentiated feedback
of DAC3 is delayed by two latches to realize a full clock pe- signal.
riod delay (see Fig. 3). The first latch is part of the 4-bit flash
ADC and sets the delay exactly to a half clock period. The delay
of the quantizer is therefore independent of process and oper- of DAC2, a delayed version, signal 2, that is output by DAC3
ating conditions as are the other system parameters, which al- half a clock period later. In effect, signal 3 is proportional to the
lows tight stability margins for the NTF. To reduce capacitive derivative of the quantizer output, and has RZ pulse shaping.
loading of the loop filter, the comparators of the flash ADC use This excess loop delay compensation avoids the need for an ad-
minimum-size input transistors whose offset is calibrated during ditional summing amplifier or differentiation logic in the digital
start up. domain which would increase power consumption and excess
The realization of the zero-order feedback path would either loop delay.
require a summing amplifier or an RZ DAC including differ- 1) Loop Filter: The third-order noise shaping loop filter is re-
entiation and control logic. Both solutions introduce additional alized as an active—RC operational-amplifier filter (see Fig. 3).
loop delay and increase power consumption. Additionally, reg- The advantages of this implementation compared to G /C fil-
ulation of the common-mode at the RZ DAC output increases ters are high linearity and high output signal swing, and that
design complexity and power consumption. To avoid this, a dif- it provides a good virtual ground for the modulator feedback
ferentiation operation is introduced in the direct feedback path DACs. This eases design, especially with low supply voltages.
which allows the signal to be fed to the input of the last inte- In order to save power and to maintain a good anti-alias filter
grator (see Fig. 4). In this way, a frequency-independent feed- characteristic in the signal-transfer function (STF), a combina-
back results and an additional summing amplifier is avoided. As tion of a feedforward and a feedback stabilized loop filter is im-
a continuous-time differentiation is difficult to implement, this plemented [2]. The feedback path to the second integrator input
is instead carried out in discrete time. To have the direct feed- is replaced by the feedforward path in order to eliminate
back signal available at the correct time at the output of the last one DAC (see Fig. 1). In contrast to a feedforward stabilized
integrator, the differentiation uses a half clock period delay. loop filter where one integrator is filtering out-of-band signals,
As shown in Fig. 5, at circuit level the discrete time differen- there are two integrators in this design. Simulation shows that
tiation is carried out by subtracting from the feedback signal 1 a 620-MHz full-scale interferer at the input of the modulator is
2644 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 12, DECEMBER 2006

Fig. 6. Block diagram of a four-stage operational amplifier with feedforward Fig. 7. Bode plot of a conventional Miller operational amplifier together with
G -C compensation. a plot of a four-stage operational amplifier. Transit frequency is 2 GHz.

filtered by two integrator stages and by the NTF and results in is considerably smaller than unity at this frequency. Thus,
a 20-MHz alias which is 78 dB below full scale. Another ad- stability is determined only by the two-stage system consisting
vantage of this loop filter topology is that the bandwidth of the of the third integrator plus the output stage.
first integrator can be large, as there is no feedback to the fol- Fig. 7 compares the bode plot of a conventional Miller oper-
lowing stage and the output signal swing of this integrator can ational amplifier with a plot of a four-stage operational ampli-
be scaled only with its bandwidth. A high bandwidth of the first fier. Both have a transit frequency of 2 GHz. As the gain of the
integrator suppresses the thermal noise of the following integra- four-stage amplifier near the transit frequency is mainly deter-
tors. The feedback path creates a notch in the NTF which mined by the third integrator, the phase and gain margins are
further reduces quantization noise in the 20-MHz signal band similar to the Miller operational amplifier. For lower frequen-
[1]. cies, the other two paths contribute to the overall gain, and gain
A disadvantage of the realized loop filter topology is that, un- slopes with 40 dB per decade in the case of two stages and 60 dB
like a feedforward stabilized loop filter, it does not automati- per decade in the case of three stages are achieved. Therefore,
cally recover from overload. A feedforward stabilized loop filter the four-stage operational amplifier achieves much higher gain
can be designed to remain stable during overload, so that only within the signal band as well as at the loop filter integrator
the first-order path maintains gain, while the higher order paths bandwidth.
are saturated. Due to the second feedback path in the loop This leads to less excess phase shift of the integrator and
filter, the modulator is only conditionally stable, as the inte- better linearity in the band of interest. To put it another way, with
grator stages saturate during overload and the gain drop makes a much lower transit frequency the same gain at the integrator
the system unstable. To avoid oscillation, an overload detection bandwidth is possible and therefore power is saved. Because
circuit is included in this design. Two comparators are detecting high gain is achieved by cascading amplifier stages, minimal
the overload level at the quantizer. In this case, the feedback device lengths can be used, which makes low power consump-
capacitor of the second integrator is shorted by two switches. tion and/or high bandwidth possible. Very low supply voltages
Therefore, an unconditionally stable second-order behavior of are possible as there is no need for cascode transistors.
the modulator results. To overcome the conditional stability of this multistage struc-
The highest integrator bandwidth in this loop filter design is ture, the feedforward paths are designed such that the lowest
300 MHz. Since excess phase shift of the integrator stages adds order path saturates last. Thus, when the operational amplifier
to the overall excess loop delay, conventional two-stage oper- is overdriven, it reduces to an unconditionally stable system.
ational amplifiers with very high bandwidth, which consume a As shown in the simplified schematic in Fig. 8, the first inte-
lot of power, would be necessary. It may even be that the re- grator contains a four-stage operational amplifier which dissi-
quired bandwidth is infeasible in the target technology. Because pates 1.2 mW in the first differential pair to satisfy the thermal
of the high linearity requirement of a THD dB, G -C noise requirement. To drive the resistive loads of the following
integrators are not an alternative. To reduce the required band- integrator stages, a feedforward class-AB output stage is used.
width, the conventional two-stage Miller operational amplifiers As the second and third integrator stages have relaxed require-
are replaced by multistage operational amplifiers with feedfor- ments regarding linearity, three-stage operational amplifiers are
ward G -C compensation [10]. used. The gain stages are simple differential stages with low DC
The concept of multistage operational amplifiers is shown gain. To achieve sufficient power supply rejection, the design is
in Fig. 6. The operational amplifier consists of three signal fully differential throughout.
paths, with different transit frequencies and different num- 2) RC Trimming: As discussed in Section I, to ensure sta-
bers of gain stages. At the overall transit frequency, only the bility of the modulator and SNR performance over the dif-
first-order path—consisting of the third integrator plus ferent output data rates, the loop filter is tuned to different sam-
output stage—has unity gain. All other paths show a gain that pling frequencies. An automatic capacitor trimming scheme is
MITTEREGGER et al.: A 20-mW 640-MHz CMOS CONTINUOUS-TIME ADC 2645

Fig. 8. Simplified schematic of a four-stage operational amplifier with

class-AB output stage.

Fig. 10. Four-bit quantizer with 4-bit flash ADC and reference voltage gener-
ation plus feedback DAC.

for the comparator inputs are generated by copying an inter-

nally available reference voltage onto a unit resistor string. The
15 comparators of the internal flash ADC consist of a double
differential input stage and a regenerative latch at the output
as shown in Fig. 11. The timing is as follows. During reset,
the input stage has a small time constant and a gain consider-
ably smaller than one. In this way, a short sampling pulse is
obtained and, hence, the additional phase shift in the quantizer
input stage is negligible. When the reset switch is opened, the
current from the input pairs generates a voltage difference on
the cross-coupled load transistors. Immediately afterwards, the
switches to the output latch are closed and the output latch is
Fig. 9. Left: Two loop filter stages with trimmable capacitors in the integrator
started. This latch has a very small regenerative time constant
feedback. Right: Implementation of the trimmable capacitor with a 7-bit binary and amplifies the voltage difference to full logic levels. In order
weighted capacitor array. to minimize kickback, the switches to the input stage are opened
before the output reaches a large voltage difference. Because
the comparators use minimum-size input transistors, an offset
employed to tune the time constants of the active-RC integrators. trimming circuit generates a current which compensates
The integrator feedback capacitors are implemented as banks of the input device offsets such that the error after trimming is
digitally switched binary weighted elements (see Fig. 9). The below 1/4 LSB. The quantizer offset calibration is done during
digital switching code is provided by a trimming circuit which startup simultaneously for all 15 flash ADC input stages (see
compares a replica of the RC time constant to the period of the Fig. 11). The loop filter is disconnected during calibration and
input reference clock. This circuit works by charging a replica the input stages are connected to the common-mode voltage,
of the capacitor bank with a fixed current for a time equal providing zero differential input voltage to all comparator
to one clock period. The resulting voltage across the capacitor inputs. The signal TRIM_MODE starts the trimming and the
is then compared with the reference voltage , counter increments until each individual comparator
where is a copy of the same current and is a replica resistor. toggles. Then the counter stops and leaves at a value that
Depending on the result of the comparison, the tuning word is compensates the offset voltage.
incremented or decremented so that and thus 4) Feedback DACs: As the loop filter implements one feed-
. forward path, only two DACs would be necessary, yet to re-
The tuning range is chosen large enough to compensate for a alize the differentiated RZ feedback, a third DAC operating on
variation of the data rate between 20 and 40 MS/s and to com- a clock, delayed by half a sampling period, is required (see
pensate for process-dependent variation of the RC time constant Fig. 12). DAC1 realizes an input to the loop filter and, hence,
of 40%. A 7-bit tuning word provides the required tuning has the highest requirements on linearity and noise performance,
range while allowing a tuning accuracy of better than 2%. which requires a large device size to get the necessary matching
Thus, the ADC can operate automatically over the range of 20 and flicker noise performance. DAC2 realizes the second feed-
to 40 MS/s. back which creates the first-order path. In combination with
3) Four-bit Flash ADC: The quantizer in the modulator DAC3, it further realizes the differentiated RZ feedback which
(Fig. 10) consists of a reference ladder and a 4-bit flash ADC compensates the quantizer delay. As any nonidealities of DAC2
with a thermometer-coded output that is sampled by the latches and DAC3 are suppressed by the gain of the first two integra-
of the current-steering DAC. The differential reference voltages tors, the requirements on noise and linearity can be relaxed. For
2646 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 12, DECEMBER 2006

Fig. 11. Left: Comparator schematic of the 4-bit flash ADC consisting of a double differential input stage and a regenerative latch at the output. Right: Schematic
of the flash ADC trimming circuit.

Fig. 12. Combined DAC unit cell for DAC1–DAC3.

all three DACs, the gate overdrive voltage is chosen to be rela- Fig. 13. LC-PLL architecture.
tively high to get good device matching and thermal noise per-
formance. The total area of DAC1 is chosen according to the for-
mulas given by van den Bosch et al. in [13] for sufficient yield order charge pump PLL with passive loop filter and a LC-VCO.
at a linearity of 76 dB. All DACs are cascoded to increase their The 13.5–40-MHz capture range is implemented by a combina-
output resistance and shield the large drain capacitance of the tion of a programmable feedback divider and a digital loop pro-
current-source transistors from the tail node of the switches. The gramming a 6-bit metal–insulator–metal capacitor (mim-cap)
switch transistors operate always in saturation mode, which fur- array in the VCO. This digital loop continuously calibrates the
ther increases output resistance and reduces both glitch energy VCO by sensing the control voltage. It allows the reduction of
and clock feedthrough. This is achieved by driving them with re- the VCO gain and thus lowers the upconversion of the LC tank
duced voltage swing. The edges of the driving dual rail signals noise into phase noise [11]. The implemented VCO gain and the
have a high crossover point to ensure that one of the switches analog tuning range allow the loop to compensate the frequency
is always on, which avoids charging and discharging of the tail change due to temperature variation. Thus, switching glitches
node. The preceding dynamic dual rail latches and drivers are are avoided during normal operation. The tank of the VCO is
sized to provide very steep transitions, which reduces sensitivity realized using an on-chip inductor, a MOS varactor [12] in ac-
to power supply ripple and device noise. The biasing circuit uses cumulation and the programmable array of mim-caps. To atten-
a resistor that matches to the modulator input resistors to derive uate the jitter of the input clock, the bandwidth of the loop is set
the DAC current from a reference voltage. Thereby, a fixed input to 450 kHz and a third-order loop filter is used. The loop filter
to output gain is ensured. To remove any noise generated by the is designed such that the noise of the resistors can be neglected
biasing circuit of the DAC, the biasing voltage of the current relative to the VCO phase noise, as shown in Fig. 14. This re-
source transistors is filtered by an RC-filter, which uses an ex- quires a large loop filter capacitor, which is realized by a vertical
ternal capacitor to set the pole to below 500 Hz. metal plate capacitor. A n-well shield is placed between the ca-
pacitor and the substrate. To increase power supply rejection,
B. LC Phase-Locked Loop the shield is connected to the tail voltage of the VCO. Sampling
The LC PLL supplies the CT modulator with a low-jitter the 40-MHz clock output with the 640-MHz clock eliminates
640-MHz sampling clock and provides a clock multiplying and feedback divider noise in the total output phase noise. Large de-
clean-up function. The chosen architecture (Fig. 13) is a fourth- vices are used in the sampling D-flip-flop to reduce flicker
MITTEREGGER et al.: A 20-mW 640-MHz CMOS CONTINUOUS-TIME ADC 2647

Fig. 15. FFT (32 768pt.) for a 4-MHz full-scale input signal. SNR is 76 dB,
Fig. 14. PLL phase noise and contributors.
0
THD 78 dB.

TABLE I
PERFORMANCE SUMMARY

noise generation, which is particularly important to improve the Fig. 16. FFT (2 097 152pt.) for a 16-MHz full-scale input signal. SNR is 76 dB.
phase noise performance at low-frequency offsets. The phase Top insert: Upper side band of the input signal in logarithmic scale. The jitter
noise simulation of the 640-MHz sampling clock, as depicted in transfer characteristic of the PLL is visible in the noise floor.
Fig. 14, has been confirmed by a fast Fourier transform (FFT)
of the ADC output signal.

IV. MEASUREMENT RESULTS

The ADC is implemented in a 130-nm 8-metal-layer CMOS
process. It is assembled into a QFN 40 package with an exposed
pad that is used as analog ground. The digital ground is supplied
via two pins. Analog and digital supplies of the evaluation board
are connected to one common power supply. The ADC is nom-
inally supplied with 1.2 V, while it is fully functional between
1.0 V and 1.4 V. The total power consumption is 58 mW. The
power consumption of the building blocks is listed in Table I.
All measurements were performed providing the single-ended
clock input of the ADC with a 40-MHz crystal oscillator refer-
ence clock.
A transformer (turn ratio 1:1) converts the single-ended input Fig. 17. SNR versus input signal level for a 3.68-MHz signal. Peak SNR is
signal to a balanced differential signal input to the ADC. Sinu- 76 dB. Dynamic range is 80 dB.
soidal input signals with a maximum input voltage of 1.6-Vpp
differential are supplied to the ADC. The captured output data signal, the THD is 78 dB. A lower noise floor in Fig. 16 re-
is windowed by a Kaiser window and a Fourier sults as the FFT size is 2 097 152 data points instead of 32 768.
transformation is applied. The spectra resulting from full-scale Fig. 17 presents the SNR versus signal amplitude. The dynamic
4-MHz and 16-MHz input signals can be seen in Figs. 15 and 16. range (defined as the range where SNR ) is 80 dB. The alias
For both signals, the peak SNR measures 76 dB. For the 4-MHz performance is evaluated by sweeping a sinusoidal input signal
2648 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 12, DECEMBER 2006

5 dB owing to the applied reference clock and the underlying

ADC noise.

V. CONCLUSION
An ultra-low-power CT ADC IC is implemented in
130-nm CMOS; Fig. 19 presents a photograph of the chip,
which has a silicon area of 9 mm . The CT modulator
itself occupies just 1.2 mm and consumes only 20 mW. The
modulator achieves a SNDR of 74 dB or an effective number
of bits (ENOB) of 12 bits over 20-MHz signal bandwidth. This
results in a figure of merit, defined as ),
of 122 fJ per conversion. The CT ADC IC comprises, in
addition to the modulator, reference and clock generation and a
decimation filter. Supplied from a common 1.2-V power supply,
the total power consumption is 58 mW. The performance is
Fig. 18. Alias filter characteristic. Dashed line: measured alias signal.
summarized in Table I.
The achieved SNR, low distortion and its anti-alias perfor-
mance at very low power consumption promotes discrete CT
ADCs as alternative to Nyquist ADCs [14].

ACKNOWLEDGMENT
The authors wish to thank H. Bachschneider, E. Engelhardt,
and S. Heib for their skillful layout work, F. Jansen for chip and
board design and measurement, and B. Fischer for the excellent
CAD support.

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MITTEREGGER et al.: A 20-mW 640-MHz CMOS CONTINUOUS-TIME ADC 2649

[15] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, E. Ro- Thomas Blon (M’99) was born in Buchloe,
mani, A. Melodia, and V. Melini, “A 14b 20mW 640MHz CMOS CT Germany, in 1968. He received the Dipl. Ing.
16 ADC with 20MHz signal bandwidth and 12b ENOB,” in IEEE Elektrotechnik degree from Technische Universität
ISSCC Dig. Tech. Papers, Feb. 2006, pp. 131–140. München, Munich, Germany, in 1994.
From 1994 to 1998, he was with the Siemens
Gerhard Mitteregger (M’03) received the M.S. Seminconductor Division in Munich working as an
degree in electrical engineering from the Technische Analog Design Engineer on xDSL analog front-ends.
Universität Graz, Graz, Austria, in 1996. From 1999 to 2001, he was with the R/W Channel
From 1995 to 1998, he was with the Siemens Group of Infineon Technolgies Corporation, based
Semiconductor Division, Munich, Germany, working in Santa Cruz, CA, designing high-speed CMOS
as an Analog Design Engineer on analog front-ends mixed-signal building blocks for hard disk drive
and clock multiplying units for Security ICs. In 1998, and optical storage applications. In 2002, he joined Xignal Technologies
he joined the Mixed-Signal Department of Infineon AG, Munich, Germany, where he is involved in the design of highly linear
Technologies AG, where he designed VGAs, active data processing circuits such as low-noise amplifiers and data converters. He
filters, clock and data recovery, and sigma-delta data currently holds nine international patents.
converters for T1/E1 and DS3/E3/STS1 transceivers.
In 2000, he joined Xignal Technologies AG, Munich, where he developed
highly linear 12/14-bit continuous-time sigma-delta data converters for VDSL
and ADSL2 transceivers. Additionally, he was involved in the design of Christophe Holuigue was born in Lille, France, in
clock and data recovery and clock multiplying units for high-speed multigi- 1974. He received the engineering diploma from the
gabit transceivers for communication products. Since 2004, he has been in Institut Supérieur d’Electronique du Nord (ISEN),
charge as a Principal Design Engineer for the system and circuit design of Lille, France, in 1998.
high-speed/high-resolution continuous-time sigma-delta modulators for ADC He joined the Mixed-Signal Department of Infi-
ICs. He currently holds 10 international patents. neon Technologies AG, Munich, Germany, in 1998
where he designed active filters and variable gain am-
plifiers for wireline ICs. Since 2001, he has been with
Xignal Technologies AG, Munich, as a Senior De-
Christian Ebner (M’99) received the diploma in sign Engineer. His work is focused on voltage-con-
electrical engineering from Technische Universität trolled oscillators and phase-locked loops for high-
München, Munich, Germany, in 1997. speed data communication ICs.
In 1997, he joined Infineon Technologies AG, Mu-
nich, Germany, where he was involved in the devel-
opment of embedded memories. In 1999, he moved
to Infineon’s Mixed-Signal Department where he de- Ernesto Romani (M’00) was born in Giulianova,
signed data converters for GSM and UMTS baseband Italy, in 1972. He received the Laurea degree in elec-
ICs. In 2001, he joined Xignal Technologies AG, Mu- trical engineering from the University of Ancona,
nich. Since then, he has been working on both the ar- Italy, in 1997.
chitectural and circuit level for a broad range of prod-
ucts including VDSL AFEs, 10-Gbit SerDes, high-speed 16 ADC ICs, and
From 1999 to 2002, he was with Infineon Tech-
nologies AG, Munich, Germany, where he worked on
clock synthesis ICs. embedded memories and developed analog circuits
for DRAMs. In 2002, he joined Xignal Technologies
AG, Munich, where he develops mixed-signal and RF
circuits for telecommunications.
Stephan Mechnig (M’97) was born in Worms,
Germany, in 1966. He received the Dipl. Ing. degree
from the FHT Mannheim, Germany, in 1993, and
the M.Sc. degree in electrical engineering from the
University of Southampton, Southampton, U.K., in
1994.
He was with Philips Semiconductor, Southampton,
U.K., from 1994 to 1998 as a member of the Mixed-
Signal IC design group, where he was involved in the
design of ADCs and DACs for compact-disc (CD)
applications. From 1998 to 2001, he was with Infi-
neon Technologies AG, Munich, Germany, as a Principal Mixed-Signal Design
Engineer. He was engaged in the design and development of high-resolution
delta-sigma data converters for GSM baseband ICs and digital audio appli-
cations. Since 2001, he has been with Xignal Technologies AG, Munich, de-
veloping transceivers for SONET/SDH transmission systems at 10-Gb/s data
rate. Since 2004, he has been responsible for the high-speed continuous-time
delta-sigma ADC designs.