56F8367

Evaluation Module User Manual

56F8300
16-bit Digital Signal Controllers

MC56F8367EVMUM
Rev. 2
07/2005

freescale.com
 Document Revision History

Version History Description of Change

Rev 1.0 Initial Public Release

Rev 2.0 Updated look and feel

 TABLE OF CONTENTS

Preface Preface-vii

Chapter 1
Introduction
1.1 56F8367EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 56F8367EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 56F8367EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Chapter 2
Technical Summary
2.1 MC56F8367 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2 Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1 SRAM Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.2 SRAM Bank 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3 RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.4 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.5 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.5.1 EXTBOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.5.2 EMI_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.5.3 CLKMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.6 Debug LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.7 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.7.1 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.7.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.8 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.11 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.11.1 Peripheral Daughter Card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.11.2 Memory Daughter Card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.12 Motor Control PWM Signals and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

Table of Contents, Rev. 2

Freescale Semiconductor i
Preliminary
2.13 CAN Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.13.1 FlexCAN #1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.13.2 FlexCAN #2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.14 Software Feature Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.15 Peripheral Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.15.1 Address Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.15.2 Data Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.15.3 External Memory Control Signal Expansion Connector . . . . . . . . . . . . . . . . . . . . . 2-30
2.15.4 Encoder #0 / Quad Timer Channel A Expansion Connector. . . . . . . . . . . . . . . . . . 2-30
2.15.5 Encoder #1 / SPI #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.15.6 Timer Channel C Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.15.7 Timer Channel D Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2.15.8 A/D Port A Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2.15.9 A/D Port B Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2.15.10 Serial Communications Port #0 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-34
2.15.11 Serial Communications Port #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-35
2.15.12 Serial Peripheral Interface #0 Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . 2-35
2.15.13 FlexCAN #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2.15.14 FlexCAN #2 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2.15.15 PWM Port A Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
2.15.16 PWM Port B Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
2.16 Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

Appendix A
56F8367EVM Schematics

Appendix B
56F8367EVM Bill of Material

MC56F8367EVM User Manual, Rev. 2

ii Freescale Semiconductor
Preliminary
 LIST OF FIGURES

1-1 Block Diagram of the 56F8367EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1-2 MC56F8367 Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3 Connecting the 56F8367EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
2-1 Schematic Diagram of the External CS0 Memory Interface . . . . . . . . . . . . . . . . . . . 2-5
2-2 Schematic Diagram of the External CS1 / CS4 Memory Interface . . . . . . . . . . . . . . 2-6
2-3 Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-4 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-5 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2-6 Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-7 Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-8 Schematic Diagram of the Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2-9 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-10 PWM Group A Interface and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2-11 CAN #1 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2-12 CAN #2 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2-13 Software Feature Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2-14 Typical Analog Input RC Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

List of Figures, Rev. 2

Freescale Semiconductor iii
Preliminary
 MC56F8367EVM User Manual, Rev. 2
iv Freescale Semiconductor
Preliminary
 LIST OF TABLES

1-1 56F8367EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

2-1 SCI #0 Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-2 RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-3 EXTBOOT Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-4 EMI Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-5 EMI Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-6 LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-7 JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-8 Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . 2-12
2-9 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-10 Parallel JTAG Interface Voltage Jumper Selection . . . . . . . . . . . . . . . . . . . . . . 2-14
2-11 Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . 2-18
2-12 Memory Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2-13 CAN #1 Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2-14 CAN #2 Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2-15 CAN #2 Pass-Through Jumper Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2-16 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-28
2-17 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-29
2-18 External Memory Control Signal Connector Description . . . . . . . . . . . . . . . . . 2-30
2-19 Timer A Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2-20 SPI #1 Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2-21 Timer Channel C Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2-22 Timer Channel D Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2-23 A/D Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2-24 A/D Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2-25 SCI #0 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

List of Tables, Rev. 2

Freescale Semiconductor v
Preliminary
2-26 SCI #1 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2-27 SPI #0 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2-28 CAN #1 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2-29 CAN #2 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2-30 PWM Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
2-31 PWM Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

MC56F8367EVM User Manual, Rev. 2

vi Freescale Semiconductor
Preliminary
Preface
This reference manual describes in detail the hardware on the 56F8367 Evaluation Module.

Audience
This document is intended for application developers who are creating software for devices using
the Freescale 56F8367 part or a member of the 56F8300 family that is compatible with this part.
Examples would include the 56F8346 and the 56F8357 devices.

Organization
This manual is organized into two chapters and two appendices:
• Chapter 1, Introduction provides an overview of the EVM and its features.
• Chapter 2, Technical Summary describes in detail the 56F8367 hardware.
• Appendix A, "56F8367EVM Schematics"contains the schematics of the
MC56F8367EVM.
• Appendix B, "56F8367EVM Bill of Material" provides a list of the materials used on the
MC56F8367EVM board.

Suggested Reading
More documentation on the 56F8367 and the MC56F8367EVM kit may be found at URL:

www.freescale.com

Preface, Rev. 2
Freescale Semiconductor vii
Preliminary
Notation Conventions
This manual uses the following notational conventions:

Term or Value Symbol Examples Exceptions

Active High Signals No special symbol A0

(Logic One) attached to the signal CLKO
name

Active Low Signals Noted with an WE In schematic drawings,

(Logic Zero) overbar in text and in OE Active Low Signals may be
most figures noted by a backslash: /WE

Hexadecimal Values Begin with a “$” sym- $0FF0

bol $80

Decimal Values No special symbol 10

attached to the 34
number

Binary Values Begin with the letter “b” b1010

attached to the number b0011

Numbers Considered positive 5 Voltage is often shown as

unless specifically -10 positive: +3.3V
noted as a negative
value

Blue Text Linkable on-line ...refer to Chapter 7, License

Bold Reference sources, ...see: www.freescale.com/

paths, emphasis

MC56F8367EVM User Manual, Rev. 2

viii Freescale Semiconductor
Preliminary
Definitions, Acronyms, and Abbreviations
Definitions, acronyms and abbreviations for terms used in this document are defined below for
reference.
A/D Analog-to-Digital; a method of converting Analog signals to Digital values
ADC Analog-to-Digital Converter; a peripheral on the 56F8367 part
CAN Controller Area Network; serial communications peripheral and method
CiA CAN in Automation; an international CAN user’s group that coordinates
standards for CAN communications protocols
D/A Digital-to-Analog; a method of converting Digital values to an Analog form
56F8367 Controller with motor control peripherals
EOnCE Enhanced On-Chip Emulation; a debug bus and port was created to enable a
designer to create a low-cost hardware interface for a professional-quality
debug environment
EVM Evaluation Module; a hardware platform which allows a customer to evaluate
the silicon and develop his application
FlexCAN Flexable CAN Interface Module; a peripheral on the 56F8367 part
GPIO General Purpose Input and Output port on Freescale’s family of controllers;
does not share pin functionality with any other peripheral on the chip and can
only be set as an input, output or level-sensitive interrupt input
IC Integrated Circuit
JTAG Joint Test Action Group; a bus protocol/interface used for test and debug
LED Light Emitting Diode
LQFP Low-profile Quad Flat Package
MPIO Multi-Purpose Input and Output port on Freescale’s family of controllers;
shares package pins with other peripherals on the chip and can function as a
GPIO
OnCETM On-Chip Emulation, a debug bus and port created to allow a means for low-cost
hardware to provide a professional-quality debug environment
PCB Printed Circuit Board
PLL Phase Locked Loop
PWM Pulse Width Modulation
QuadDec Quadrature Decoder; a peripheral on the 56F8367 part

Preface, Rev. 2
Freescale Semiconductor ix
Preliminary
RAM Random Access Memory
R/C Resistor/Capacitor Network
ROM Read-Only Memory
SCI Serial Communications Interface; a peripheral on Freescale’s family of
controllers
SPI Serial Peripheral Interface; a peripheral on Freescale’s family of controllers
SRAM Static Random Access Memory
WS Wait State

References
The following sources were referenced to produce this manual:
[1] DSP56800E Reference Manual, DSP56800ERM, Freescale Semiconductor
[2] 56F8300 Peripheral User Manual, MC56F8300UM, Freescale Semiconductor
[3] 56F8367 Technical Data, MC56F8367, Freescale Semiconductor
[4] CiA Draft Recommendation DR-303-1, Cabling and Connector Pin Assignment,
Version 1.0, CAN in Automation
[5] CAN Specification 2.0B, BOSCH or CAN in Automation

MC56F8367EVM User Manual, Rev. 2

x Freescale Semiconductor
Preliminary
Chapter 1
Introduction
The 56F8367EVM is used to demonstrate the abilities of the 56F8367 controller and to provide a
hardware tool allowing the development of applications.

The 56F8367EVM is an evaluation module board that includes a 56F8367 part, peripheral
expansion connectors, a CAN interface, 512KB of external memory and a pair of daughter card
connectors. The daughter card connectors are for signal monitoring and user feature
expandability.

The 56F8367EVM is designed for the following purposes:

• Allowing new users to become familiar with the features of the 56800E architecture. The
tools and examples provided with the 56F8367EVM facilitate evaluation of the feature set
and the benefits of the family.
• Serving as a platform for real-time software development. The tool suite enables the user
to develop and simulate routines, download the software to on-chip or on-board RAM, run
it, and debug it using a debugger via the JTAG/Enhanced OnCE (EOnCE) port. The
breakpoint features of the EOnCE port enable the user to easily specify complex break
conditions and to execute user-developed software at full speed until the break conditions
are satisfied. The ability to examine and modify all user-accessible registers, memory and
peripherals through the EOnCE port greatly facilitates the task of the developer.
• Serving as a platform for hardware development. The hardware platform enables the user
to connect external hardware peripherals. The on-board peripherals can be disabled,
providing the user with the ability to reassign any and all of the processor's peripherals.
The EOnCE port's unobtrusive design means that all memory on the board and on the
processor is available to the user.

Introduction, Rev. 2
Freescale Semiconductor 1-1
Preliminary
1.1 56F8367EVM Architecture
The 56F8367EVM facilitates the evaluation of various features present in the 56F8367 part. The
56F8367EVM can be used to develop real-time software and hardware products. The
56F8367EVM provides the features necessary for a user to write and debug software,
demonstrate the functionality of that software and interface with the user's application-specific
device(s). The 56F8367EVM is flexible enough to allow a user to fully exploit the 56F8367's
features to optimize the performance of his product, as shown in Figure 1-1.

CAN #1 Bus
56F8367 DaisyChain

FlexCAN #1 CAN #1 Interface CAN #1 Bus

Program Memory Address, Header
128K x 16-bit Data &
SRAM Control
RS-232 DSub
SCI #0 Interface 9-Pin
Data Memory
128K x 16-bit
SRAM

Memory
Expansion SPI #0
Connector SCI #1
Memory Timer C
Daughter Card Peripheral Peripheral
Connector Timer D Expansion Daughter Card
PWMA Connectors Connector
ADCA
Reset Logic RESET QuadDec #0
PWMB
Mode/IRQ
MODE/IRQ ADCB
Logic
QuadDec #1
FlexCAN #2
JTAG
Connector JTAG/EOnCE
CAN #2 Bus
CAN #2 Interface Header
Parallel Debug LEDs
DSub CAN #2 Bus
JTAG
25-Pin DaisyChain
Interface
PWM LEDs

8.00MHz XTAL/ +3.3V & GND Power Supply

Crystal EXTAL +3.3V A & +3.3V, +3.3V A,
AGND +5V & +3.3VREF
+3.3VREF

Figure 1-1. Block Diagram of the 56F8367EVM

MC56F8367EVM User Manual, Rev. 2

1-2 Freescale Semiconductor
Preliminary
 56F8367EVM Configuration Jumpers

1.2 56F8367EVM Configuration Jumpers

Ninteen jumper groups, (JG1-JG19), shown in Figure 1-2, are used to configure various features
on the 56F8367EVM board. Table 1-1 describes the default jumper group settings.

4 3
JG6 JG4 JG5 JG7
JG14
JG12 2 1
JG13

1 3
J16 J18 J19 J14
J20 2 4
J11 J13 J15 J17 J4 J5
J21

JG8
JG13

JG15 J7 J8
J6 J12 J14
J22

PC0 JG5 J24 JG7

PC1 J1 JG6 JG4 JG8 JG17
PC2
PC3
J23
1 3
1 3
PD6
PD7
U1
J2

S/N
PWMA0
PWMA1
PWMA2 U2 U3
PWMA3
PWMA4
PWMA5
JG2 JG1
JG17
JG16
JG15

Y1 JTAG
JG9 JG12 JG18
JG16
J3
JG10 J9 J10

3 1
U8 U9 JG3
U4 MC56F8357EVM JG19
JG11 P2 S3 S2 S1 P1 P3

LED3

JG9 RESET IRQA IRQB

4 2

JG2 JG1 3
JG10 JG3
JG18 JG19
JG11 1 3 1

Figure 1-2. MC56F8367 Default Jumper Options

Introduction, Rev. 2
Freescale Semiconductor 1-3
Preliminary
 Table 1-1. 56F8367EVM Default Jumper Options
Jumper Jumpers
Comment
Group Connections

JG1 Use on-board EXTAL crystal input for oscillator 1–2

JG2 Use on-board XTAL crystal input for oscillator 1–2

JG3 Enable on-board Parallel JTAG Host/Target Interface NC

JG4 Enable Internal Boot Mode 1–2

JG5 Enable A0 - A23 for external memory accesses NC

JG6 Enable Crystal Mode 1–2

JG7 Enable SRAM Memory Bank 0 (use CS0) 1–2

JG8 Enable SRAM Memory Bank 1 (use CS1 & CS4) 1–2 & 3–4

JG9 Pass RXD0 & TXD0 to RS-232 level converter 1–2 & 3–4

JG10 Enable RS-232 output NC

JG11 Pass RS-232 RST to CTS 1–2

JG12 Pass Temperature Diode to ANA7 1–2

JG13 CAN #1 termination selected 1–2

JG14 Pass CAN2_TX & CAN2_RX to CAN tranceiver 1–2 & 3–4

JG15 High selected on User Jumper #0 1–2

JG16 High selected on User Jumper #1 1–2

JG17 CAN2 termination selected 1–2

JG18 Analog Ground to Digital Ground not reconnected NC

JG19 Use +3.3V for Printer Interface to on-board Parallel JTAG Host/Target 1-2

MC56F8367EVM User Manual, Rev. 2

1-4 Freescale Semiconductor
Preliminary
 56F8367EVM Connections

1.3 56F8367EVM Connections

An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V DC/AC power supply to the 56F8367EVM board.

Parallel extension
cable

MC56F8367EVM
PC-compatible
computer
P1
Connect cable P3
to parallel / printer port
External with 2.1mm,
+12V receptacle
power connector

Figure 1-3. Connecting the 56F8367EVM Cables

Perform the following steps to connect the 56F8367EVM cables:

1. Connect the parallel extension cable to the parallel port of the host computer.
2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3, on the
56F8367EVM board. This provides the connection which allows the host computer to
control the board.
3. Make sure that the external +12V DC, 1.2A power supply is not plugged into a +120V AC
power source.
4. Connect the 2.1mm output power plug from the external power supply into P3, shown in
Figure 1-3, on the 56F8367EVM board.
5. Apply power to the external power supply. The green Power-On LED, LED13, will
illuminate when power is correctly applied.

Introduction, Rev. 2
Freescale Semiconductor 1-5
Preliminary
 MC56F8367EVM User Manual, Rev. 2
1-6 Freescale Semiconductor
Preliminary
Chapter 2
Technical Summary
The 56F8367EVM is designed as a versatile development card using the 56F8367 processor,
allowing the creation of real-time software and hardware products to support a new generation of
applications in servo and motor control, digital and wireless messaging, digital answering
machines, feature phones, modems, and digital cameras. The power of the 16-bit 56F8367
processor, combined with the on-board 128K x 16-bit external Program/Data Static RAM
(SRAM), 128K x 16-bit external Data/Program SRAM, RS-232 interface, CAN interface,
daughter card interface, peripheral expansion connectors and parallel JTAG interface, makes the
56F8367EVM ideal for developing and implementing many motor controlling algorithms, as
well as for learning the architecture and instruction set of the 56F8367 processor.

The main features of the 56F8367EVM, with board and schematic reference designators, include:

• MC56F8367VPY60, a 16-bit +3.3V/+2.5V controller operating at 60MHz [U1]

• External Fast Static RAM (FSRAM) memory, configured as:
— 128K x 16-bit of memory [U2] with 0 wait state at 60MHz via CS0
— 128K x 16-bit of memory [U3] with 0 wait state at 60MHz via CS1/CS4
• 8.00MHz crystal oscillator, for base processor frequency generation [Y1]
• Optional external oscillator frequency input connectors [JG1 and JG2]
• Joint Test Action Group (JTAG) port interface connector, for an external debug Host
Target Interface [J3]
• On-board parallel JTAG host target interface, with a connector for a PC printer port cable
[P1], including a disable jumper [JG3] and a printer port voltage selection jumper [JG19]
• RS-232 interface, for easy connection to a host processor [U4 and P2], including a disable
jumper [JG10]
• RTS and CTS RS-232 control signal access [JG11]
• CAN interface, for high speed, 1.0Mbps, FlexCAN communications [U10 and J20]
• CAN bypass and bus termination [J21 and JG13]

Technical Summary, Rev. 2

Freescale Semiconductor 2-1
Preliminary
 • CAN #2 interface, for high speed, 1.0Mbps, FlexCAN communications [U11 and J22]
• CAN #2 bypass and bus termination [J23 and JG17]
• CAN #2 interface signal isolation [JG14]
• Peripheral Daughter Card connector, to allow the user to connect his own SCI, SPI or
GPIO-compatible peripheral to the controller [J1]
• Memory Daughter Card connector, to allow the user to connect his own memory or
memory device to the device [J2]
• SCI #0 expansion connector, to allow the user to connect his own SCI #0 /
MPIO-compatible peripheral [J13]
• SCI #1 expansion connector, to allow the user to connect his own SCI #1 /
MPIO-compatible peripheral [J14]
• SPI #0 expansion connector, to allow the user to connect his own SPI #0 /
MPIO-compatible peripheral [J11]
• SPI #1 expansion connector, to allow the user to connect his own SPI #1 /
MPIO-compatible peripheral [J12]
• PWMA expansion connector, to allow the user to connect his own PWMA-compatible
peripheral [J7]
• PWMB expansion connector, to allow the user to connect his own PWMB-compatible
peripheral [J8]
• CAN #1 expansion connector, to allow the user to connect his own CAN physical layer
peripheral [J18]
• CAN #2 expansion connector, to allow the user to connect his own CAN physical layer
peripheral [J19]
• Timer A expansion connector, to allow the user to connect his own Timer A / Encoder
#0-compatible peripheral [J15]
• Timer C expansion connector, to allow the user to connect his own Timer C-compatible
peripheral [J16]
• Timer D expansion connector, to allow the user to connect his own Timer D-compatible
peripheral [J17]
• ADC A expansion connector, to allow the user to attach his own A/D Port A-compatible
peripheral [J9]
• ADC B expansion connector, to allow the user to attach his own A/D Port B-compatible
peripheral [J10]

MC56F8367EVM User Manual, Rev. 2

2-2 Freescale Semiconductor
Preliminary
 • Address bus expansion connector, to allow the user to monitor the external address bus
[J4]
• Data bus expansion connector, to allow the user to monitor the external data bus [J5]
• External memory bus control signal connector, to allow the user to monitor the external
memory bus [J6]
• On-board power regulation provided from an external +12V DC-supplied power input
[P3]
• Light Emitting Diode (LED) power indicator [LED13]
• Six on-board real-time user debugging LEDs [LED1 - 6]
• Six on-board Port A PWM monitoring LEDs [LED7 - 12]
• Internal/external (EXTBOOT) boot mode selector [JG4]
• Address range (EMI_MODE) boot mode selector [JG5]
• Clock mode (CLKMODE) boot selector [JG6]
• Temperature sense diode to ANA7 selector [JG12]
• Manual reset push button [S1]
• Manual interrupt push button for IRQA [S2]
• Manual interrupt push button for IRQB [S3]
• General-purpose jumper on GPIO PE4 [JG15]
• General-purpose jumper on GPIO PE7 [JG16]

Technical Summary, Rev. 2

Freescale Semiconductor 2-3
Preliminary
2.1 MC56F8367
The 56F8367EVM uses a Freescale MC56F8367VPY60 part, designated as U1 on the board and
in the schematics. This part will operate at a maximum external bus speed of 60MHz. A full
description of the 56F8367, including functionality and user information, is provided in these
documents:

• 56F8367 Technical Data Sheet, (MC56F8367): Electrical and timing specifications, pin
descriptions, device-specific peripheral information and package descriptions (this
document)
• 56F8300 Peripheral User Manual, (MC56F8300UM): Detailed description of peripherals
of the 56F8300 family of devices
• DSP56800E Reference Manual, (DSP56800ERM): Detailed description of the 56800E
family architecture, 16-bit core processor, and the instruction set
Refer to these documents for detailed information about chip functionality and operation. They
can be found on this URL:

www.freescale.com

2.2 Program and Data Memory

The 56F8367EVM contains two 128K x 16-bit Fast Static RAM banks. SRAM bank 0 is
controlled by CS0 and SRAM bank 1 is controlled by CS1 and CS4. This provides a total of
256K x 16 bits of external memory.

MC56F8367EVM User Manual, Rev. 2

2-4 Freescale Semiconductor
Preliminary
 Program and Data Memory

2.2.1 SRAM Bank 0

SRAM bank 0, which is controlled by CS0, uses a 128K x 16-bit Fast Static RAM (GSI
GS72116, labeled U2) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-1. CS0 can be configured to use this memory bank as 16 bits of Program memory, Data
memory, or both. Additionally, CS0 can be configured to assign this memory’s size and starting
address to any modulo address space.

This memory bank will operate with zero wait state access while the 56F8367 is running at
60MHz and can be disabled by removing the jumper at JG7.

MC56F8367 GS72116

A0 - A16 A0 - A16
D0 - D15 DQ0 - DQ15

RD OE

WR WE

PS / CS0
+3.3V

Jumper Pin 1-2: JG7

Enable SRAM
1
2

Jumper Removed:
Disable SRAM CE

Figure 2-1. Schematic Diagram of the External CS0 Memory Interface

Technical Summary, Rev. 2

Freescale Semiconductor 2-5
Preliminary
2.2.2 SRAM Bank 1
SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K x 16-bit Fast Static RAM (GSI
GS72116, labeled U3) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-2. Using CS1 and CS4, this memory bank can be configured as byte (8-bit) or word
(16-bit) accessable Program memory, Data memory, or both. Additionally, CS1 and CS4 can be
configured to assign this memory’s size and starting address to any modulo address space.

This memory bank will operate with zero wait state access while the 56F8367 is running at
60MHz and can be disabled by removing the jumpers at JG8.

MC56F8367 GS72116

A0 - A16 A0 - A16
D0 - D15 DQ0 - DQ15

RD OE

WR WE
JG8

DS / CS1 1 2 LB
PD2 / CS4 3 4 HB
CE
Jumper Pin 1-2:
Enable SRAM Low Byte
Jumper Pin 3-4:
Enable SRAM High Byte

Figure 2-2. Schematic Diagram of the External CS1 / CS4 Memory Interface

MC56F8367EVM User Manual, Rev. 2

2-6 Freescale Semiconductor
Preliminary
 RS-232 Serial Communications

2.3 RS-232 Serial Communications

The 56F8367EVM provides an RS-232 interface by the use of an RS-232 level converter, Maxim
MAX3245EEAI, designated as U4. Refer to the RS-232 schematic diagram in Figure 2-3. The
RS-232 level converter transitions the SCI port’s +3.3V signal levels to RS-232-compatible
signal levels and connects to the host’s serial port via connector P2. RTS/CTS flow control is
provided on JG11 as a jumper, but could be implemented using uncommitted GPIO signals. The
SCI port #0 signals can be isolated from the RS-232 level converter by removing the jumpers in
JG9; see Table 2-1. The pin-out of connector P2 is listed in Table 2-2. The RS-232 level
converter/transceiver can be disabled by placing a jumper at JG10.

RS-232
MC56F8367 Level Converter
Interface P2
1
6
JG9
TXD 2
TXD0 1 2 T1 in T1 out
7
RXD 3
RXD0 3 4 R1 out R1 in 8
JG11 4
RTS T2 in R2 in
1 9
x
CTS 5
2 R2 out T2 out
+3.3V

FORCEOFF

Jumper Removed: JG10

Enable RS-232 1
Jumper Pin 1-2: 2
Disable RS-232

Figure 2-3. Schematic Diagram of the RS-232 Interface

Table 2-1. SCI #0 Jumper Options

JG9

Pin # Signal Pin # Signal

1 TXD0 2 RS-232 TXD

3 RXD0 4 RS-232 RXD

Technical Summary, Rev. 2

Freescale Semiconductor 2-7
Preliminary
 Table 2-2. RS-232 Serial Connector Description

P2

Pin # Signal Pin # Signal

1 Jumper to 6 & 4 6 Jumper to 1 & 4

2 TXD 7 CTS

3 RXD 8 RTS

4 Jumper to 1 & 6 9 NC

5 GND

2.4 Clock Source

The 56F8367EVM uses an 8.00MHz crystal, Y1, connected to its external crystal inputs, EXTAL
and XTAL. To achieve its maximum internal operating frequency, the 56F8367 uses its internal
PLL to multiply the input frequency. An external oscillator source can be connected to the
processor by using the oscillator bypass connectors, JG1 and JG2; see Figure 2-4. If the input
frequency is above 8MHz, then the EXTAL input should be jumpered to ground by adding a
jumper between JG1 pins 2 and 3. The input frequency would then be injected on JG2’s pin 2. If
the input frequency is below 4MHz, then the input frequency can be injected on JG1’s pin 2.

External
Oscillator
Headers MC56F8367
JG1
1
2 EXTAL
3

8.00MHz

JG2

1
2 XTAL

Figure 2-4. Schematic Diagram of the Clock Interface

MC56F8367EVM User Manual, Rev. 2

2-8 Freescale Semiconductor
Preliminary
 Operating Mode

2.5 Operating Mode

The 56F8367EVM provides three boot mode selection jumpers, EXTBOOT, EMI_MODE and
CLKMODE, to provide boot-up mode options.

2.5.1 EXTBOOT
The 56F8367EVM provides an external/internal boot mode jumper, JG4. This jumper is used to
select the internal or external memory operation of the processor as it exits reset. Refer to the
56F8300 Peripheral User Manual and the 56F8367 Technical Data Sheet for a complete
description of the chip’s operating modes. Table 2-3 shows the two external boot operation
modes available on the 56F8367.

Table 2-3. EXTBOOT Operating Mode Selection

Operating Mode JG4 Comment

0 1-2 Bootstrap from internal memory (GND)

3 No Jumper Bootstrap from external memory (+3.3V)

2.5.2 EMI_MODE
The 56F8367EVM provides an EMI boot mode jumper, JG5. This jumper is used to select the
external memory addressing range operating mode of the processor as it exits reset. The user can
select between a 64K address space or an 8M address space. Refer to the 56F8300 Peripheral
User Manual and the 56F8367 Technical Data Sheet for a complete description of the chip’s
operating modes. Table 2-4 shows the two EMI operation modes available on the 56F8367.

Table 2-4. EMI Operating Mode Selection

Operating Mode JG5 Comment

V1 1-2 A0 - A15 (64K) available for external memory bus (GND)

V2 No Jumper A0 - A23 (8M) available for external memory bus (+3.3V)

Technical Summary, Rev. 2

Freescale Semiconductor 2-9
Preliminary
2.5.3 CLKMODE
The 56F8367EVM provides a clock boot mode jumper, JG6. This jumper is used to select the
type of clock source being provided to the processor as it exits reset. The user can select between
the use of a crystal or an oscillator as the clock source for the processor. Refer to the 56F8300
Peripheral User Manual and the 56F8367 Technical Data Sheet for a complete description of
the chip’s operating modes. Table 2-5 shows the two CLKMODE operation modes available on
the 56F8367.

Table 2-5. EMI Operating Mode Selection

Operating Mode JG6 Comment

Crystal 1-2 Enables the external clock drive logic so an external

crystal can be used as the input clock source. (GND)

Oscillator No Jumper Disables the external clock drive logic. Use oscillator
input on XTAL and Ground on EXTAL. (3.3V)

2.6 Debug LEDs

Six on-board Light Emitting Diodes, (LEDs), are provided to allow real-time debugging for user
programs. These LEDs will allow the programmer to monitor program execution without having
to stop the program during debugging; refer to Figure 2-5. Table 2-6 describes the control of
each LED.

Table 2-6. LED Control

Controlled by

User LED Color Signal

LED1 RED Port C Bit 0 (PC0)

LED2 YELLOW Port C Bit 1 (PC1)

LED3 GREEN Port C Bit 2 (PC2)

LED4 RED Port C Bit 3 (PC3)

LED5 YELLOW Port D Bit 6 (PD6)

LED6 GREEN Port D Bit 7 (PD7)

MC56F8367EVM User Manual, Rev. 2

2-10 Freescale Semiconductor
Preliminary
 Debug Support

Setting PC0, PC1, PC2, PC3, PD6, or PD7 to a Logic One value will turn on the associated LED.

MC56F8367 INVERTING BUFFER

+3.3V
RED LED
PC0

YELLOW LED

PC1

GREEN LED
PC2

RED LED
PC3

YELLOW LED
PD6

GREEN LED
PD7

Figure 2-5. Schematic Diagram of the Debug LED Interface

2.7 Debug Support

The 56F8367EVM provides an on-board parallel JTAG host target interface and a JTAG
interface connector for external target interface support. Two interface connectors are provided to
support each of these debugging approaches. These two connectors are designated the JTAG
connector and the host parallel interface connector.

Technical Summary, Rev. 2

Freescale Semiconductor 2-11
Preliminary
2.7.1 JTAG Connector
The JTAG connector on the 56F8367EVM allows the connection of an external host target
interface for downloading programs and working with the 56F8367’s registers. This connector is
used to communicate with an external host target interface, which passes information and data
back and forth with a host processor running a debugger program. Table 2-7 shows the pin-out
for this connector.

Table 2-7. JTAG Connector Description

J3

Pin # Signal Pin # Signal

1 TDI 2 GND

3 TDO 4 GND

5 TCK 6 GND

7 NC 8 KEY

9 RESET 10 TMS

11 +3.3V 12 NC

13 DE 14 TRST

When this connector is used with an external host target interface, the parallel JTAG interface
should be disabled by placing a jumper in jumper block JG3. Reference Table 2-8 for this
jumper’s selection options.

Table 2-8. Parallel JTAG Interface Disable Jumper Selection

JG3 Comment

No jumpers Enables On-board Parallel JTAG Interface

1-2 Disables on-board Parallel JTAG Interface

MC56F8367EVM User Manual, Rev. 2

2-12 Freescale Semiconductor
Preliminary
 Debug Support

2.7.2 Parallel JTAG Interface Connector

The Parallel JTAG Interface Connector, P1, allows the 56F8367 to communicate with a parallel
printer port on a Windows PC; reference Figure 2-6. Using this connector, the user can
download programs and work with the 56F8367’s registers. Table 2-9 shows the pin-out for this
connector. When using the parallel JTAG interface, the jumper at JG3 should be removed, as
shown in Table 2-8. The printer port interface voltage of +3.3V or +5.0V can be selected by a
jumper on JG19, as shown in Table 2-10.

DB-25 Connector Parallel JTAG Interface MC56F8367

TDI IN OUT TDI

TDO OUT IN TDO
P_TRST IN OUT TRST
TMS IN OUT TMS
TCK IN OUT TCK
P_RESET IN OUT RESET
P_DE IN OUT DE
+3.3V
EN Vcc
JG3
Jumper Removed:
1 JG19
Enable JTAG I/F
2 1 +3.3V
Jumper Pin 1-2: 2
Disable JTAG I/F 3 +5.0V

Figure 2-6. Block Diagram of the Parallel JTAG Interface

Technical Summary, Rev. 2

Freescale Semiconductor 2-13
Preliminary
 Table 2-9. Parallel JTAG Interface Connector Description

P1

Pin # Signal Pin # Signal

1 NC 14 NC

2 PORT_RESET 15 PORT_IDENT

3 PORT_TMS 16 NC

4 PORT_TCK 17 NC

5 PORT_TDI 18 GND

6 PORT_TRST 19 GND

7 PORT_DE 20 GND

8 PORT_IDENT 21 GND

9 PORT_VCC 22 GND

10 NC 23 GND

11 PORT_TDO 24 GND

12 NC 25 GND

13 PORT_CONNECT

Table 2-10. Parallel JTAG Interface Voltage Jumper Selection

JG19 Comment

1-2 Interface with the PC’s printer port using +3.3V signals

2-3 Interface with the PC’s printer port using +5.0V signals

MC56F8367EVM User Manual, Rev. 2

2-14 Freescale Semiconductor
Preliminary
 External Interrupts

2.8 External Interrupts

Two on-board push button switches are provided for external interrupt generation, as shown in
Figure 2-7. S2 allows the user to generate a hardware interrupt for signal line IRQA. S3 allows
the user to generate a hardware interrupt for signal line IRQB. These two switches allow the user
to generate interrupts for his user-specific programs.

+3.3V

MC56F8367
10K
S2
IRQA
0.1µF

+3.3V

10K
S3
IRQB
0.1µF

Figure 2-7. Schematic Diagram of the User Interrupt Interface

Technical Summary, Rev. 2

Freescale Semiconductor 2-15
Preliminary
2.9 Reset
Logic is provided on the 56F8367 to generate an internal power-on reset. Additional reset logic is
provided to support the reset signals from the JTAG connector, the parallel JTAG interface and
the user reset push button, S1; refer to Figure 2-8.

JTAG_RESET
RESET

RESET
PUSHBUTTON
MANUAL RESET
S1

TRST
JTAG_TAP_RESET

Figure 2-8. Schematic Diagram of the Reset Interface

MC56F8367EVM User Manual, Rev. 2

2-16 Freescale Semiconductor
Preliminary
 Power Supply

2.10 Power Supply

The main power input to the 56F8367EVM, +12V DC at 1.2A, is through a 2.1mm coax power
jack. This input power is rectified to provide a DC supply input. This allows a user the option to
use a +12V AC power supply. A 1.2 Amp power supply is provided with the 56F8367EVM;
however, less than 500mA is required by the EVM. The remaining current is available for custom
control applications when connected to the daughter card connectors. The 56F8367EVM
provides +5.0V DC regulation for the CAN interface and additional regulators. The
56F8367EVM provides +3.3V DC voltage regulation for the processor, memory, D/A, ADC,
parallel JTAG interface and supporting logic; refer to Figure 2-9. Additional voltage regulation
logic provides a low-noise +3.3V DC voltage reference to the processor’s A/D VREFH. A jumper,
JG18, and resistor, R66, are provided to allow the analog and digital grounds to be isolated on the
56F8367EVM board. This allows the analog ground reference point to be provided on a custom
board attached to the 56F8367EVM daughter card connectors. By removing R66, the AGND
reference is disconnected from the 56F8367EVM’s digital ground. By placing a jumper on JG18,
the AGND is reconnected to the 56F8367EVM’s digital ground. Power applied to the
56F8367EVM is indicated with a power-on LED, referenced as LED13. Optionally, the user can
provide the +2.5 DC voltage needed by the processor’s core on connector J24 and disable the
on-chip core voltage regulator by moving the resistor at R72 to R71. Additonally, four zero ohm
resistors or shorting wires must be added at R67, R68, R69, and R70 to allow the external +2.5V
DC to pass to the 56F8367.

P3 +5.0V DC
+12V DC/AC +5.0V Power
Bridge CAN
Input Regulator Condition
Rectifier

+3.3V +3.3V DC 56F8367

Regulator VDD_IO & PLL

56F8367EVM
Parts

J24
R67 - R70 56F8367
+2.5V DC 1
Ext In VDD Core
2

Power On
+3.3V +3.3VA DC 56F8367
Regulator ADC

U15
+3.3V +3.3VA DC 56F8367
Regulator VREFH

Figure 2-9. Schematic Diagram of the Power Supply

Technical Summary, Rev. 2

Freescale Semiconductor 2-17
Preliminary
2.11 Daughter Card Connectors
The EVM board contains two daughter card connectors. One connector, J1, contains the
processor’s peripheral port signals. The second connector, J2, contains the processor’s external
memory bus signals.

2.11.1 Peripheral Daughter Card Connector

The processor’s peripheral port signals are connected to the peripheral daughter card connector,
J1. The peripheral daughter card connector is used to connect a daughter card or a user-specific
daughter card to the processor’s peripheral port signals. The peripheral port daughter card
connector is a 100-pin high-density connector with signals for the IRQs, reset, SPI, SCI, PWM,
ADC and Quad Timer ports. Table 2-11 shows the peripheral daughter card connector’s
signal-to-pin assignments.

Table 2-11. Peripheral Daughter Card Connector Description

J1

Pin # Signal Pin # Signal

1 +12V 2 +12V

3 GND 4 GND

5 +5.0V 6 +5.0V

7 GND 8 GND

9 +3.3V 10 +3.3V

11 GND 12 GND

13 PHASEA0 / TA0 / PC4 14 PHASEB0 / TA1 / PC5

15 INDEX0 / TA2 / PC6 16 HOME0 / TA3 / PC7

17 GND 18 GND

19 PHASEA1 / PC0 / TB0 / SCLK1 20 PHASEB1 / PC1 / TB1 / MOSI1

21 INDEX1 / PC2 / TB2 / MISO1 22 HOME1 / PC3 / TB3 / SS1

23 TXD0 / PE0 24 TXD1 / PD6

25 TXD0 / PE0 26 TXD1 / PD6

27 RXD0 / PE1 28 RXD1 / PD7

MC56F8367EVM User Manual, Rev. 2

2-18 Freescale Semiconductor
Preliminary
 Daughter Card Connectors

Table 2-11. Peripheral Daughter Card Connector Description (Continued)

J1

Pin # Signal Pin # Signal

29 IRQA 30 IRQB

31 RXD0 / PE1 32 RXD1 / PD7

33 PWMB0 34 PWMB1

35 PWMB2 36 PWMB3

37 PWMB4 38 PWMB5

39 GND 40 GND

41 ISB0 / PD10 42 ISB1 / PD11

43 ISB2 / PD12 44 GND

45 FAULTB1 46 FAULTB0

47 FAULTB3 48 FAULTB2

49 GND 50 GND

51 PWMA0 52 PWMA1

53 PWMA2 54 PWMA3

55 PWMA4 56 PWMA5

57 GND 58 GND

59 FAULTA0 60 FAULTA1

61 FAULTA2 62 MISO0 / PE6

63 ISA0 / PC8 64 ISA1 / PC9

65 ISA2 / PC10 66 RSTO

67 MOSI0 / PE5 68 SS0 / PE7

69 TD0 / PE10 70 TD1 / PE11

71 SCLK0 / PE7 72 TC0 / PE8

73 CAN_TX 74 CAN_RX

75 MOSI0 / PE5 76 MISO0 / PE6

77 SCLK0 / PE4 78 SS0 / PE7

79 GND 80 GND

Technical Summary, Rev. 2

Freescale Semiconductor 2-19
Preliminary
 Table 2-11. Peripheral Daughter Card Connector Description (Continued)

J1

Pin # Signal Pin # Signal

81 +VREFH 82 +VREFH

83 GNDA 84 GNDA

85 AN0 86 AN1

87 AN2 88 AN3

89 AN4 90 AN5

91 AN6 92 AN7

93 AN8 94 AN9

95 AN10 96 AN11

97 AN12 98 AN13

99 AN14 100 AN15

2.11.2 Memory Daughter Card Connector

The processor’s external memory bus signals are connected to the memory daughter card
connector, J2. Table 2-12 shows the port signal-to-pin assignments.

Table 2-12. Memory Daughter Card Connector Description

J2

Pin # Signal Pin # Signal

1 A4 / PA12 2 A5 / PA13

3 A3 / PA11 4 A6 / PE2

5 A2 / PA10 6 A7 / PE3

7 A1 / PA9 8 RD

9 GND 10 GND

11 A0 / PA8 12 DS / CS1

13 PS / CS0 14 PD0 / CS2 / CAN2_TX

MC56F8367EVM User Manual, Rev. 2

2-20 Freescale Semiconductor
Preliminary
 Daughter Card Connectors

Table 2-12. Memory Daughter Card Connector Description (Continued)

J2

Pin # Signal Pin # Signal

15 D0 / PF9 16 D15 / PF8

17 D1 / PF10 18 D14 / PF7

19 GND 20 GND

21 GND 22 GND

23 D2 / PF11 24 D13 / PF6

25 D3 / PF12 26 D12 / PF5

27 D4 / PF13 28 D11 / PF4

29 D5 / PF14 30 D10 / PF3

31 GND 32 GND

33 GND 34 GND

35 D6 / PF15 36 D9 / PF2

37 D7 / PF0 38 D8 / PF1

39 WR 40 PD1 / CS3 / CAN2_RX

41 A15 / PA7 42 A8 / PA0

43 GND 44 GND

45 A14 / PA6 46 A9 / PA1

47 A13 / PA5 48 A10 / PA2

49 A12 / PA4 50 A11 / PA3

51 PB0 / A16 52 GND

53 GND 54 GND

55 +3.3V 56 +3.3V

57 GND 58 GND

59 +5.0V 60 +5.0V

Technical Summary, Rev. 2

Freescale Semiconductor 2-21
Preliminary
2.12 Motor Control PWM Signals and LEDs
The 56F8367 has two independent groups of dedicated PWM units. Each unit contains six PWM,
three phase current sense inputs and four fault input lines. PWM group A’s PWM lines are
connected to a set of six PWM LEDs via inverting buffers. The buffers are used to isolate and
drive the Processor’s PWM group A’s outputs to the PWM LEDs. The PWM LEDs indicate the
status of PWM group A signals; refer to Figure 2-10. PWM Group A and B signals are routed
out to headers, J7 and J8 respectively, and to the peripheral daughter card connector for easy use
by the end user.

56F8367

PWMA0 PWMA0
PWMA1 PWMA1
PWMA2 PWMA2
PWMA3 PWMA3
PWMA4 PWMA4
PWMA5 PWMA5

+3.3V

Yellow LED LED7

Phase A Top
Green LED LED8
Phase A Bottom
LED
Yellow LED LED9 Phase B Top
Buffer
Green LED LED10
Phase B Bottom
Yellow LED LED11 Phase C Top

Green LED LED12 Phase C Bottom

Figure 2-10. PWM Group A Interface and LEDs

MC56F8367EVM User Manual, Rev. 2

2-22 Freescale Semiconductor
Preliminary
 CAN Interfaces

2.13 CAN Interfaces

The 56F8367EVM board contains two FlexCAN interfaces. The primary CAN interface uses the
CAN1_RX and CAN1_TX pins on the 56F8367. The secondary CAN interface uses the
CAN2_RX and CAN2_TX pins on the 56F8367.

2.13.1 FlexCAN #1 Interface

The 56F8367EVM board contains a CAN physical-layer interface chip that is attached to the
FlexCAN port’s CAN1_RX and CAN1_TX pins on the 56F8367. The EVM board uses a Phillips
high-speed, 1.0Mbps, physical layer interface chip, PCA82C250. Due to the +5.0V operating
voltage of the CAN interface chip, a pull-up to +5.0V is required to level shift the transmit data
output line from the 56F8367. The CANH and CANL signals pass through inductors before
attaching to the CAN bus connectors. A primary, J20, and daisy-chain, J21, CAN connector are
provided to allow easy daisy-chaining of CAN devices. CAN bus termination of 120 ohms can be
provided by adding a jumper to JG13. Refer to Table 2-14 for the CAN connector signals and
Figure 2-12 for a connection diagram.

+5.0V

MC56F8367
1K CAN Transceiver
J20
CAN1_TX TXD
CANH 4 CAN #1 Bus
5
CANL 3
Connector

CAN1_RX RXD
J21
PCA82C250 4 Daisy-Chain CAN #1
5 Connector
3

JG13
1 CAN Bus #1
2 Terminator
120

Figure 2-11. CAN #1 Interface

Technical Summary, Rev. 2

Freescale Semiconductor 2-23
Preliminary
 Table 2-13. CAN #1 Header Description

J20 and J21

Pin # Signal Pin # Signal

1 NC 2 NC

3 CANL 4 CANH

5 GND 6 NC

7 NC 8 NC

9 NC 10 NC

2.13.2 FlexCAN #2 Interface

The 56F8367EVM board contains a second FlexCAN port, the CAN2_RX and CAN2_TX pins
on the 56F8367. These signals pass through an isolation jumper, JG14, before going to the CAN
physical layer interface. The EVM board uses a Phillips high-speed, 1.0Mbps, physical layer
interface chip, PCA82C250. Due to the +5.0V operating voltage of the CAN interface chip, a pull
up to +5.0V is required to level shift the transmit data output line from the 56F8367. The CAN2H
and CAN2L signals pass through inductors before attaching to the CAN bus connectors. A
primary, J22, and daisy-chain, J23, CAN connector are provided to allow easy daisy-chaining of
CAN devices. CAN bus termination of 120 ohms can be provided by adding a jumper to JG17.
Refer to Figure 2-12 for a connection diagram and to Table 2-14 and Table 2-15 for the CAN
connector signals.

MC56F8367EVM User Manual, Rev. 2

2-24 Freescale Semiconductor
Preliminary
 CAN Interfaces

+5.0V

MC56F8367
1K
CAN Transceiver
JG14
J22
PD0 / CAN2_TX 1 2 TXD
CANH 4 CAN #2 Bus
5 Connector
CANL 3
PD1 / CAN2_RX 3 4 RXD
J23
PCA82C250 4 Daisy-Chain
5 CAN #2
3 Connector

JG17
1 CAN #2 Bus
2 Terminator
120

Figure 2-12. CAN #2 Interface

Table 2-14. CAN #2 Header Description

J22 and J23

Pin # Signal Pin # Signal

1 NC 2 NC

3 CAN2L 4 CAN2H

5 GND 6 NC

7 NC 8 NC

9 NC 10 NC

Table 2-15. CAN #2 Pass-Through Jumper Description

JG14

Pin # Signal Pin # Signal

1 PD0 2 CAN2_TX

3 PD1 4 CAN2_RX

Technical Summary, Rev. 2

Freescale Semiconductor 2-25
Preliminary
2.14 Software Feature Jumpers
The 56F8367EVM board contains two software feature jumpers that allow the user to select
user-defined software features. Two GPIO port pins, PE4 and PE7, are pulled high or low with
10K ohm resistors on JG15 and JG16. Attaching a jumper between pins 1 and 2 will place a high
or 1 on the port pin. Attaching a jumper between pins 2 and 3 will place a low or 0 on the port
pin; see Figure 2-13.

MC56F8367
JG15 +3.3V
10K
1 User Jumper
SCLK0 / PE4 2 #0
3
10K

JG16 +3.3V
10K
1 User Jumper
SS0 / PE7 2 #1
3
10K

Figure 2-13. Software Feature Jumpers

MC56F8367EVM User Manual, Rev. 2

2-26 Freescale Semiconductor
Preliminary
 Peripheral Expansion Connectors

2.15 Peripheral Expansion Connectors

The EVM board contains a group of peripheral expansion connectors used to gain access to the
resources of the 56F8367. The following signal groups have expansion connectors:

• External Memory Address Bus (A0 - A23)

General Purpose Port A (bits 0 - 13)
General Purpose Port E (bits 2 & 3)
General Purpose Port B (bit 0 - 7)
• External Memory Data Bus (D0 - D15)
General Purpose Port F (bits 0 - 15)
• External Memory Control
General Purpose Port D (bits 0 - 5, 8 & 9)
• Quadrature Decoder #0
Quad Timer Channel A
• Quadrature Decoder #1
Serial Peripheral Interface Port #1
Quad Timer Channel B
General Purpose Port C (bits 0 - 3)
• Quad Timer Channel C
General Purpose Port E (bits 8 & 9)
• Quad Timer Channel D
General Purpose Port E (bits 10 - 13)
• A/D Input Port A
• A/D Input Port B
• Serial Communications Port #0 / General Purpose Port E (bits 0 and 1)
• Serial Communications Port #1 / General Purpose Port D (bits 6 and 7)
• Serial Peripheral Interface Port #0 / General Purpose Port E (bits 4 - 7)
• PWM Port A / General Purpose Port C (bits 8 - 10)
• PWM Port B / General Purpose Port C (bits 0 - 3)
• CAN Port #1
• CAN Port #2

Technical Summary, Rev. 2

Freescale Semiconductor 2-27
Preliminary
2.15.1 Address Bus Expansion Connector
The address bus expansion connector contains the 56F8367’s 24 external memory address signal
lines. Address lines A6 and A7 can optionally be used as GPIO Port E lines (bits 2 and 3).
Address lines A8 - A15 can optionally be used as GPIO Port A lines (bits 0 - 7). Address lines
A0 - A5 can optionally be used as GPIO Port A lines (bits 8 - 13). Address lines A16 - A23 are
MPIO signals, which can be configured as A16 - A23 or GPIO Port B bits 0 - 7. Refer to
Table 2-16 for the address bus connector information.

Table 2-16. External Memory Address Bus Connector Description

J4

Pin # Signal Pin # Signal

1 A0 / PA8 2 A1 / PA9

3 A2 / PA10 4 A3 / PA11

5 A4 / PA12 6 A5 / PA13

7 A6 / PE2 8 A7 / PE3

9 A8 / PA0 10 A9 / PA1

11 A10 / PA2 12 A11 / PA3

13 A12 / PA4 14 A13 / PA5

15 A14 / PA6 16 A15 / PA7

17 PB0 / A16 18 PB1 / A17

19 PB2 / A18 20 PB3 / A19

21 PB4 / A20 22 PB5 / A21

23 PB6 / A22 24 PB7 / A23

19 GND 20 +3.3V

MC56F8367EVM User Manual, Rev. 2

2-28 Freescale Semiconductor
Preliminary
 Peripheral Expansion Connectors

2.15.2 Data Bus Expansion Connector

The data bus expansion connector contains the 56F8367’s 16 external memory data signal lines.
Refer to Table 2-17 for the data bus connector information. Data lines D0 - D15 can also be used
as GPIO Port F lines (bits 0 - 15).

Table 2-17. External Memory Address Bus Connector Description

J5

Pin # Signal Pin # Signal

1 D0 / PF9 2 D1 / PF10

3 D2 / PF11 4 D3 / PF12

5 D4 / PF13 6 D5 / PF14

7 D6 / PF15 8 D7 / PF0

9 D8 / PF1 10 D9 / PF2

11 D10 / PF3 12 D11 / PF4

13 D12 / PF5 14 D13 / PF6

15 D14 / PF7 16 D15 / PF8

17 GND 18 +3.3V

Technical Summary, Rev. 2

Freescale Semiconductor 2-29
Preliminary
2.15.3 External Memory Control Signal Expansion Connector
The external memory control signal connector contains the 56F8367’s external memory control
signal lines. CS2 and CS3 are MPIO signals, which can be configured as GPIO Port D lines (bits
0 and 1). Refer to Table 2-18 for the names of these signals.

Table 2-18. External Memory Control Signal Connector Description

J6

Pin # Signal Pin # Signal

1 RD 2 IRQA

3 WR 4 IRQB

5 PS / CS0 6 DS / CS1

7 PD0 / CS2 / CAN2_TX 8 PD1 / CS3 / CAN2_RX

PD2 / CS4 PD3 / CS5

PD4 / CS6 PD5 / CS7

9 CLKO 10 RESET

11 GND 12 RSTO

2.15.4 Encoder #0 / Quad Timer Channel A Expansion Connector

The Encoder #0 / Quad Timer Channel A port is an MPIO port attached to the Timer A expansion
connector. This port can be configured as a Quadrature Decoder interface port or as a Quad
Timer port. Refer to Table 2-19 for the signals attached to the connector.

Table 2-19. Timer A Signal Connector Description

J15

Pin # Signal Pin # Signal

1 PHASEA0 / TA0 2 PHASEB0 / TA1

3 INDEX0 / TA2 4 HOME0 / TA3

5 GND 6 +3.3V

MC56F8367EVM User Manual, Rev. 2

2-30 Freescale Semiconductor
Preliminary
 Peripheral Expansion Connectors

2.15.5 Encoder #1 / SPI #1 Expansion Connector

The Encoder #1 / SPI #1 port is an MPIO port attached to the SPI #1 expansion connector. This
port can be configured as a Quadrature Decoder interface port, a Serial Peripherial Interface,
Quad Timer port or General Purpose I/O port. Refer to Table 2-20 for the signals attached to the
connector.

Table 2-20. SPI #1 Signal Connector Description

J12

Pin # Signal Pin # Signal

1 PHASEB1 / MOSI1 / TB1 / PC1 2 INDEX1 / MISO1 / TB2 / PC2

3 PHASEA1 / SCLK1 / TB0 / PC0 4 HOME1 / SS1 / TB3 / PC3

5 GND 6 +3.3V

2.15.6 Timer Channel C Expansion Connector

The Timer Channel C port is a Quad Timer port attached to the Timer C expansion connector.
This port can be configured as a Quad Timer port or a General Purpose I/O port. Refer to
Table 2-21 for the signals attached to the connector.

Table 2-21. Timer Channel C Connector Description

J16

Pin # Signal Pin # Signal

1 TC0 / PE8 2 TC1 / PE9

3 GND 4 +3.3V

Technical Summary, Rev. 2

Freescale Semiconductor 2-31
Preliminary
2.15.7 Timer Channel D Expansion Connector
The Timer Channel D port is a Quad Timer attached to the Timer D expansion connector. This
port can be configured as a Quad Timer port or a General Purpose I/O port. Refer to Table 2-22
for the signals attached to the connector.

Table 2-22. Timer Channel D Connector Description

J17

Pin # Signal Pin # Signal

1 TD0 / PE10 2 TD1 / PE11

3 TD2 / PE12 4 TD3 / PE13

3 GND 4 +3.3V

MC56F8367EVM User Manual, Rev. 2

2-32 Freescale Semiconductor
Preliminary
 Peripheral Expansion Connectors

2.15.8 A/D Port A Expansion Connector

The eight-channel Analog-to-Digital conversion Port A is attached to this connector. Refer to
Table 2-23 for connection information. There is a Resistor/Connector (R/C) network on each of
the Analog Port A input signals; see Figure 2-14.

Table 2-23. A/D Port A Connector Description

J9

Pin # Signal Pin # Signal

1 AN0 2 AN1

3 AN2 4 AN3

5 AN4 6 AN5

7 AN6 8 AN7

9 GNDA 10 +VREFH

100 ohm
To Processor’s Analog
Analog Input Port
0.0022uF

Figure 2-14. Typical Analog Input RC Filter

Technical Summary, Rev. 2

Freescale Semiconductor 2-33
Preliminary
2.15.9 A/D Port B Expansion Connector
The eight-channel Analog-to-Digital conversion Port B is attached to this connector. Refer to
Table 2-24 for connection information. There is an R/C network on each of the Analog Port B
input signals; see Figure 2-14.

Table 2-24. A/D Port B Connector Description

J10

Pin # Signal Pin # Signal

1 AN8 2 AN9

3 AN10 4 AN11

5 AN12 6 AN13

7 AN14 8 AN15

9 GNDA 10 +VREFH

2.15.10 Serial Communications Port #0 Expansion Connector

The Serial Communications Port #0 is an MPIO port attached to the SCI #0 expansion connector.
This port can be configured as a Serial Communications Interface or as a General Purpose I/O
port. Refer to Table 2-25 for connection information.

Table 2-25. SCI #0 Connector Description

J13

Pin # Signal Pin # Signal

1 TXD0 / PE0 2 RXD0 / PE1

3 GND 4 +3.3V

5 GND 6 +5.0V

MC56F8367EVM User Manual, Rev. 2

2-34 Freescale Semiconductor
Preliminary
 Peripheral Expansion Connectors

2.15.11 Serial Communications Port #1 Expansion Connector

The Serial Communications Port #1 is an MPIO port attached to the SCI #1 expansion connector.
This port can be configured as a Serial Communications Interface or as a General Purpose I/O
port. Refer to Table 2-26 for connection information.

Table 2-26. SCI #1 Connector Description

J14

Pin # Signal Pin # Signal

1 TXD1 / PD6 2 RXD1 / PD7

3 GND 4 +3.3V

5 GND 6 +5.0V

2.15.12 Serial Peripheral Interface #0 Expansion Connector

The Serial Peripheral Interface #0 is an MPIO port attached to this connector. This port can be
configured as a Serial Peripheral Interface or as a General Purpose I/O port. Refer to Table 2-27
for the connection information.

Table 2-27. SPI #0 Connector Description

J11

Pin # Signal Pin # Signal

1 MOSI0 / PE5 2 MISO0 / PE6

3 SCLK0 / PE4 4 SS0 / PE7

5 GND 6 +3.3V

Technical Summary, Rev. 2

Freescale Semiconductor 2-35
Preliminary
2.15.13 FlexCAN #1 Expansion Connector
The FlexCAN Port #1 is attached to this connector. Refer to Table 2-28 for connection
information.

Table 2-28. CAN #1 Connector Description

J18

Pin # Signal Pin # Signal

1 CAN1_TX 2 GND

3 CAN1_RX 4 GND

2.15.14 FlexCAN #2 Expansion Connector

The FlexCAN Port #2 is attached to this connector. Refer to Table 2-29 for connection
information.

Table 2-29. CAN #2 Connector Description

J19

Pin # Signal Pin # Signal

1 CAN2_TX 2 GND

3 CAN2_RX 4 GND

MC56F8367EVM User Manual, Rev. 2

2-36 Freescale Semiconductor
Preliminary
 Peripheral Expansion Connectors

2.15.15 PWM Port A Expansion Connector

The PWM Port A is attached to this connector. Refer to Table 2-30 for connection information.

Table 2-30. PWM Port A Connector Description

J7

Pin # Signal Pin # Signal

1 PWMA0 2 PWMA1

3 PWMA2 4 PWMA3

5 PWMA4 6 PWMA5

7 FAULTA0 8 FAULTA1

9 FAULTA2 10 FAULTA3

11 ISA0 / PC8 12 ISA1 / PC9

13 ISA2 / PC10 14 GND

2.15.16 PWM Port B Expansion Connector

The PWM Port B is attached to this connector. Refer to Table 2-31 for connection information.

Table 2-31. PWM Port B Connector Description

J8

Pin # Signal Pin # Signal

1 PWMB0 2 PWMB1

3 PWMB2 4 PWMB3

5 PWMB4 6 PWMB5

7 FAULTB0 8 FAULTB1

9 FAULTB2 10 FAULTB3

11 ISB0 / PD10 12 ISB1 / PD11

13 ISB2 / PD12 14 GND

Technical Summary, Rev. 2

Freescale Semiconductor 2-37
Preliminary
2.16 Test Points
The 56F8367EVM board has a total of seven test points:

• Analog Ground (AGND)

• Three Digital Grounds (GND)
• +3.3V
• +3.3VA
• +5.0V

MC56F8367EVM User Manual, Rev. 2

2-38 Freescale Semiconductor
Preliminary
 Appendix A
56F8367EVM Schematics

56F8367EVM Schematics, Rev. 2

Freescale Semiconductor Appendix A-1
Preliminary
 A B C D E

U1A

Appendix A-2
A0 154 A0/PA8 PWMA0 73 PWMA0
A1 10 A1/PA9 PWMA1 75 PWMA1
A2 11 A2/PA10 PWMA2 76 PWMA2
12 78 U1B
A3 A3/PA11 PWMA3 PWMA3
A4 13 A4/PA12 PWMA4 79 PWMA4 +3.3V 1 VDD_IO1 VDDA_OSC_PLL 92 +3.3V_PLL
A5 14 A5/PA13 PWMA5 81 PWMA5 16 VDD_IO2
A6 17 A6/PE2 ISA0/PC8 126 ISA0 31 VDD_IO3 VDDA_ADC 114 +3.3VA
4 4
A7 18 A7/PE3 ISA1/PC9 127 ISA1 42 VDD_IO4
A8 19 A8/PA0 ISA2/PC10 128 ISA2 77 VDD_IO5 C14 C57 C58
A9 20 A9/PA1 FAULTA0 82 FAULTA0 +2.5V 96 VDD_IO6 0.1uF 0.001uF 100pF
A10 21 A10/PA2 FAULTA1 84 FAULTA1 134 VDD_IO7
22 85 R67 R68 R69 R70 115
A11 A11/PA3 FAULTA2 FAULTA2 VSSA_ADC
23 87 0 Ohm 0 Ohm 0 Ohm 0 Ohm 141 Single trace
A12 A12/PA4 FAULTA3 FAULTA3 VPP1
24 DNP DNP DNP DNP 2
A13 A13/PA5 VPP2 to GNDA
A14 25 A14/PA6 PHASEA0/TA0/PC4 155 PHASEA0
26 156 VCAPC1 62
A15 A15/PA7 PHASEB0/TA1/PC5 PHASEB0 VCAPC1
33 157 VCAPC2 144 113
PB0 PB0/A16 INDEX0/TA2/PC6 INDEX0 VCAPC2 VREFH +VREFH
34 158 VCAPC3 95
PB1 PB1/A17 HOME0/TA3/PC7 HOME0 VCAPC3
35 VCAPC4 15
PB2 PB2/A18 VCAPC4
36 100 C6 112 VREFP
PB3 PB3/A19 ANA0 ANA0 VREFP
37 101 2.2uF C7 27 111 VREFMID
PB4 PB4/A20/Prescaler_Clock ANA1 ANA1 VSS_IO1 VREFMID
46 102 2.2uF C8 41 110 VREFN
PB5 PB5/A21/SYS_CLK ANA2 ANA2 VSS_IO2 VREFN
47 103 2.2uF C9 74
PB6 PB6/A22/SYS_CLKx2 ANA3 ANA3 VSS_IO3
48 104 2.2uF 80 C15 C16 C17
PB7 PB7/A23/OSC_CLOCK ANA4 ANA4 VSS_IO4
ANA5 105 ANA5 125 VSS_IO5 0.1uF 0.1uF 0.1uF
D0 70 D0/PF9 ANA6 106 ANA6 160 VSS_IO6
D1 71 D1/PF10 ANA7 107 ANA7
D2 83 D2/PF11 91 OCR_DIS VREFLO 109
D3 86 D3/PF12 PWMB0 38 PWMB0 R71 Single trace
88 39 OCR_DIS
D4 D4/PF13 PWMB1 PWMB1 +3.3V
MC56F8367VPY60
to GNDA
3 D5 89 D5/PF14 PWMB2 40 PWMB2 0 Ohm 3
D6 90 D6/PF15 PWMB3 43 PWMB3 DNP
28 44 R72 Use on-chip
D7 D7/PF0 PWMB4 PWMB4
29 45 Use external 0 Ohm
D8 D8/PF1 PWMB5 PWMB5 regulators
D9 30 D9/PF2 ISB0/PD10 61 ISB0 +2.5V Supply
D10 32 D10/PF3 ISB1/PD11 63 ISB1
D11 149 D11/PF4 ISB2/PD12 64 ISB2
D12 150 D12/PF5 FAULTB0 67 FAULTB0
D13 151 D13/PF6 FAULTB1 68 FAULTB1
D14 152 D14/PF7 FAULTB2 69 FAULTB2
D15 153 D15/PF8 FAULTB3 72 FAULTB3

/PS 53 PS/CS0/PD8 ANB0 116 ANB0

/DS 54 DS/CS1/PD9 ANB1 117 ANB1
PD0 55 PD0/CS2/CAN2_TX ANB2 118 ANB2
PD1 56 PD1/CS3/CAN2_RX ANB3 119 ANB3
PD2 57 PD2/CS4 ANB4 120 ANB4
PD3 58 PD3/CS5 ANB5 121 ANB5
PD4 59 PD4/CS6 ANB6 122 ANB6
PD5 60 PD5/CS7 ANB7 123 ANB7 R15 R19
FAULTA0 FAULTB0
/WR 51 WR PHASEA1/TB0/SCLK1/PC0 6 PHASEA1 47K 47K
/RD 52 RD PHASEB1/TB1/MOSI1/PC1 7 PHASEB1
INDEX1/TB2/MISO1/PC2 8 INDEX1
2 EXTBOOT 124 9 HOME1 R16 R20 2
EXTBOOT HOME1/TB3/SS1/PC3 FAULTA1 FAULTB1
EMI_MODE 159 EMI_MODE
TC0/PE8 133 TC0 47K 47K
XTAL 93 XTAL TC1/PE9 135 TC1
EXTAL 94 EXTAL
TD0/PE10 129 TD0 R17 R21
3 130 FAULTA2 FAULTB2
CLKO CLKO TD1/PE11 TD1
CLKMODE 99 CLKMODE TD2/PE12 131 TD2 47K 47K
TD3/PE13 132 TD3

MC56F8367EVM User Manual, Rev. 2

98 TEMP_SENSE
/RESET RESET
/RSTO 97 RSTO CAN1_TX 142 CAN_TX R18 R22
143 C77 FAULTA3 FAULTB3
CAN1_RX CAN_RX
147 JG12 0.1uF
MISO0 MISO0/PE6 47K 47K
148 108 TEMP_SENSE
MOSI0 MOSI0/PE5 TEMP_SENSE 1
146 ANA7
SCLK0 SCLK0/PE4 2
/SS0 145 SS0/PE7 TXD0/PE0 4 TXD0
RXD0/PE1 5 RXD0

TDI 139 TDI TXD1/PD6 49 TXD1

TDO 140 TDO RXD1/PD7 50 RXD1 Digital Signal Controller Operation
TCK 137 TCK
/TRST 136 TRST IRQA 65 /IRQA 2100 East Elliot Road
TMS 138 TMS IRQB 66 /IRQB
Tempe, Arizona 85284
1 1
MC56F8367VPY60 (512) 895-7215 FAX: (480) 413-2510

Title MC56F8367 Processor

Document Rev.
Size Number MC56F8367EVM.DSN
B 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 1 of 14
A B C D E

Figure A-1. 56F8367 Processor

Preliminary
Freescale Semiconductor
 A B C D E

Preliminary
JG1 +3.3V +3.3V
CLOCK MODE JUMPER
1
2 EXTAL USE CRYSTAL 1 - 2
3 R2 R7
OSC BYPASS 10K EXT OSC NC 10K
Y1 1M
4 4
8.00MHz R1 S1 JG6
/POR 2 CLKMODE

Freescale Semiconductor
JG2 1
RESET PUSHBUTTON
1
2 XTAL

+3.3V +3.3V
BOOT MODE JUMPER
EXT BOOT NC +3.3V
INT BOOT R5 R3
1 - 2 10K 10K R8
IRQA PUSHBUTTON
JG15
10K
3 JG4 S2 User 3
PE4 1
2 EXTBOOT /IRQA SCLK0 2
Jumper
1 3 #0
R9
C18
0.1uF
10K

SOFTWARE FEATURE JUMPERS

EMI MODE JUMPER +3.3V
+3.3V
EMI A0-A23 NC +3.3V
EMI A0-A15 1 - 2 R6 R4
10K 10K R10
IRQB PUSHBUTTON
JG16
10K
JG5 S3 User
2 PE7 1 2
2 EMI_MODE /IRQB /SS0 2
Jumper
1 3 #1
R11
C19
0.1uF

56F8367EVM Schematics, Rev. 2

10K
OPTIONAL

+3.3V
Digital Signal Controller Operation
U16
2100 East Elliot Road
2 Vcc
1 /POR Tempe, Arizona 85284
RST
3 GND
(512) 895-7215 FAX: (480) 413-2510
DS1818
1 1
Title RESET, MODE, CLOCK & IRQS
3

DS1818
Document Rev.
Size Number MC56F8367EVM.DSN
1 2 1.0
A Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 2 of 14
A B C D E

Figure A-2. Reset, Mode, Clock & IRQs

Appendix A-3
 A B C D E

128Kx16-bit Program Memory (CS0) 128Kx16-bit Data Memory (CS1/CS4)

Appendix A-4
U2 U3
5 7 A0 5 7 D0
A0 A0 DQ1 D0 A0 DQ1
4 8 A1 4 8 D1
A1 A1 DQ2 D1 A1 DQ2
3 9 A2 3 9 D2
4 A2 A2 DQ3 D2 A2 DQ3 4
2 10 A3 2 10 D3
A3 A3 DQ4 D3 A3 DQ4
1 13 A4 1 13 D4
A4 A4 DQ5 D4 A4 DQ5
44 14 A5 44 14 D5
A5 A5 DQ6 D5 A5 DQ6
43 15 A6 43 15 D6
A6 A6 DQ7 D6 A6 DQ7
42 16 A7 42 16 D7
A7 A7 DQ8 D7 A7 DQ8
27 29 A8 27 29 D8
A8 A8 DQ9 D8 A8 DQ9
26 30 A9 26 30 D9
A9 A9 DQ10 D9 A9 DQ10
25 31 A10 25 31 D10
A10 A10 DQ11 D10 A10 DQ11
24 32 A11 24 32 D11
+3.3V A11 A11 DQ12 D11 A11 DQ12
21 35 A12 21 35 D12
A12 A12 DQ13 D12 A12 DQ13
20 36 A13 20 36 D13
A13 A13 DQ14 D13 A13 DQ14
19 37 A14 19 37 D14
A14 A14 DQ15 D14 A14 DQ15
18 38 A15 18 38 D15
A15 A15 DQ16 D15 A15 DQ16
R12 A16 22 PB0 22
PB0 A16 A16
10K A17 23 PB1 23
PB1 A17 A17
A18 28 PB2 28
PB2 A18 A18
VDD1 11 +3.3V VDD1 11 +3.3V
3 JG7 41 33 /RD 41 33 3
/RD OE VDD2 OE VDD2
17 /WR 17
/PS 1 /WR WE JG8 WE
/ECS0 6 /CE 6
2 /LB CE /ECS1 CE
39 LB VSS1 12 /DS 1 2 39 LB VSS1 12
/UB 40 34 /ECS4 40 34
UB VSS2 PD2 3 4 UB VSS2
GS72116TP-7 R32 GS72116TP-7
R30 R31 1K
1K 1K
Note: A17 & A18 are Note: A17 & A18 are
N/C on GS72116. N/C on GS72116.

+3.3V
CS1/CS4 ENABLE JUMPER
OPTION JG8 R13
CS0 ENABLE JUMPER /ECS1
2 SRAM WORD ENABLE 1-2 3-4 10K 2
OPTION JG7
SRAM UPPER BYTE ENABLE NC 3-4
R14
SRAM ENABLE 1-2 /ECS4
SRAM LOWER BYTE ENABLE 1-2 NC
10K
SRAM DISABLE NC NC

MC56F8367EVM User Manual, Rev. 2

SRAM DISABLE NC

Digital Signal Controller Operation

2100 East Elliot Road
Tempe, Arizona 85284
Note:
(512) 895-7215 FAX: (480) 413-2510
GS71116ATP 64Kx16-bit
1 GS72116ATP 128Kx16-bit 1
GS74116ATP 256Kx16-bit Title PROGRAM [WORD] (CS0) and DATA [BYTE] (CS1/CS4) SRAM MEMORY
IS61LV51216 512Kx16-bit
Document Rev.
Size Number MC56F8367EVM.DSN
A 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 3 of 14
A B C D E

Figure A-3. Program [Word] (CS0) & Data [Byte] (CS1/CS4) SRAM Memory

Preliminary
Freescale Semiconductor
 A B C D E

Preliminary
+3.3V
U4
4 4
28 C1+ VCC 26
C10
C12

Freescale Semiconductor
1.0uF 3
V-
24 C1- 1.0uF
1 C2+
C11 27 C13
1.0uF V+ 1.0uF
2 C2- GND 25
P2
1 DCD
JG9 6 DSR
TXD0 TX_IN 14 9 TXD 2 TXD
1 2 RTS1 T1IN T1OUT RTS
RXD0 3 4 13 T2IN T2OUT 10 7 CTS
T3IN 12 11 3 RXD
T3IN T3OUT 1
8 RTS
20 R2OUTB 4 DTR
RX_OUT 1 19 4 RXD 9
CTS1 R1OUT R1IN CTS
3 18 5 5 GND 3
R2OUT R2IN R3IN
1 17 R3OUT R3IN 6
16 7 R4IN +3.3V
+3.3V 1 R4OUT R4IN R5IN
1 15 R5OUT R5IN 8 SCI #0 /EN R34
/EN 23 RS-232 1K
FORCEON
INVALID 21 1 CONNECTOR
R33 22
RS-232 SHUTDOWN JUMPER 1K FORCEOFF T3IN R35
MAX3245EEAI 1K
RS-232 ENABLE N/C JG10
RS232EN
1 R3IN R36
RS-232 DISABLE 2
1 - 2 1K

R4IN R37

2 1K 2

JG11 R5IN R38

RTS1
1 1K
CTS1
2

56F8367EVM Schematics, Rev. 2

Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
(512) 895-7215 FAX: (480) 413-2510
1 1
Title RS-232 AND SCI CONNECTORS
Document Rev.
Size Number MC56F8367EVM.DSN
A 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 4 of 14
A B C D E

Figure A-4. RS-232 and SCI Connectors

Appendix A-5
 A B C D E

+3.3V
U6A

Appendix A-6
LED1
PC0 R58 RED LED
PHASEA1 1 2
270
74AC04
4 4

U6B
LED2
R59 YELLOW LED
PC1 3 4
PHASEB1
270
74AC04

U6C
LED3
PC2 R60 GREEN LED
INDEX1 5 6
270 USER
74AC04

3 U6D
LED4
LEDS 3

PC3 R61 RED LED

HOME1 9 8
270
74AC04

U6E
LED5
R62 YELLOW LED
PD6 11 10
TXD1
270
74AC04

U6F
LED6
2 PD7 R63 GREEN LED 2
RXD1 13 12
270
74AC04

MC56F8367EVM User Manual, Rev. 2

Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
(512) 895-7215 FAX: (480) 413-2510
1 1
Title USER DEBUG LEDS
Document Rev.
Size Number MC56F8367EVM.DSN
A 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 5 of 14
A B C D E

Figure A-5. User Debug LEDs

Preliminary
Freescale Semiconductor
 A B C D E

Preliminary
+3.3V
U5A
LED7
R52 YELLOW LED
4 PWMA0 1 2 4
270

Freescale Semiconductor
74AC04

U5B
LED8
R53 GREEN LED
PWMA1 3 4
270
74AC04

U5C
LED9
R54 YELLOW LED
PWMA2 5 6 PWM STATE
270
74AC04
3 3
U5D LEDS
LED10
R55 GREEN LED
PWMA3 9 8
270
74AC04

U5E
LED11
R56 YELLOW LED
PWMA4 11 10
270
74AC04

U5F
LED12
R57 GREEN LED
2 PWMA5 13 12 2
270
74AC04

56F8367EVM Schematics, Rev. 2

Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
(512) 895-7215 FAX: (480) 413-2510
1 1
Title PWM PORT A STATE LEDS
Document Rev.
Size Number MC56F8367EVM.DSN
A 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 6 of 14
A B C D E

Figure A-6. PWM Port A State LEDs

Appendix A-7
 A B C D E

Appendix A-8
+5.0V

4 4

R28 +5.0V
1K

U10
CAN_TX 1 TXD VCC 3
CAN_RX 4 RXD VREF 5 1 T1 L6
7 CANH BCANH
CANH CANL BCANL
CANL 6

8 SLOPE GND 2

PCA82C250T

3 3

DAISY-CHAIN
CAN BUS CONNECTOR CAN BUS CONNECTOR
JG13
J20 J21 BCANH CAN BUS
1
TERMINATION
BCANL 1 2 BCANH BCANL 1 2 BCANH 2
3 4 3 4
5 6 5 6
7 8 7 8 R40
9 10 9 10 120
2 2
1/4W
BCANL

MC56F8367EVM User Manual, Rev. 2

Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
(512) 895-7215 FAX: (480) 413-2510
1 1
Title HIGH-SPEED CAN PORT #1 INTERFACE
Document Rev.
Size Number MC56F8367EVM.DSN
A 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 7 of 14
A B C D E

Figure A-7. High-Speed CAN Port #1 Interface

Preliminary
Freescale Semiconductor
 A B C D E

Preliminary
+5.0V

4 4

Freescale Semiconductor
R29 +5.0V
1K

JG14 U11
CAN2_TX 1 3
PD0 1 2 TXD VCC
CAN2_RX 4 5
PD1 3 4 RXD VREF 1 T2 L7
7 CAN2H BCAN2H
CANH CAN2L BCAN2L
CANL 6

8 SLOPE GND 2

PCA82C250T

3 3

DAISY-CHAIN
CAN BUS CONNECTOR CAN BUS CONNECTOR
JG17
J22 J23 BCAN2H CAN BUS
1
TERMINATION
BCAN2L 1 2 BCAN2H BCAN2L 1 2 BCAN2H 2
3 4 3 4
5 6 5 6
7 8 7 8 R41
9 10 9 10 120
2 2
1/4W
BCAN2L

56F8367EVM Schematics, Rev. 2

Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
(512) 895-7215 FAX: (480) 413-2510
1 1
Title HIGH-SPEED CAN PORT #2 INTERFACE
Document Rev.
Size Number MC56F8367EVM.DSN
A 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 8 of 14
A B C D E

Figure A-8. High-Speed CAN Port #2 Interface

Appendix A-9
 A B C D E

Appendix A-10
J1
J2
+12V 1 2 +12V
GND GND
4 3 4 A4 1 2 A5 4
+5.0V 5 6 +5.0V A3 3 4 A6
GND GND
7 8 A2 5 6 A7
+3.3V 9 10 +3.3V A1 A20 7 8 /RD
GND GND GND
TA0 11 12 TA1 PB4 9 10 /CS1
PHASEA0 TA2 13 14 TA3 PHASEB0 A0 /CS0 11 12 /CS2/CAN2_TX /DS
INDEX0 15 16 HOME0 /PS 13 14 PD0
GND GND
PC0/TB0/SCLK1 17 18 PC1/TB1/MOSI1 D0 15 16 D15
PHASEA1 PC2/TB2/MISO1 19 20 PC3/TB3/SS1 PHASEB1 D1 /CS6 17 18 /CS7 D14
INDEX1 PE0 GND 21 22 GND PD6 HOME1 PD4 19 20 PD5
GND GND
TXD0 23 24 TXD1 21 22
TXD0 25 26 TXD1 D2 23 24 D13
RXD0 27 28 RXD1 D3 25 26 D12
/IRQA PE1 GND 29 30 GND PD7 /IRQB D4 27 28 D11
RXD0 31 32 RXD1 D5 /CS5 29 30 /CS4 D10
PWMB0 33 34 PWMB1 PD3 31 32 PD2
GND GND
PWMB2 35 36 PWMB3 33 34
PWMB4 37 38 PWMB5 D6 35 36 D9
3 GND GND 3
39 40 D7 37 38 /CS3/CAN2_RX D8
ISB0 41 42 ISB1 /WR 39 40 PD1
GND
ISB2 43 44 A15 A19 41 42 A18 A8
FAULTB1 45 46 FAULTB0 PB3 43 44 PB2
FAULTB3 47 48 FAULTB2 A14 45 46 A9
GND GND
49 50 A13 47 48 A10
PWMA0 51 52 PWMA1 A12 A16 49 50 A17 A11
PWMA2 53 54 PWMA3 PB0 51 52 PB1
GND GND
PWMA4 55 56 PWMA5 53 54
GND GND
57 58 +3.3V 55 56 +3.3V
GND GND
FAULTA0 59 60 GND PE6 FAULTA1 57 58
FAULTA2 61 62 MISO0 +5.0V 59 60 +5.0V
ISA0 63 64 ISA1
ISA2 65 66 /RSTO Daughter Address/Data Connector
PE5 GND GND PE7
MOSI0 67 68 /SS0
TD0 PE4 GND 69 70 TD1
SCLK0 71 72 TC0
2 CAN_TX 73 74 CAN_RX 2
MOSI0 75 76 MISO0
GNDA GND
SCLK0 77 78 /SS0
GND GND
79 80
+3.3VA 81 82 +3.3VA
GNDA GNDA
83 84
AN0 85 86 AN1

MC56F8367EVM User Manual, Rev. 2

AN2 87 88 AN3
AN4 89 90 AN5
AN6 91 92 AN7
AN8 93 94 AN9 Digital Signal Controller Operation
AN10 95 96 AN11
AN12 97 98 AN13 2100 East Elliot Road
AN14 99 100 AN15
Tempe, Arizona 85284
Daughter Peripheral Port Connector
(512) 895-7215 FAX: (480) 413-2510
1 1
Title DAUGHTER CARD CONNECTORS
Document Rev.
Size Number MC56F8367EVM.DSN
A 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 9 of 14
A B C D E

Figure A-9. Daughter Card Connectors

Preliminary
Freescale Semiconductor
 A B C D E

Preliminary
J4 J5 J6
A0 1 2 A1 D0 1 2 D1 /RD 1 2 /IRQA
A2 3 4 A3 D2 3 4 D3 /WR /CS0 3 4 /CS1 /IRQB
A4 5 6 A5 D4 5 6 D5 /PS /CS2 5 6 /CS3 /DS
A6 7 8 A7 D6 7 8 D7 PD0 /CS4 7 8 /CS5 PD1
A8 9 10 A9 D8 9 10 D9 PD2 /CS6 9 10 /CS7 PD3
4 A10 11 12 A11 D10 11 12 D11 PD4 11 12 PD5 4
A12 13 14 A13 D12 13 14 D13 CLKO 13 14 /RESET
A14 15 16 A15 D14 15 16 D15 15 16 /RSTO
PB0 A16 A17 PB1 +3.3V
17 18 17 18
PB2 A18 A19 PB3 ADDRESS CONTROL

Freescale Semiconductor
19 20
PB4 A20 A21 PB5 DATA BUS
21 22
PB6 A22 A23 PB7
23 24
25 26 +3.3V
ADDRESS BUS

J7 J8 J9 J10
PWMA0 1 2 PWMA1 PWMB0 1 2 PWMB1 AN0 1 2 AN1 AN8 1 2 AN9
PWMA2 3 4 PWMA3 PWMB2 3 4 PWMB3 AN2 3 4 AN3 AN10 3 4 AN11
PWMA4 5 6 PWMA5 PWMB4 5 6 PWMB5 AN4 5 6 AN5 AN12 5 6 AN13
FAULTA0 7 8 FAULTA1 FAULTB0 7 8 FAULTB1 AN6 7 8 AN7 AN14 7 8 AN15
FAULTA2 9 10 FAULTA3 FAULTB2 9 10 FAULTB3 9 10 +3.3VA 9 10 +3.3VA
ISA0 11 12 ISA1 ISB0 11 12 ISB1
3 ISA2 13 14 ISB2 13 14
A/D PORT A A/D PORT B 3

PWMA PWMB

J11 J12 J13 J14

MOSI1 MISO1
MOSI0 1 2 MISO0 PHASEB1 SCLK1 1 2 /SS1 INDEX1 TXD0 1 2 RXD0 TXD1 1 2 RXD1
SCLK0 3 4 /SS0 PHASEA1 3 4 HOME1 3 4 +3.3V 3 4 +3.3V
5 6 +3.3V 5 6 +3.3V 5 6 +5.0V 5 6 +5.0V
SPI #0 SPI #1 SCI #0 SCI #1
&
QUAD-DECODER #1

2 2

J15 J16 J17

TA0 TA1

56F8367EVM Schematics, Rev. 2

PHASEA0 TA2 1 2 TA3 PHASEB0 TC0 1 2 TC1 TD0 1 2 TD1
INDEX0 3 4 HOME0 3 4 +3.3V TD2 3 4 TD3
5 6 +3.3V 5 6 +3.3V
TIMER CHANNEL C
TIMER CHANNEL A TIMER CHANNEL D
&
QUAD-DECODER #0

Digital Signal Controller Operation

2100 East Elliot Road
J18 J19 Tempe, Arizona 85284
1 CAN2_TX 1
CAN_TX 1 2 PD0 CAN2_RX 1 2
CAN_RX 3 4 PD1 3 4 (512) 895-7215 FAX: (480) 413-2510
CAN #1 CAN #2
Title PROCESSOR PORT EXPANSION CONNECTORS
Document Rev.
Size Number MC56F8367EVM.DSN
B 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 10 of 14
A B C D E

Figure A-10. Processor Port Expansion Connectors

Appendix A-11
 A B C D E

Appendix A-12
Parallel JTAG Interface
4 4

PORT_IDENT

P1
1
14 U8 R73 U9
2 PORT_RESET 2 18 2 18 P_RESET
1A1 1Y1 1A1 1Y1
15 0 Ohm R74
3 PORT_TMS 4 16 4 16 TMS
1A2 1Y2 1A2 1Y2
16 R75 0 Ohm
4 PORT_TCK 6 14 6 14 TCK
1A3 1Y3 1A3 1Y3
17 0 Ohm R76
5 PORT_TDI 8 12 8 12 TDI
1A4 1Y4 1A4 1Y4
18 R77 0 Ohm
6 /PORT_TRST 11 9 11 9 /J_TRST
2A1 2Y1 2A1 2Y1
19 R43 0 Ohm
7 PORT_DE 13 7 7 13 P_DE +3.3V
2A2 2Y2 1 1 2Y2 2A2
20 5.1K
8 JG19 +Vsel 15 5 15 TDO R24
2A3 2Y3 2A3 TDO
21 +3.3V 1
9 20 17 3 17 PWR
PORT_VCC 2 VCC 2A4 2Y4 2A4 47K
3 22 +5.0V 3 3
10 +3.3V
R25
23 1 PWR
R51 1G
11 PORT_TDO 5 20
2Y3 /CCEN VCC 47K
24 51 Ohm 2G 19 1 1G
12 PORT_PU 19 10 R26
2G GND /DE
25 R50
PORT_CONNECT R44 R45

2
1
13 3 2Y4 GND 10 JG3 47K
5.1K 5.1K MC74LCX244DW
51 Ohm
MC74HC244DW R46
5.1K
On-Board
Host Target Interface
R27
Disable /J_TRST

47K
R47
P_DE
5.1K

+3.3V
2 U7A U7B 2
/J_RESET 1 4
R42 3 6 J3
/RESET
5.1K 2 5 /DE /J_TRST
/POR 13 14
/J_RESET +3.3V /J_RESET 11 12
74AC00 74AC00 TMS
9 10
7 8 KEY
U7D U7C
R48 TCK 5 6
12 9 TDO 3 4

MC56F8367EVM User Manual, Rev. 2

P_RESET Q1 11 8
2N2222A /TRST TDI 1 2
/J_TRST 13 10
5.1K JTAG Connector
R23 74AC00 74AC00
47K

Digital Signal Controller Operation

+Vsel 2100 East Elliot Road
Tempe, Arizona 85284
1 1
R94
PORT_PU (512) 895-7215 FAX: (480) 413-2510
1K
Title PARALLEL JTAG HOST TARGET INTERFACE AND JTAG CONNECTOR
R95
PORT_CONNECT Document
MC56F8367EVM.DSN Rev.
1K Size Number
DNP
B 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 11 of 14
A B C D E

Figure A-11. Parallel JTAG Host Target Interface and JTAG Connector

Preliminary
Freescale Semiconductor
 A B C D E

Preliminary
R78 R85 R90
AN0 ANA0 AN7 ANA7 AN12 ANB4
100 100 100
C59 C66 C71
4 0.0022uF 0.0022uF 0.0022uF 4

Freescale Semiconductor
R79 R86 R91
AN1 ANA1 AN8 ANB0 AN13 ANB5
100 100 100
C60 C67 C72
0.0022uF 0.0022uF 0.0022uF

R80 R87 R92

AN2 ANA2 AN9 ANB1 AN14 ANB6
100 100 100
3 C61 C68 C73 3
0.0022uF 0.0022uF 0.0022uF

R81 R88 R93

AN3 ANA3 AN10 ANB2 AN15 ANB7
100 100 100
C62 C69 C74
0.0022uF 0.0022uF 0.0022uF

R82 R89
AN4 ANA4 AN11 ANB3
100 100
2 2
C63 C70
0.0022uF 0.0022uF NOTE: Use a single trace
for GNDA signals to the
common GNDA point.

56F8367EVM Schematics, Rev. 2

R83
AN5 ANA5
100
C64
0.0022uF Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
R84
AN6 ANA6 (512) 895-7215 FAX: (480) 413-2510
100
1 1
C65 Title A/D INPUT FILTERS
0.0022uF
Document Rev.
Size Number MC56F8367EVM.DSN
A 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 12 of 14
A B C D E

Figure A-12. A/D Input Filters

Appendix A-13
 A B C D E

Appendix A-14
EXTERNAL POWER INPUT
7-12V DC/AC D2

4 P3 4

2 1 FM4001
+12V

3
D1

3
U12 +5.0V

2 - + 1 3 2 J24
VIN VOUT
L1 +2.5V +2.5V Input
+ C1 C20 1
1 GND VOUT 4 2
470uF 0.1uF +2.5V Ground Reference
FERRITE BEAD +
16VDC C2

4
MC33269DT-5.0 47uF
10VDC
External +2.5V +5.0V
Power Supply
Input
R64
D4 D3 270

DNP DNP POWER GOOD LED

FM4001 FM4001
LED13
3 GREEN LED 3
U14 U13
VCC
+5.0V 3 VIN VOUT 2 +5.0V 3 VIN VOUT 2
L4 L2
1 GND VOUT 4 +3.3V 1 GND VOUT 4 +3.3VA
FERRITE BEAD + Typ 135mA FERRITE BEAD
C3
MC33269DT-3.3 47uF MC33269DT-3.3 C22 + C4
10VDC 0.1uF 47uF
L3 10VDC JG18 NOTE: Remove 0 OHM
1 resistor to use Analog
FERRITE BEAD 2 GND isolation jumper.
NOTE: To measure +3.3V supply
R66
current, remove L2 and replace 0 Ohm
with amp meter.
Single trace
to GNDA.

2 L5 U15 2
+3.3V +3.3V_PLL +5.0V 1 VIN R65 3.3V AND 5.0V
5
+3.3V
FERRITE BEAD VOUT +VREFH 3.3V REF
3 EN 10 Ohm
REGULATOR
NR 4 REGULATOR
+ C5 C21 2 + C75
47uF 0.1uF GND C76 10uF 4
10VDC REG113NA-3.3/3K 0.01uF 6VDC
1 5

MC56F8367EVM User Manual, Rev. 2

2 1 2 3
3 4

REG113NA3/3K MC33269

Digital Signal Controller Operation

+3.3V +3.3VA GROUND GROUND GROUND ANALOG GROUND +5.0V
2100 East Elliot Road
TEST POINT TEST POINT TEST POINT TEST POINT TEST POINT TEST POINT TEST POINT Tempe, Arizona 85284
1 TP4 TP5 TP1 TP2 TP3 TP6 TP7 1

1
1
1
1
1
1
1

(512) 895-7215 FAX: (480) 413-2510

Title POWER SUPPLIES

+3.3V +3.3VA +5.0V Document
MC56F8367EVM.DSN Rev.
Size Number
B 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 13 of 14
A B C D E

Figure A-13. Power Supplies

Preliminary
Freescale Semiconductor
 A B C D E

Preliminary
U1
MC56F8367
+3.3V +VREFH

4 4

Freescale Semiconductor
C23 C24 C25 C26 C52 C53 C54 C27 C28
0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.1uF 0.1uF

U2 U3 U4 U5 U6 U7 U8 U9 U10 U11
GS72116 GS72116 MAX3245 74AC04 74AC04 74AC00 74HC244 74LCX244 PCA82C250 PCA82C250
3 3
+3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +Vsel +3.3V +5.0V +5.0V

C29 C55 C30 C56 C51 C38 C39 C37 C36 C35 C31 C32
0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
DNP

J4 J5
J1 J2 ADDRESS BUS DATA BUS J9 J10
PERIPHERAL CONNECTOR MEMORY CONNECTOR CONNECTOR CONNECTOR A/D CONNECTOR A/D CONNECTOR

2 +5.0V +3.3V +12V +3.3VA +5.0V +3.3V +3.3V +3.3V +3.3V +3.3VA +3.3VA 2

C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

56F8367EVM Schematics, Rev. 2

Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
1 1
(512) 895-7215 FAX: (480) 413-2510

Title BYPASS CAPACITORS

Document Rev.
Size Number MC56F8367EVM.DSN
B 1.0
Date: Thursday, September 02, 2004 Designer: DSCO Design Sheet 14 of 14
A B C D E

Figure A-14. Bypass Capacitors

Appendix A-15
 MC56F8367EVM User Manual, Rev. 2
Appendix A-16 Freescale Semiconductor
Preliminary
Appendix B
56F8367EVM Bill of Material

Qty Description Ref. Designators Vendor Part #

Integrated Circuits

1 MC56F8367 U1 Freescale, MC56F8367VPY60

2 128K x 16-Bit SRAM U2, U3 GSI, GS72116ATP-8

1 RS-232 Transceiver U4 Maxim, MAX3245EEAI

2 74AC04 U5, U6 ON Semiconductor, MC74AC04AD

1 74AC00 U7 Fairchild, 74AC00SC

1 74HC244 U8 ON Semiconductor, MC74LHC44AADW

1 74LCX244 U9 ON Semiconductor, MC74LCX244ADW

2 CAN Transceiver U10, U11 Philips Semiconductor, PCA82C250T

1 +5.0V Voltage Regulator U12 ON Semiconductor, MC33269DT-5

2 +3.3V Voltage Regulator U13, U14 ON Semiconductor, MC33269DT-3.3

1 +3.3V Voltage Regulator U15 Burr-Brown, REG113NA-3.3

0 Power-On Reset U16 (Optional) Dallas Semiconductor, DS1818

Resistors

1 1MΩ R1 SMEC, RC73L2A105OHMJT

13 10KΩ R2 - R14 SMEC, RC73L2A103OHMJT

13 47KΩ R15 - R27 SMEC, RC73L2A473OHMJT

12 1KΩ R28 - R38, R94 SMEC, RC73L2A103OHMJT

0 1KΩ R95 (Optional) SMEC, RC73L2A103OHMJT

2 120Ω, 1/4W R40, R41 YAGEO, CFR 120QBK

56F8367EVM Bill of Material, Rev. 2

Freescale Semiconductor Appendix B-1
Preliminary
 Qty Description Ref. Designators Vendor Part #

Resistors (Continued)

7 5.1KΩ R42 - R48 SMEC, RC73L2A512OHMJT

2 51Ω R50, R51 SMEC, RC73L2A51OHMJT

13 270Ω R52 - R64 SMEC, RC73L2A271OHMJT

1 10Ω R65 SMEC, RC73L2A100OHMJT

7 0Ω R66, R72 - R77 SMEC, RC73JP2A

0 0Ω R67 - R71 (Optional) SMEC, RC73JP2A

16 100Ω R78 - R93 SMEC, RC73L2A101OHMJT

Inductors

5 1.0mH FERRITE BEAD L1 - L5 Panasonic, EXC-ELSA35V

2 CAN Bus Filter L6, L7 EPCOS, B82790-S0513-N201

LEDs

2 Red LED LED1, LED4 Hewlett-Packard, HSMS-C650

5 Yellow LED LED2, LED5, LED7, LED9, Hewlett-Packard, HSMY-C650

LED11

6 Green LED LED3, LED6, LED8, LED10, Hewlett-Packard, HSMG-C650

LED12, LED13

Diode

1 +50V 1A BRIDGE RECT D1 DIODES, DF02S

1 S2B-FM401 D2 Vishay, DL4001DICT

0 S2B-FM401 D3, D4 (Optional) Vishay, DL4001DICT

Capacitors

1 470µF, +16V DC C1 ELMA, RV-16V471MH10R

4 47µF, +16V DC C2 - C5 ELMA, RV2-16V470M-R

4 2.2µF, +25V DC C6 - C9 TAIYO YUDEN, CELMK212BJ225MG-T

(Low ESR)

4 1.0µF, +25V DC C10 - C13 SMEC, MCCE105K3NR-T1

37 0.1µF C14 - C32, C35 - C51, C77 SMEC, MCCE104K2NR-T1

6 0.01µF C52 - C56, C76 SMEC, MCCE103K2NR-T1

MC56F8367EVM User Manual, Rev. 2

Appendix B-2 Freescale Semiconductor
Preliminary
 Qty Description Ref. Designators Vendor Part #

Capacitors (Continued)

1 0.001µF C57 SMEC, MCCE102K2NR-T1

1 100pF C58 SMEC, MCCE101K2NR-T1

16 0.0022µF C59 - C74 SMEC, MCCE222K2NR-T1

1 10µF, +10V DC C75 KEMET, T494B106M010AS

Jumpers

4 3 × 1 Bergstick JG1, JG15, JG16, JG19 SAMTEC, TSW-103-07-S-S

12 1 × 2 Bergstick JG2 - JG7, JG10 - JG13, JG17, SAMTEC, TSW-102-07-S-S

JG18

3 2 × 2 Bergstick JG8, JG9, JG14 SAMTEC, TSW-102-07-S-D

Test Points

3 GND Test Point TP1, TP2, TP3 KEYSTONE, 5001, BLACK

1 +3.3V Test Point TP4 KEYSTONE, 5000, RED

1 +3.3V A Test Point TP5 KEYSTONE, 5004, YELLOW

1 GNDA Test Point TP6 KEYSTONE, 5002, WHITE

1 +5.0V Test Point TP7 KEYSTONE, 5003, ORANGE

Crystals

1 8.00MHz Crystal Y1 CTS, ATS08ASM-T

Connectors

1 DB25M Connector P1 AMPHENOL, 617-C025P-AJ121

1 DE9S Connector P2 AMPHENOL, 617-C009S-AJ120

1 2.1mm coax P3 Switchcraft, RAPC-722

Power Connector

1 Peripheral Daughter Card J1 HRS, FX6-100P-0.8SV2

Connector

1 Memory Bus Daughter J2 HRS, FX6-60P-0.8SV2

Card Connector

1 7 x 2 JTAG Header J3 SAMTEC, TSW-106-07-S-D

1 13 x 2 Header J4 SAMTEC, TSW-106-13-S-D

56F8367EVM Bill of Material, Rev. 2

Freescale Semiconductor Appendix B-3
Preliminary
 Qty Description Ref. Designators Vendor Part #

Connectors (Continued)

1 9 x 2 Header J5 SAMTEC, TSW-106-09-S-D

1 8 x 2 Header J6 SAMTEC, TSW-106-08-S-D

2 7 x 2 Header J7, J8 SAMTEC, TSW-106-07-S-D

6 5 x 2 Header J9, J10, J20 - J23 SAMTEC, TSW-106-05-S-D

6 3 x 2 Header J11 - J15, J17 SAMTEC, TSW-106-03-S-D

3 2 x 2 Header J16, J18, J19 SAMTEC, TSW-106-02-S-D

Switches

3 SPST Push button S1 - S3 Panasonic, EVQ-PAD05R

Transistors

1 2N2222A Q1 ZETEX, FMMT2222ACT

Miscellaneous

18 Shunt SH1 - SH13 Samtec, SNT-100-BL-T

4 Rubber Feet RF1 - RF4 3M, SJ5018BLKC

MC56F8367EVM User Manual, Rev. 2

Appendix B-4 Freescale Semiconductor
Preliminary
 INDEX
Numerics F
1.2 Amp power supply 2-17 FlexCAN Preface-ix
56F8300 Peripheral User Manual 2-4 FlexCAN Interface Module
56F8357 Technical Data Sheet 2-4 FlexCAN Preface-ix
8.00MHz crystal oscillator 2-1 FSRAM 2-1, 2-5, 2-6

A G
A/D Preface-ix General Purpose Input and Output
ADC Preface-ix GPIO Preface-ix
Analog-to-Digital GPIO Preface-ix, 2-28
A/D Preface-ix
Analog-to-Digital Converter H
ADC Preface-ix
Host Parallel Interface Connector 2-11
C Host Target Interface 2-11

CAN Preface-ix I
bus termination 2-1, 2-2
bypass 2-1, 2-2 IC Preface-ix
interface 2-1 Integrated Circuit
CAN in Automation IC Preface-ix
CiA Preface-ix
CAN physical layer peripheral 2-2 J
CiA Preface-ix
Joint Test Action Group
Controller Area Network
JTAG Preface-ix
CAN Preface-ix
JTAG Preface-ix, 2-1
D JTAG/Enhanced OnCE (EOnCE) 1-1
Jumper Group 1-4
D/A Preface-ix JG1 1-4
Daughter Card Expansion JG10 1-4
interface 2-1 JG11 1-4
Debugging 2-10 JG12 1-4
Digital-to-Analog JG13 1-4
D/A Preface-ix JG14 1-4
DSP56800E Reference Manual 2-4 JG15 1-4
JG16 1-4
E JG17 1-4
JG18 1-4
Enhanced On-Chip Emulation JG19 1-4
EOnCE Preface-ix JG2 1-4
EOnce Preface-ix JG3 1-4
Evaluation Module JG4 1-4
EVM Preface-ix JG5 1-4
EVM Preface-ix JG6 1-4
External oscillator frequency input 2-1 JG7 1-4
JG8 1-4
JG9 1-4

Index, Rev. 2
Freescale Semiconductor Index-1
Preliminary
L R
LED Preface-ix R/C Preface-x
Light Emitting Diode RAM Preface-x
LED Preface-ix Random Access Memory
Low-profile Quad Flat Package RAM Preface-x
LQFP Preface-ix Read-Only Memory
LQFP Preface-ix ROM Preface-x
real-time debugging 2-10
M Resistor/Capacitor Network
R/C Preface-x
MPIO Preface-ix, 2-31 ROM Preface-x
Multi Purpose Input and Output RS-232 2-1
MPIO Preface-ix level converter 2-7
schematic diagram 2-7
O
S
On-board power regulation 2-3
OnCE Preface-ix SCI Preface-x
On-Chip Emulation SCI/MPIO-compatible peripheral 2-2
OnCE Preface-ix Serial Communications Interface
SCI Preface-x
P Serial Peripheral Interface
SPI Preface-x
Parallel JTAG Host Target Interface 2-1
SPI Preface-x
PCB Preface-ix
SPI/MPIO-compatible peripheral 2-2
peripheral port signals 2-18
SRAM Preface-x
Phase Locked Loop
external data 2-1
PLL Preface-ix
external program 2-1
PLL Preface-ix
Static Random Access Memory
Printed Circuit Board
SRAM Preface-x
PCB Preface-ix
Pulse Width Modulation T
PWM Preface-ix
PWM Preface-ix Timer-compatible peripheral 2-2
PWMA-compatible peripheral 2-2
PWMB-compatible peripheral 2-2 W
Q Wait State
WS Preface-x
QuadDec Preface-ix WS Preface-x
Quadrature Decoder
interface port 2-30
QuadDec Preface-ix

MC56F8367EVM User Manual, Rev. 2

Index-2 Freescale Semiconductor
Preliminary
How to Reach Us:
Home Page:
www.freescale.com

E-mail:
[email protected]

USA/Europe or Locations Not Listed:

Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
[email protected]

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
[email protected]

Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064, Japan Information in this document is provided solely to enable system and
0120 191014 or +81 3 5437 9125 software implementers to use Freescale Semiconductor products. There are
[email protected] no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
2 Dai King Street
representation or guarantee regarding the suitability of its products for any
Tai Po Industrial Estate particular purpose, nor does Freescale Semiconductor assume any liability
Tai Po, N.T., Hong Kong arising out of the application or use of any product or circuit, and specifically
+800 2666 8080 disclaims any and all liability, including without limitation consequential or
[email protected] incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
For Literature Requests Only: applications and actual performance may vary over time. All operating
Freescale Semiconductor Literature Distribution Center parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
P.O. Box 5405
not convey any license under its patent rights nor the rights of others.
Denver, Colorado 80217 Freescale Semiconductor products are not designed, intended, or authorized
1-800-441-2447 or 303-675-2140 for use as components in systems intended for surgical implant into the body,
Fax: 303-675-2150 or other applications intended to support or sustain life, or for any other
[email protected] application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor,

Inc. All other product or service names are the property of their respective owners.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.

MC56F8367EVMUM
Rev. 2
07/2005