BACHELOR DEGREE IN

ELECTRICAL&ELECTRONICS ENGINEERING
UNIVERSITY OF BRADFORD, UK

ENG 3051M: DIGITAL DESIGN USING HDL

TITLE: EXPERIMENT 1(REALISATION OF GATES)
OBJECTIVE

To be able to write and simulate the VHDL coding of Logic gates below :

1. 2 input AND gate

2. 2 input NAND gate
3. 2 input OR gate
4. 2 input NOR gate
5. EXCLUSIVE OR ( XOR ) gate
6. EXCLUSIVE NOR ( XNOR ) gate
7. NOT gate ( INVERTER )

THEORY

Boolean functions may be practically implemented by using electronic gates.

Electronic gates require a power supply. Gate inputs are driven by voltages having two nominal
values, they represent logic 0 and logic 1 . While the output of a gate provides two nominal values
of voltage only, they also represent logic 0 and logic 1 .

Logic gates
Digital systems are said to be constructed by using three basic logic gates. These gates are the
AND gate, OR gate and NOT gate. There also exists other logical gates, like the NAND,NOR,
XOR,and XNOR gates. All the operation of the gates are discussed below.

AND gate

The AND gate is an electronic circuit that gives a high output (1) if all its inputs are high. A dot (.) is
used to show the AND operation.
NAND gate

This is a NOT-AND circuit which is equal to an AND circuit followed by a NOT circuit. The output of
all AND gates are high if any of the inputs are low.

OR gate

The OR gate is an electronic circuit that gives a high output if one or more of its inputs are high. A
plus (+) is used to describe the OR operations.

NOR gate

This is a NOT-OR circuit which is equal to an OR circuit followed by a NOT circuit. The output of all
NOR gates are high if any of the inputs are high.

XOR gate

The Exclusive-OR gate is a circuit which will give a high output if either, but not both, of its two
inputs are high. An encircled plus sign ( ) is used to show the EOR operations.
XNOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if
either, but not both, of its two inputs are high. The symbol is an XOR gate with a small circle on
the output. The small circle represents inversion.

NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the inputs logic at its
output. It is also known as an inverter. If the input variable is A, the inverted output is known as
NOT A.
ALGORITHM & DISCUSSION

i) AND gate

Library ieee ;
Use ieee.std_logic_1164.all ; // import std logic from IEEE Library
Entity AND_gate is // entity is declared as AND gate is used
Port (A,B; in bit ; C: out bit) ; // A,B are assigned as input and C as output
End entity AND_gate ; // declares the end of the entity
Architecture LogicFunction of AND_gate is // The operation of and gate is executed
begin
C<= A and B // output C is obtained by operation of A and B
End architecture LogicFunction ; // end of and gate execution

ii) NAND gate

Library ieee ;
Use ieee.std_logic_1164.all ; // import std logic from IEEE Library
Entity NAND_gate is // entity is declared as NAND gate is used
Port (A,B; in bit ; C: out bit) ; // A,B are assigned as input and C as output
End entity NAND_gate ; // declares the end of the entity
Architecture LogicFunction of NAND_gate is begin // The operation of nandgate is
executed
C<= A nand B // output C is obtained by operation of A nand B
End architecture LogicFunction ; // end of nand gate execution

iii) OR gate

Library ieee ; // import std logic from IEEE Library

Use ieee.std_logic_1164.all ;
Entity OR_gate is // entity is declared as OR gate is used
Port (A,B; in bit ; C: out bit) ; // A,B are assigned as input and C as output
End entity OR_gate ; // declares the end of the entity
Architecture LogicFunction of OR_gate is begin// The operation of or gate is executed
 C<= A or B // output C is obtained by operation of A and B
End architecture LogicFunction ; // end of or gate execution

iv) NOR gate

Library ieee ; // import std logic from IEEE Library

Use ieee.std_logic_1164.all ;
Entity NOR_gate is // entity is declared as NOR gate is used
Port (A,B; in bit ; C: out bit) ; // A,B are assigned as input and C as output
End entity NOR_gate ; // declares the end of the entity
Architecture LogicFunction of NOR_gate is // The operation of nor gate is executed
begin
C<= A nor B // output C is obtained by operation of A nor B
End architecture LogicFunction ; // end of nor gate execution

v) EXCLUSIVE OR ( XOR ) gate

Library ieee ; // import std logic from IEEE Library

Use ieee.std_logic_1164.all ;
Entity XOR_gate is // entity is declared as XOR gate is used
Port (A,B; in bit ; C: out bit) ; // A,B are assigned as input and C as output
End entity XOR_gate ; // declares the end of the entity
Architecture LogicFunction of XOR_gate is // The operation of xor gate is executed
begin
C<= A xor B // output C is obtained by operation of A xor B
End architecture LogicFunction ; // end of xor gate execution

vi) EXCLUSIVE NOR ( XNOR ) gate

Library ieee ; // import std logic from IEEE Library

Use ieee.std_logic_1164.all ;
Entity XNOR_gate is // entity is declared as XNOR gate is used
Port (A,B; in bit ; C: out bit) ; // A,B are assigned as input and C as output
End entity XNOR_gate ; // declares the end of the entity
Architecture LogicFunction of XNOR_gate is // The operation of xnor gate is executed
begin
C<= A xnor B // output C is obtained by operation of A xnor B
End architecture LogicFunction ; // end of xnor gate execution
vii) NOT gate ( INVERTER )

Library ieee ; // import std logic from IEEE Library

Use ieee.std_logic_1164.all ;
Entity NOT_gate is // entity is declared as NOT gate is used
Port (A; in bit ; C: out bit) ; // A is assigned as input and C as output
End entity NOT_gate ; // declares the end of the entity
Architecture LogicFunction of NOT_gate is // The operation of not gate is executed
begin
C<= not A // output C is obtained by operation of not A
End architecture LogicFunction ; // end of not gate execution
RESULT

i) AND gate

- Truth Table

Inputs Outputs
A B C
0 0 0
0 1 0
1 0 0
1 1 1

- Program

- Waveform
ii) NAND gate

- Truth Table

Inputs Outputs
A B C
0 0 0
0 1 0
1 0 0
1 1 1

- Program

- Waveform
iii) OR gate

- Truth Table

Inputs Outputs
A B C
0 0 0
0 1 1
1 0 1
1 1 1

- Program

- Waveform
iv) NOR gate

- Truth Table

Inputs Outputs
A B C
0 0 1
0 1 0
1 0 1
1 1 1

- Program

- Waveform
v) EXCLUSIVE OR ( XOR ) gate

- Truth Table

Inputs Outputs
A B C
0 0 0
0 1 1
1 0 1
1 1 0

- Program

- Waveform
vi) EXCLUSIVE NOR ( XNOR ) gate

- Truth Table

Inputs Outputs
A B C
0 0 1
0 1 0
1 0 0
1 1 1

- Program
 - Waveform

vii) NOT gate ( INVERTER )

- Truth Table

Inputs Outputs
A C
0 1
1 0

- Program
- Waveform