Ninevah University

College of Electronics Engineering

Microprocessors II
Lecture 1
Memory and Input/Output Interfaces
Lecturer
Dr. Faris S. Alghareb
PhD in Computer Engineering
University of Central Florida
Copyright © 2020 Faris S. Alghareb. All rights reserved.
 Grading Information
v Quizzes / Homework / Attendance / Class participation & assignments

10% (plus 5% is bonus, take advantage of this opportunity)

v Midterm Exam 25%

v Lab reports/ Lab examination 15%

v Final Semester Exam 50%

35% theory 15% practical

based on what will based on lab
be given in lectures, programming
classwork, and assignments and lab
homework reports

SCE3313 Microprocessors II : 8086 microprocessor hardware interfacing Slide I

 Required textbooks

Required textbook:

“The 8088 and 8086 Microprocessors, Programming, Interfacing, Software,

Hardware and Applications” Fourth Edition. By: Walter A. Triebel

Recommended textbooks:

“The Intel Microprocessors, Architecture, programming and interfacing” Eighth

Edition. BY: Barry B. Brey

“Computer Organization and Design: The Hardware/Software Interface” By David

Patterson & John Hennessy, Fifth Edition (2014), Morgan Kaufmann, ISBN: 978-0-
12-407726-3.

SCE3313 Microprocessors II : 8086 microprocessor hardware interfacing Slide II

 8088/8086 Microprocessors
and their Memory and I/O Interfaces
In the previous course (Microprocessor I), we have studied the 8088/8086
microprocessors from a software point of view and covered the followings:
Software Architecture of the 8088/8086 microprocessors
Instruction Set Architecture (ISA)
Debug programming in assembly language

In this course (Microprocessor II), we will be covering and examining the

8088/8086 microprocessor from the hardware point of view. Herein, we cover
the followings (including but not limited to):
The 8088/8086’s signals interface
Memory interfaces
Input/output interfaces

SCE3313 Microprocessors II : 8086 microprocessor hardware interfacing Slide 1

 8088/8086 Microprocessors
and their Memory and I/O Interfaces

20 bits 16 bits

MPU
8086 Memory I/O
1 Mbyte devices
(1M x 8 bits) (64 Kbyte)

Data Bus (16-bit)

Control Bus
RD / WR
ALE (address latch enable)
M / IO
Ready, HALD, INTA
SCE3313 Microprocessors II : 8086 microprocessor hardware interfacing Slide 2
 8088/8086 Microprocessors
and their Memory and I/O Interfaces
The 8086 microprocessor was the first 16-bit microprocessor announced by
Intel Corporation in 1978, following by 8088 in 1979 that has the same
software architecture; however, its hardware different as it can execute only
an 8-bit instruction width (data bus width).

◆ both devices (8088 and 8086) can access and address 1Mbyte of
memory via 20-bit address bus.
◆ able to address up to 64K of 1 byte-wide Input/Output (I/O) ports.
◆ their internal circuitry has approximately 29,000 transistors.
◆ 40-pin for input and output ports.
◆ 5 volt for power supply voltage Vcc

Both 8088 and 8086 can be configured to work to either of two modes:

v Minimum-mode ⎼ MN/MX = 1
These modes allow the 8086 MPU to meet the
v Maximum-mode ⎼ MN/MX = 0 needs of wide variety of system requirements.

SCE3313 Microprocessors II : 8086 memory and I/O address spaces Slide 3

 Minimum and Maximum Mode systems
Minimum Mode:
Min-mode is selected by applying logic ‘1’ to the MN/MX signal. In this mode,
the system is smaller and contains a single microprocessor.

Maximum Mode:
Max-mode is selected by applying logic ‘0’ to the MN/MX signal. This mode is
activated to work in larger systems with multiple processors.

Based on the mode of operation (Min or Max), the assignments or function of

some of the 40 pins (pin functions) on the microprocessor package are
changed.

The three tables in next slides show the common and different signals
between the Min and Max mode of system operation.

SCE3313 Microprocessors II : 8086 minimum and maximum mode systems Slide 4

 8086 Microprocessor Layout Pin
The 29,000 transistors are housed in a 40-pin dual in-line package. The common
signals between the two types of modes are listed in table I below.

Table I: Signals common to both Minimum and Maximum modes.

Figure 1: Pin layout of the 8086 microprocessor. (Intel

Corporation, © 1979)

SCE3313 Microprocessors II : 8086 MPU pin diagram Slide 5

 Minimum-mode Interface

Vcc = 5 volt = Logic ‘1’

Figure 2: Block diagram of the minimum-mode 8086 MPU

SCE3313 Microprocessors II : 8086 minimum mode system Slide 6

 Minimum Mode System
Minimum-mode interface signals:
In this mode, the 8086 MPU provides all control signals needed to implement the
memory and I/O interfaces.
These control signals can be grouped into the following types: address/data bus,
status, control, interrupt, and Direct Memory Access (DMA).

Table II: Unique minimum-mode signals. Table III: Unique maximum-mode signals.

SCE3313 Microprocessors II : 8086 minimum mode system Slide 7

 Signals of Address and Data Bus of 8086 MPU
◆ Address/Data Bus
address bus bits are used to carry address information
to the MEM and I/O ports.
address bus is 20-bit long (A0 - A19) Multiplexed address/data bus lines
- A0: Least Significant Bit (LSB) AD0 – AD15
- A19: Most Significant Bit (MSB) A0
M AD0
20 bits give ability to address 1Mbyte memory address D0 U
X
space sel0
only 16-bit is used when dealing and serving an I/O A1
M AD1
port, which provides an independent I/O address space D1 U
X
of 64Kbytes in length. sel1

D0 – D15 and A0 – A15 lines are multiplexed. Thus, they .. ..

. .
denoted as AD0 through AD15 A15
M AD15
- when acting as data bus, they carry read/write data D 15
U
X
for memory, and sel15

- I/O data for input/output devices.

SCE3313 Microprocessors II : 8086 minimum-mode address/data bus signals Slide 8

 Status Signals (S6 through S3)
◆ Status signals
S6 through S3 bits represent the status signals
S3 – S4 together form 2-binary code that is used to identify which of the internal
registers was used to generate the PA
PA then sent on the address bus to select the output during the current bus
cycle.
S6 through S4 are also multiplexed with A19 through A16 and denoted as A16/S3 –
A19/S6

S4 S3 Address Status
0 0 Alternate (relative to the ES segment)
0 1 Stack (relative to the SS segment)
1 0 Code/none (relative to the CS segment or a
default of zero)
1 1 Data (relative to the DS segment)

SCE3313 Microprocessors II : 8086 minimum-mode status signals Slide 9

 Control Signals (1/2)
◆ Control signals
these signals are required to support the memory and I/O interfaces of the
8088/8086 microprocessor.
they are used to control functions, such as
- when a valid address is carried on bus
- which direction data are transferred over the bus
- when to put read data from MEM or from an I/O port on the bus, and
- when a valid write data are on the bus

For example, address latch enable (ALE) signal sets to logic ‘1’ (ALE = ‘1’) to indicate
there is a valid address on the address bus.

M / 𝐈𝐎 (Memory / IO) signal: to indicate if the address on the address bus goes
to the MEM (in case of logic ‘1’) or to an I/O port (logic ‘0’).
𝐃𝐄𝐍 (data enable) signal: used to enable the data bus

SCE3313 Microprocessors II : 8086 minimum-mode control signals Slide 10

 Control Signals (2/2)
DT/ 𝐑 (data transmit/receive) line: is used to specify which direction data are to
be transferred over the data bus.
- DT/ 𝐑 = logic ‘1’, indicates that data are either written into MEM or output to
an I/O device (monitor, printer, etc.)
- DT/ 𝐑 = logic ‘0’, this corresponds to reading data from memory or input of
data from an input device (keyboard, scanner, etc.)

𝐑𝐃 read signal: indicates that the MPU is performing a read of data off the bus
𝐖𝐑 write signal: set to logic ‘0’, indicates performing write data or output data
on the bus, thus a write bus cycle is in progress
During all MEM read/write operations 𝐃𝐄𝐍 (data enable) control signal is set to
logic ‘0’ to enable the data bus

READY signal: is used to insert wait states into the bus cycle. It can be
supplied by the memory or I/O subsystem to tell the 8086 when they are ready
to allow the data transfer to be completed.
SCE3313 Microprocessors II : 8086 minimum-mode control signals Slide 11
 Interrupt and DMA Interface Signals
◆ Control signals
INTR (Interrupt request): used by an external device to signal/inform the MPU that it
needs to be serviced, logic ‘1’ represents active interrupt request
𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) signal: the microprocessor sets INTA to logic ‘0’ as a
response to the INTR to serve the request
𝐓𝐄𝐒𝐓 line: when it is set to logic ‘1’ the MPU enters the ideal state and no longer
executes instructions. It can be used to synchronize MPU to an event in external
hardware
NMI (nonmaskable interrupt): this type of interrupt request has the highest priority
that cannot be masked by software
RESET signal: is used to provide and perform a hardware reset for the microprocessor.
◆ DMA interface signals
Direct Memory Access (DMA) interface signal consists of two signals HOLD & HLDA
These signals used by an external device when it needs to take control of the system
bus, thus the device signals the HOLD to logic ‘1’ so the MPU enters HOLD state
Hold acknowledge (HLDA) sets to logic ‘1’ by the MPU to indicate that it is in the
hold state.
SCE3313 Microprocessors II : 8086 minimum-mode interrupt signals Slide 12
 Maximum-mode Interface Signals
Maximum-mode interface signals:
In this mode, the 8086 MPU implements a multiprocessor (coprocessor) system
environment. This means that multiple microprocessors involve in the system and
each one executes its own program.

Some system resources are common to all processors and these resources are called
global resources
Local or private resources, on the other hand, are assigned to specific processors.

8288 Bus Controller:

This chip is used to control the control signals of the maximum mode interface. As
show in figure 3 in next slide, the 3-bit but status code S2 S1 and S0 used as inputs of
the 8288 bus controller to produce/output a status code on the bus, so that identifying
which type of the bus cycle will be to follow.

The 8288 decodes these 3-bit (S2 S1 and S0) lines to identify the type of the
MPU bus cycle.
The 8288 produces one or two command signals for each bus cycle

SCE3313 Microprocessors II : 8086 maximum-mode system (8288 bus controller) Slide 13

 8288 Bus Controller
MRDC : memory read command
MWTC : memory write command
AMWC : advanced memory write command
IORC : I/O read command
IOWC : I/O write command
AIOWC : advanced I/O write command
INTA : interrupt acknowledge

Connected these signals provide the same functions

to GND as those in the minimum-mode system
(logic ‘0’)
environment

Figure 3: Maximum-mode block diagram and control signals

For instance, when the 8086 MPU outputs the code S2 S1 S0 = 001 on the bus command
status code, it indicates that an I/O read cycle is to be performed/executed.
S2 S1 S0 =111, this means no bus activity is running or taking place.
SCE3313 Microprocessors II : 8086 maximum-mode system (8288 bus controller) Slide 14
 8288 Bus Controller
Example – Bus command status code
✏ Giving that an 8086 Intel Corporation MPU is operating in the maximum-mode, and
the bus status code equals 101, as shown in the table below. Then what type of bus
activity is taking place? Which command output is produced by the 8288 bus
controller chip?
Status Inputs 8288
CPU Cycle
𝐒𝟐 𝐒𝟏 𝐒𝟎 Command

0 0 0 Interrupt Acknowledge INTA

0 0 1 Read I/O Port IORC
0 1 0 Write I/O Port IOWC , AIOWC
0 1 1 Halt None
1 0 0 Instruction Fetch MRCD
1 0 1 Read Memory MRCD
1 1 0 Write Memory MWTC , AMWC
1 1 1 Passive None

Ans: Based on the giving status inputs for S2 S1 S0 = 101, we see that the bus status code
identifies Read Memory bus cycle. And the MEM Read Command (MRCD) is produced on the
bus controller circuitry which is activated by setting it to logic ‘0’.
SCE3313 Microprocessors II : 8086 maximum-mode system (8288 bus controller) Slide 15
 Minimum-mode I/O Bus Cycle (1/2)
Input bus cycle of the 8086
v Reading data from an I/O port
v 𝐑𝐃 = logic ‘0’ to indicate valid data are on the bus
ONE BUS CYCLE
T1 T2 T3 T4
CLK
Address is active during T1 Status will be active from T2 – T4
A19/S6 – A16/S3 and A19 – A16 , 𝐁𝐇𝐄 STATUS (S7 – S7) Time
𝐁𝐇𝐄 /S7 Demultiplexing
Address bus Bus reserved for data from T2 – T4
address, data,
AD15 – AD0 A15 – A0 D15 – D0 ( IN )
and status bus

ALE

M / IO

𝐑𝐃

DT/𝐑

𝐃𝐄𝐍
T1 T2 T3 T4
SCE3313 Microprocessors II : 8086 maximum-mode system (8288 bus controller) Slide 16
 Minimum-mode I/O Bus Cycle (2/2)
Output bus cycle of the 8086
v Writing data to an I/O port
v 𝐖𝐑 = logic ‘0’ to signal (tell) the I/O system that valid data are on the bus
ONE BUS CYCLE
T1 T2 T3 T4

CLK
Address is active during T1 Status will be active from T2 – T4
A19/S6 – A16/S3 and A19 – A16 , 𝐁𝐇𝐄 STATUS (S7 – S7)
𝐁𝐇𝐄 /S7
Address bus Bus reserved for data from T2 – T4
AD15 – AD0 A15 – A0 D15 – D0 (DATA OUT)

ALE

M / IO

𝐖𝐑

DT/R
T1 T2 T3 T4
𝐃𝐄𝐍
SCE3313 Microprocessors II : 8086 maximum-mode system (8288 bus controller) Slide 17