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DDR / Ddr1 Sdram Memory

DDR/DDR1 SDRAM was an early development of SDRAM that improved performance by transferring data twice per clock cycle, on both the rising and falling edge. This doubled the data rate and became widely adopted. It worked by very tightly controlling timing to transfer data at almost twice the rate of SDRAM. While it provided a speed boost, it also consumed more power with more open rows and banks in operation. DDR1 SDRAM was later superseded by DDR2 SDRAM.

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66 views3 pages

DDR / Ddr1 Sdram Memory

DDR/DDR1 SDRAM was an early development of SDRAM that improved performance by transferring data twice per clock cycle, on both the rising and falling edge. This doubled the data rate and became widely adopted. It worked by very tightly controlling timing to transfer data at almost twice the rate of SDRAM. While it provided a speed boost, it also consumed more power with more open rows and banks in operation. DDR1 SDRAM was later superseded by DDR2 SDRAM.

Uploaded by

Neha Upadhyay Mehta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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DDR / DDR1 SDRAM Memory

DDR SDRAM, also called DDR1 SDRAM is a form of


semiconductor memory - it as popular when first introduced by has
now been supeseeded.

SDRAM Memory Tutorial Includes:


What is SDRAM memory     SDRAM architecture     SDRAM timing & control     DDR / DDR1
SDRAM     DDR2 SDRAM     DDR3 SDRAM     DDR4 SDRAM     JEDEC 79 Standard    

Return to: Memory types & technologies    

DDR or as it was sometimes called DDR1 SDRAM was a development of the first SDRAM memory
technology to improve its performance.

The initials DDR stand for Double Data Rate and as such it gave a significant increase in the speed
of operation of the previous generation of SDRAM technology at the time of its introduction.

DDR SDRAM / DDR1 SDRAM was the first incarnation of this technology and it achieved its speed
increase by transferring data by transferring data twice per cycle, i.e. on both the rising and then the
falling edge of the clock signal.

As a result of its speed improvement, DDR / DDR1 SDRAM was quickly adopted and single data
rate, SDRAM soon became obsolete.

DDR SDRAM / DDR1 SDRAM basics


DDR SDRAM utilises techniques including very tight timing controls to increase the data transfer
rates by almost a fact of two.

The very tight timing requirements often require the use of phase locked loops and self-calibration
techniques to ensure the timing is sufficiently accurate.

The key to the operation is that the DDR SDRAM is able to transfer data on both the rising as well as
the falling edges of the clock pulse. This has many advantages, not only increasing the data rate, but
also reducing other problems such as the signal integrity requirements. At these speeds, signal
integrity can become a significant issue, and maximising the data transfer rate for a given clock rate
provides improvements in this area.
DDR SDRAM DATA RATES AND CLOCK SPEEDS
DDR SDRAM TYPE DATA RATE MEMORY CLOCK SPEED
MB/S/PIN (MHZ)
DDR-266 266 133
DDR-333 333 166
DDR-400 400 200
DDR SDRAMs access multiple memory locations in a single read or write command.

A memory read operation entails sending an "Activate" command followed by a "Read" command.

The memory has a certain latency after which the data is available - the memory provides a burst of
data from two, four, or eight memory locations at a rate of two memory locations per clock cycle. It is
therefore possible to read four memory locations in two consecutive clock cycles.

DDR SDRAM banks & arrays


DDR SDRAM memory has multiple banks within the memory. This enables the memory to provide
multiple interleaved memory access, and this enables the overall memory bandwidth to be
increased. A bank of memory is equal to an array or memory.

These banks can be addressed separately, and to accommodate this memory addressing is
required. As this is done in binary notation, four DDR SDRAM memory banks require two lines for
addressing: BA0 & BA1.

To provide an example of how DDR SDRAM operates in banks, a four bank DDR SDRAM may
operate as follows:

 An activate command opens a row in the first SDRAM bank.


 A second Activate command activates a row in the second bank.
 Read or Write commands can be sent to columns in the rows in banks one and two where
the rows are open.
 A Precharge command is sent once the read or write operations are complete. This closes
the row and bank areas open.
 The memory is ready for the next Activate command.

DDR / DDR1 SDRAM power


While DDR SDRAM provides an improvement in speed, this comes at a cost of the power
dissipated.

The power required by a DDR / DDR1 SDRAM is related to the number of rows that are open at any
one time. Thus to gain the fastest operation, it is necessary to open a number of rows together, but
this consumes more power. For low power operation, only one row should be open at any one time
in each bank, and there should also not be multiple banks each with open rows.
DDR / DDR1 SDRAM gave significant improvements in performance at the time. However it was
superseded by the next generation of SDRAM known as DDR2 SDRAM.

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