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Mod8 Test Bench

This document defines an entity called simulacion for simulation purposes. It declares a component called principal with clock, reset, and 3-bit output ports. It generates a clock signal and resets the principal component, then waits. The principal component is instantiated with the appropriate port mappings.

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Jair Tinta
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36 views

Mod8 Test Bench

This document defines an entity called simulacion for simulation purposes. It declares a component called principal with clock, reset, and 3-bit output ports. It generates a clock signal and resets the principal component, then waits. The principal component is instantiated with the appropriate port mappings.

Uploaded by

Jair Tinta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY simulacion IS
END simulacion;

ARCHITECTURE behavior OF simulacion IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT principal
PORT(
clk : IN std_logic;
reset : IN std_logic;
numero : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';

--Outputs
signal numero : std_logic_vector(2 downto 0);

-- Clock period definitions


constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: principal PORT MAP (
clk => clk,
reset => reset,
numero => numero
);

-- Clock process definitions


clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.

reset <= '1';


wait for 0.00001 ns;
reset <= '0';

wait;
end process;

END;

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