Scribd
Upload
1K views7 pages

Lect.-4-CMOS Process Enhancement

The document discusses enhancements to CMOS processes including adding multiple levels of metal and polysilicon to improve routability and provide on-chip resistors and capacitors. It describes how multiple metal layers improve power distribution and ease signal routing. Local interconnects using silicide can reduce area by connecting polysilicon and diffusion without using contacts and metal. The goals of CMOS enhancements are to provide on-chip capacitors, resistors, and routing of interconnects by using techniques like multiple metal and polysilicon layers.

Uploaded by

Karan Singh Panwar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
1K views7 pages

Lect.-4-CMOS Process Enhancement

The document discusses enhancements to CMOS processes including adding multiple levels of metal and polysilicon to improve routability and provide on-chip resistors and capacitors. It describes how multiple metal layers improve power distribution and ease signal routing. Local interconnects using silicide can reduce area by connecting polysilicon and diffusion without using contacts and metal. The goals of CMOS enhancements are to provide on-chip capacitors, resistors, and routing of interconnects by using techniques like multiple metal and polysilicon layers.

Uploaded by

Karan Singh Panwar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 7

Lecture-4/Unit-V

CMOS Process Enhancement

CMOS Process Enhancement –Enhancement to increase routability of circuits,


provides high-quality capacitor, or provides resistors of variable characteristics.
These enhancements include :

• Multiple levels of metal (more than five levels).

• Double or triple-level poly.

• Combinations of the above.

1) Interconnect
• More levels of metal improve the power and clock distribution to modules and
ease the signal routability.

Metal Interconnect

• If planarization is employed, the second level metal pitch can be the same as the
first. However, if the vertical topology becomes more varied, the width and
spacing of metal has to increase to prevent the metal from breaking.

• Contacting the second-layer metal to the first-layer metal is achieved by via as


shown in Figure 1 and a number of contact geometries are shown in Figure 2.
Fig.1

• No restrictions on the placement of the via with respect to underlying layers


(Figure 2(a)).

• Placement of via inside (Figure 2 (b)) or outside (Figure 2 (c)) the underlying
polysilicon or diffusion areas.

• Stacking of vias on top of contacts (Figure 2 (d)).


Fig.2

The steps for a two-metal process

• The oxide below the first-metal layer is deposited by atmospheric chemical vapor
deposition (CVD).

• The second oxide layer between the two metal layers is applied in a similar
manner.

• Removal of the oxide by a plasma etcher.

Polysilicon/Refractory Metal Interconnect

A doped-polysilicon with sheet resistance ranged from 20 to 40 Ω/square can also


be used as interconnect layer.

To further reduce the resistance of polysilicon, a refractory metal can be coated


upon the polysilicon without extra mask with the following three approaches.
• As shown in Figure 3(a), a silicide (e.g., silicon and tantalum) is used as
gate material. Sheet resistances of the order of 1 to 5 Ω/square may be obtained.
This is called the silicide gate approach.

• Figure 3 (b) uses a sandwich of silicide upon polysilicon, which is


commonly called the polycide approach.

• The approach presented in Figure 3 (a) & (b) can be applied to the
formation of source and drain region using the salicide process (Self Aligned
SILICLDE) (Figure 3(c)). An increasing trend is to use the salicide approach.

Fig. 3

Local Interconnect

The silicide (eg., TiN) itself may be used as a “local interconnect” layer for
connection within logic cells.

Local interconnect allows a direct connection between polysilicon and diffusion,


thus reducing the need for area-intensive contacts and metal.

Figure 4 shows a portion of a six transistor SRAM Cell that uses local
interconnect. Thus, area is reduced by 25%.
Fig.4
CMOS Process Enhancements:
In the Analog, Digital or RF CMOS integrated circuits along with transistors other
elements such as interconnects, resistors, capacitors are to be integrated on chip.
In order to achieve this, enhancements in CMOS process technology is required.
The main goals of adding CMOS enhancements are :

(1) To provide on chip capacitors for analog circuits.

(2) To provide on chip resistors.

(3) To provide routing of interconnects.

The enhancements in CMOS technology are :

(1) Multilevel metal layers.

(2) Multilevel poly layers.

Transistors :

To enhance the CMOS technology the bipolar transistors can be integrated on chip
in CMOS technology and this forms the BiCMOS technology. Here we will discuss
the processing requirements to make these devices on chip.

Figure below shows the cross-section of BiCMOS process in which NMOS and npn
transistor are fabricated on the same substrate.

The starting material is p substrate on which n type epitaxial layer is grown. To


form the NMOS transistor a p well is diffused in selected area. And n + diffusions
form the source and drain contacts. The nepilar is diffused with the p + diffusion
which forms the base for the npn transistor both the devices i.e. NMOS and npn
transistors are isolated by field oxide.

You might also like