2016

IC Manufacturing Process

Sudha
 Manufacturing Process of Integrated Circuits(IC)
Integrated Circuits:
It is also called as Chip or Microchip. The active and passive components such as
resistors, inductors, capacitors, transistors and external connections are made in a single chip of
silicon. All circuit components and interconnections are formed on single thin wafer (substrate)
is called Monolithic IC.
Steps in IC Fabrication:

1. Silicon Preparation:
Silicon is commonly used for manufacturing semiconductor materials. Silicon in pure
form is not available in nature. It will be available as either Silicon-di-oxide(SiO2 ) or Silicate.
Common forms of silicon dioxide are quartzite, quartz, rock crystal, amethyst, agate, flint, jasper,
and opal.
1.1 Purification of Quartzite-Creation of polysilicon:
Silicon for semiconductor applications is taken from quartzite. The purification
process of quartzite involves reaction with Carbon material at 20000 C. It produces
Metallurgic Grade Silicon (MGS) which is 98% pure. Silicon is reacted with HCL to
form a new liquid called trichlorosilane. Remove impurities by fractional distillation.
The liquid is converted to polycrystalline electronic grade silicon (EGS) by the
Siemens' process. The Siemens' process changes the liquid into a solid polycrystalline
silicon
 Fig 1.1 Polysilicon creation

1.2 Czochralski Crystal Growing-Preparation of silicon ingot:

This Step converts the very pure silicon from a polysilicon crystal form into a
single crystal or monocrystalline form. It can be called as Cz process.

The Polysilicon is placed in a pure Quartz crucible along with dopant materials to
make P or N-type. Argon gas is applied and heated to 14200C , melting point of silicon. A
previously loaded monocrystalline silicon "seed" of the desired crystal orientation is
lowered into the molten silicon and then slowly withdrawn as the "seed" and crucible
rotate in opposite directions.
This process causes the molten silicon to freeze out onto the "seed" crystal,
forming a monocrystalline Silicon ingot. The dopant species added to the polysilicon
material determines the crystal's electrical characteristics. The silicon ingot is evaluated
for both electrical and mechanical parameters.
 Figure 1.2 Czochralski Crystal grower
2. Wafer Production:

The next sequence of process steps involves sawing the ingot into the individual
wafers and grinding the outer edge to form a desired shape. The wafer is double sided
polished and chemically etched for smooth surface. The wafers are packed in clean
environment and ready for fabrication process.
 Figure 1.3 Sawing of Silicon Ingot

Figure 1.4 Wafer Preparation

3. Epitaxial Growth
The term epitaxial means build upon. It is the deposition of a layer of
single-crystal silicon on a single-crystal wafer
4. Dielectric Formation:
Dielectric materials are poor conductor of electricity. They are used for:

 Insulation between different conducting layers

 To protect surface of completed die
 To mask surface of wafers
 between Capacitors plates

The various types of formation of Sio2 layer are mentioned below

a) Thermally Grown Silicon Dioxide:

Silicon react with oxygen in the air at room temperature to form a very
thin layer of silicon dioxide . This layer will be 20 to 30Å thick. The process
of reacting the silicon wafer with some source of oxygen is referred to as
thermal oxidation

Figure 1.5 SiO2 Growth

b) Chemical Vapour Deposition (CVD):

The process reactions bring about a chemical decomposition of certain elements

or compounds by using heat, light, pressure/vacuum, and/or plasma energy to form a
stable solid. CVD-deposited oxides are used at several different places in the
manufacturing sequence. The following lists some of the more common uses.
1. To increase oxide thickness of thermal oxides

2. Capacitor dielectric

3. Dielectric over polysilicon Basic Integrated Circuit Manufacturing

4. Dielectric over metal

5. Buffer oxide layer to match mechanical requirements

6. Masking oxide layer

7. Final passivation

Figure 1.6 Block Diagram of CVD system

5. Photolithography:
The wafer is covered with a layer of light-sensitive material called
photoresist, which is then selectively exposed to light.

5.1 Masking:
The geometric images created by a circuit designer to a photosensitive
film applied to the surface of the silicon wafer as a mask. The exposed photoresist
is etched, washed away, and the remaining unexposed photoresist is hardened by
baking.
 Figure 1.7 Photolithography using Positive photoresist
Positive Resist:
An alkaline developer solution will react only with the exposed resist
Negative Resist:
Xylene is the common developer for negative resist. Only the unexposed resist is
dissolved and washed away.

6. Etching:
It removes material selectively from the surface of wafer to create
patterns. The pattern is defined by etching mask. The parts of material are
protected by this etching mask. Either wet (chemical) or dry (physical) etching
can be used to remove the unmasked material.
 Figure 1.8 Etching
7. Photoresist Removal:
At the completion of the etching process, the photoresist is removed. The pattern
has now transferred from the mask or reticle into the resist and from the resist into
the layer below the resist
8. Junction Formation:
Formation of junction is done by solid-state diffusion or ion implantation.
a. Diffusion:
In this method p and n regions are created by adding dopants into the wafer.
The wafers are placed in an oven which is made up of quartz and it is surrounded
with heating elements. Then the wafers are heated at a temperature of about 1500-
2200°F. The inert gas carries the dopant chemical. The dopant and gas is passed
through the wafers and finally the dopant will get deposited on the wafer. This
method can only be used for large areas. For small areas it will be difficult and it
may not be accurate.
 Figure 1.9 Diffusion
b. Ion Implantation:
Ion implantation is a low-temperature technique. Dopant gas such as
phosphine or boron trichloride will be ionized first. Then it provides a beam of
high energy dopant ions to the specified regions of wafer. It will penetrate the
wafer. The depth of the penetration depends on the energy of the beam. By
altering the beam energy, it is possible to control the depth of penetration of
dopants into the wafer. The beam current and time of exposure is used to control
the amount of dopant.

Figure 2.0 Configuration of Ion Implanter

9. Metallization:
It is used to create contact with silicon and to make interconnections on chip. A
thin layer of aluminum is deposited over the whole wafer. Aluminium is selected
because it is a good conductor, has good mechanical bond with silicon, forms low
resistance contact and it can be applied and patterned with single deposition and
etching process.

Figure 2.1 Metallization process sequence

10. Making Successive Layers:

The process such as masking, etching, doping will be repeated for each successive
layers until all integrated chips are completed. Between the components, silicon
dioxide is used as insulator. To avoid damage and contamination of circuit, final
dielectric layer is deposited.
11. Assembly & Packaging:
The assembly or packaging process will place the electrically good
devices in a package, interconnect the device to the package's leads and provide
some form of final sealing.
Each of the wafers contains hundreds of chips. These chips are separated
and packaged by a method called scribing and cleaving. A diamond saw cut the
wafer into single chips (die). The good chip is then mounted into a package. Thin
wire is connected using ultrasonic bonding. It is then encapsulated for protection.

Figure 2.2 IC Assembly sequence

There are three configurations available for packaging. They are metal can
package, ceramic flat package and dual in line package. For military applications,
the chip is assembled in ceramic packages. The complete integrated circuits are
sealed in anti-static plastic bags.