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JK FF Counter

1) The document describes the truth tables and K-map minimization for a JK flip-flop circuit with inputs J, K and a clock QT. 2) It shows that the minimized output equations for the Q output on the next clock (QT+1) and each input are: QT+1 = C, JA = BC(A' + A) = BC, KA = C, JB = A'C, KB = C, JC = 1. 3) A link is provided to download a Multisim simulation file to test the JK flip-flop circuit.

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77 views1 page

JK FF Counter

1) The document describes the truth tables and K-map minimization for a JK flip-flop circuit with inputs J, K and a clock QT. 2) It shows that the minimized output equations for the Q output on the next clock (QT+1) and each input are: QT+1 = C, JA = BC(A' + A) = BC, KA = C, JB = A'C, KB = C, JC = 1. 3) A link is provided to download a Multisim simulation file to test the JK flip-flop circuit.

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Output Input

No
QT QT+1 J K
1 0 0 0 X
2 0 1 1 X
3 1 0 X 1
4 1 1 X 0
Eksintansi JK FF

Tabel kebenaran JK FF K-MAP JA


Output FF A FF B FF C A/BC 00 01 11 10
Dec
QA QB QC JA KA JB KB JC KC 0 0 0 1 0
0 0 0 0 0 X 0 X 1 X 1 X X X X
1 0 0 1 0 X 1 X X 1 Maka JA =A'BC + ABC = BC(A' + A) = BC
2 0 1 0 0 X X 0 1 X
3 0 1 1 1 X X 1 X 1 K-MAP KA
4 1 0 0 X 0 0 X 1 X A/BC 00 01 11 10
5 1 0 1 X 1 0 X X 1 0 X X X X
0 0 0 0 1 0 1 X X
Maka KA = A'B'C + A'BC + AB'C + ABC = C
K-MAP JB K-MAP KB
A/BC 00 01 11 10 A/BC 00 01 11 10 K-MAP JC
0 0 1 X X 0 X X 1 0 A/BC 00 01 11 10
1 0 0 X X 1 X X X X 0 1 X X 1
Maka JB = A'B'C + A'BC = A'C Maka KB = A'B'C + A'BC + AB'C + ABC = C 1 1 X X X
Maka JC = A'B'C + A'B'C + A'BC + A'BC' + AB'C' + AB'C + ABC + ABC' = 1
K-MAP KC
A/BC 00 01 11 10
0 X 1 1 X
1 X 1 X X
Maka KC = A'B'C + A'B'C + A'BC + A'BC' + AB'C' + AB'C + ABC + ABC' = 1

Link Download file simulasi multisim : https://drive.google.com/file/d/1hExuD4MxDf7nb571lXJ1iKZxAXKdLgst/view?usp=sharing

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