Scribd
Upload
94 views7 pages

Verilog Code For SERIAL

The document contains Verilog code for a 4-bit serial shift register with an input, clock, reset and output. The code defines a module with always blocks that shift the data from one register to the next on each clock cycle when reset is low. A test bench is provided that applies inputs and resets to simulate the shift register behavior.

Uploaded by

Zulfiqar Ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
94 views7 pages

Verilog Code For SERIAL

The document contains Verilog code for a 4-bit serial shift register with an input, clock, reset and output. The code defines a module with always blocks that shift the data from one register to the next on each clock cycle when reset is low. A test bench is provided that applies inputs and resets to simulate the shift register behavior.

Uploaded by

Zulfiqar Ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 7

Verilog code for SERIAL-SHIFT REGISTER:

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 03:46:59 12/27/2020

// Design Name:

// Module Name: lab5

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module lab5(

input clk,

input reset,

input E,
output reg A

);

reg B,C,D;

always @ (posedge clk or posedge reset)

begin

if (reset)

begin

A <= 0;

B <= 0;

C <= 0;

D <= 0;

end

else

begin

A <= B;

B <= C;

C <= D;

D <= E;

end

end

endmodule

TEXT BENCH:

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:

// Engineer:

//

// Create Date: 03:55:02 12/27/2020

// Design Name: lab5

// Module Name: E:/xilinux based labs/lab5/LAB_5.v

// Project Name: lab5

// Target Device:

// Tool versions:

// Description:

//

// Verilog Test Fixture created by ISE for module: lab5

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

////////////////////////////////////////////////////////////////////////////////

module LAB_5;

reg clk;

reg reset;

reg E;
wire A;

lab5 uut (

.clk(clk),

.reset(reset),

.E(E),

.A(A)

);

integer i,j;

initial

begin

clk=0;

for(i=0;i<=40;i=i+1)

#10 clk=~clk;

end

initial

begin

$dumpfile("test.vcd");

$dumpvars(0,LAB_5);

E = 0; reset = 0;

#1 E = 0; reset = 1;

#1 reset = 0;

for(j=0;j<=10;j=j+1)

begin

#20 E=~E;

end
#20 E=1;

#20 E=0;

#20 E=1;

#20 E=0;

#20 E=1;

#20 E=0;

#20 E=1;

#20 E=1;

#20 E=0;

end

initial

begin

$monitor("clk=%b,E=%b,A=%b",clk,E,A);

end

endmodule

ISIM SIMULATION:

always @ (posedge clk or posedge reset)

if (reset)
out <= 0;

else begin

if (en)

case (srl)

0 : out <= {out[MSB-2:0], d};

1 : out <= {d, out[MSB-1:1]};

endcase

else

out <= out;

end

jkk

always #10 clk = ~clk;

initial begin

// Initialize Inputs

d <= 'h1;

clk <= 0;

en <= 0;

srl <= 0;

reset <= 0;

end

initial begin

reset<=0;

#20 reset<=1;

en <= 1;

repeat(7)@(posedge clk)
d <= ~d;

#10 srl<= 1;

repeat(7)@(posedge clk)

d <=~d;

repeat(7)@(posedge clk);

end

initial

$monitor("reset=%0b,en=%0b,d=%b,srl=%0b,out=%b",reset,en,d,srl,out);

You might also like