Features

• Serial Peripheral Interface (SPI) Compatible

• Supports SPI Modes 0 (0,0) and 3 (1,1)
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• 3.0 MHz Clock Rate (5V)
• 32-byte Page Mode
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
SPI Serial
•
•
Self-timed Write Cycle (5 ms Typical)
High-reliability
EEPROMs
– Endurance: One Million Write Cycles
– Data Retention: 100 Years 8K (1024 x 8)
• Automotive Grade Devices Available
• 8-lead PDIP, 8-lead JEDEC SOIC and 14-lead TSSOP Packages 16K (2048 x 8)
Description
32K (4096 x 8)
The AT25080/160/320/640 provides 8192/16384/32768/65536 bits of serial electri- 64K (8192 x 8)
cally-e ra sa ble pro gramma ble re ad on ly memo r y ( EEPROM ) or ga nize d a s
1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT25080/160/320/640 is available in space saving 8-lead PDIP, 8-
AT25080
lead JEDEC SOIC and 14-lead TSSOP packages.
The AT25080/160/320/640 is enabled through the Chip Select pin (CS) and accessed
AT25160
via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
AT25320
rate ERASE cycle is required before WRITE. AT25640

Pin Configuration 8-lead PDIP

Pin Name Function CS 1 8 VCC

SO 2 7 HOLD
CS Chip Select WP 3 6 SCK
GND 4 5 SI
SCK Serial Data Clock
SI Serial Data Input 8-lead SOIC
SO Serial Data Output CS 1 8 VCC
SO 2 7 HOLD
GND Ground
WP 3 6 SCK
VCC Power Supply GND 4 5 SI

WP Write Protect
14-lead TSSOP
HOLD Suspends Serial Input
CS 1 14 VCC
NC No Connect SO 2 13 HOLD
NC 3 12 NC
DC Don’t Connect NC 4 11 NC
NC 5 10 NC
WP 6 9 SCK
GND 7 8 SI
0675M–SEEPR–9/03

1
BLOCK WRITE protection is enabled by programming the status register with one of four blocks of write protection. Sepa-
rate program enable and program disable instructions are provided for additional data protection. Hardware data protection
is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to
suspend any serial communication without resetting the serial sequence.

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground .....................................-1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage .......................................... 6.25V conditions for extended periods may affect device
reliability.
DC Output Current........................................................ 5.0 mA

Block Diagram

2 AT25080/160/320/640
0675M–SEEPR–9/03
 AT25080/160/320/640

Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (SO) 8 pF VOUT = 0V
CIN Input Capacitance(CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V

Note: 1. This parameter is characterized and is not 100% tested.

DC Characteristics(1)
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V
(unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 3.6 V
VCC2 Supply Voltage 2.7 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5.0V at 1 MHz, SO = Open, Read 3.0 mA
VCC = 5.0V at 2 MHz, SO = Open,
ICC2 Supply Current 5.0 mA
Read, Write
ISB1 Standby Current VCC = 1.8V, CS = VCC 0.1 1.0 µA
ISB2 Standby Current VCC = 2.7V, CS = VCC 0.2 2.0 µA
ISB3 Standby Current VCC = 5.0V, CS = VCC 2.0 5.0 µA
IIL Input Leakage VIN = 0V to VCC -3.0 µA
IOL Output Leakage VIN = 0V to VCC, TAC = 0°C to 70°C -3.0 3.0 µA
(1)
VIL Input Low-voltage -0.6 VCC x 0.3 V
(1)
VIH Input High-voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low-voltage IOL = 3.0 mA 0.4 V
4.5V ≤ VCC ≤ 5.5V
VOH1 Output High-voltage IOH = -1.6 mA VCC - 0.8 V
VOL2 Output Low-voltage IOL = 0.15 mA 0.2 V
1.8V ≤ VCC ≤ 3.6V
VOH2 Output High-voltage IOH = -100 µA VCC - 0.2 V

Note: 1. VIL min and VIH max are reference only and are not tested.

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0675M–SEEPR–9/03
AC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
Symbol Parameter Voltage Min Max Units
4.5 - 5.5 0 3.0
fSCK SCK Clock Frequency 2.7 - 5.5 0 2.1 MHz
1.8 - 5.5 0 0.5
4.5 - 5.5 2
tRI Input Rise Time 2.7 - 5.5 2 µs
1.8 - 5.5 2
4.5 - 5.5 2
tFI Input Fall Time 2.7 - 5.5 2 µs
1.8 - 5.5 2
4.5 - 5.5 133
tWH SCK High Time 2.7 - 5.5 200 ns
1.8 - 5.5 800
4.5 - 5.5 133
tWL SCK Low Time 2.7 - 5.5 200 ns
1.8 - 5.5 800
4.5 - 5.5 250
tCS CS High Time 2.7 - 5.5 250 ns
1.8 - 5.5 1000
4.5 - 5.5 250
tCSS CS Setup Time 2.7 - 5.5 250 ns
1.8 - 5.5 1000
4.5 - 5.5 250
tCSH CS Hold Time 2.7 - 5.5 250 ns
1.8 - 5.5 1000
4.5 - 5.5 50
tSU Data In Setup Time 2.7 - 5.5 50 ns
1.8 - 5.5 100
4.5 - 5.5 50
tH Data In Hold Time 2.7 - 5.5 50 ns
1.8 - 5.5 100
4.5 - 5.5 100
tHD Hold Setup Time 2.7 - 5.5 100
1.8 - 5.5 400
4.5 - 5.5 200
tCD Hold Hold Time 2.7 - 5.5 200 ns
1.8 - 5.5 400
4.5 - 5.5 0 133
tV Output Valid 2.7 - 5.5 0 200 ns
1.8 - 5.5 0 800
4.5 - 5.5 0
tHO Output Hold Time 2.7 - 5.5 0 ns
1.8 - 5.5 0

4 AT25080/160/320/640
0675M–SEEPR–9/03
 AT25080/160/320/640
AC Characteristics (Continued)
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
Symbol Parameter Voltage Min Max Units
4.5 - 5.5 0 100
tLZ Hold to Output Low Z 2.7 - 5.5 0 100 ns
1.8 - 5.5 0 100
4.5 - 5.5 100
tHZ Hold to Output High Z 2.7 - 5.5 100 ns
1.8 - 5.5 100
4.5 - 5.5 250
tDIS Output Disable Time 2.7 - 5.5 250 ns
1.8 - 5.5 1000
4.5 - 5.5 5
tWC Write Cycle Time 2.7 - 5.5 10 ms
1.8 - 5.5 20
Endurance(1) 5.0V, 25°C, Page Mode 1M Write Cycles
Note: 1. This parameter is characterized and is not 100% tested.

5
0675M–SEEPR–9/03
Serial Interface MASTER: The device that generates the serial clock.
Description SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080/160/320/640
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25080/160/320/640 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25080/160/320/640, and the serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25080/160/320/640 is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO)
will remain in a high impedance state.
HO LD: The HOL D pin is use d in conjunctio n with th e CS pin to select th e
AT25080/160/320/640. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without resetting
the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low.
To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK
may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the
high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when
held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the sta-
tus register are inhibited. WP going low while CS is still low will interrupt a write to the status
register. If the internal write cycle has already been initiated, WP going low will have no effect
on any write operation to the status register. The WP pin function is blocked when the WPEN
bit in the status register is “0”. This will allow the user to install the AT25080/160/320/640 in a
system with the WP pin tied to ground and still be able to write to the status register. All WP
pin functions are enabled when the WPEN bit is set to “1”.

6 AT25080/160/320/640
0675M–SEEPR–9/03
 AT25080/160/320/640

SPI Serial Interface

7
0675M–SEEPR–9/03
Functional The AT25080/160/320/640 is designed to interface directly with the synchronous serial periph-
eral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
Description
The AT25080/160/320/640 utilizes an 8-bit instruction register. The list of instructions and their
operation codes are contained in Table 1. All instructions, addresses, and data are transferred
with the MSB first and start with a high-to-low CS transition.

Table 1. Instruction Set for the AT25080/160/320/640

Instruction Name Instruction Format Operation
WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Latch
RDSR 0000 X101 Read Status Register
WRSR 0000 X001 Write Status Register
READ 0000 X011 Read Data from Memory Array
WRITE 0000 X010 Write Data to Memory Array

WRITE ENABLE (WREN): The device will power-up in the write disable state when V CC is
applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the sta-
tus of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable status of the device can be deter-
mined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of
protection employed. These bits are set by using the WRSR instruction.

Table 2. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEN RDY

Table 3. Read Status Register Bit Definition

Bit Definition
Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is
Bit 0 (RDY)
in progress.
Bit 1= 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the
Bit 1 (WEN)
device is WRITE ENABLED.
Bit 2 (BP0) See Table 4 on page 9.
Bit 3 (BP1) See Table 4 on page 9.
Bits 4 - 6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 5 on page 9.
Bits 0 - 7 are 1s during an internal write cycle.

8 AT25080/160/320/640
0675M–SEEPR–9/03
 AT25080/160/320/640

WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25080/160/320/640 is divided into four array segments. One
quarter (1/4), one half (1/2), or all of the memory segments can be protected. Any of the data
within any selected segment will therefore be READ only. The block write protection levels and
corresponding status register control bits are shown in Table 4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g. WREN, tWC, RDSR).

Table 4. Block Write Protect Bits

Status
Register Bits Array Addresses Protected
Level BP1 BP0 AT25080 AT25160 AT25320 AT25640
0 0 0 None None None None
0300 0600 0C00 1800
1(1/4) 0 1
-03FF -07FF -0FFF -1FFF
0200 0400 0800 1000
2(1/2) 1 0
-03FF -07FF -0FFF -1FFF
0000 0000 0000 0000
3(All) 1 1
-03FF -07FF -0FFF -1FFF

The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,
writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-
protected sections in the memory array are disabled. Writes are only allowed to sections of the
memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as
long as the WP pin is held low.

Table 5. WPEN Operation

Protected Unprotected Status
WPEN WP WEN Blocks Blocks Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable

9
0675M–SEEPR–9/03
 READ SEQUENCE (READ): Reading the AT25080/160/320/640 via the SO (Serial Output)
pin requires the following sequence. After the CS line is pulled low to select a device, the
READ op-code is transmitted via the SI line followed by the byte address to be read (A15 - A0,
Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data (D7 - D0)
at the specified address is then shifted out onto the SO line. If only one byte is to be read, the
CS line should be driven high after the data comes out. The READ sequence can be contin-
ued since the byte address is automatically incremented and data will continue to be shifted
out. When the highest address is reached, the address counter will roll over to the lowest
address allowing the entire memory to be read in one continuous READ cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25080/160/320/640, two separate
instructions must be executed. First, the device must be write enabled via the Write Enable
(WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also, the address of
the memory location(s) to be programmed must be outside the protected address field location
selected by the Block Write Protection Level. During an internal write cycle, all commands will
be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to select the
device, the WRITE op-code is transmitted via the SI line followed by the byte address
(A15 - A0) and the data (D7 - D0) to be programmed (Refer to Table 6). Programming will start
after the CS pin is brought high. (The LOW-to-High transition of the CS pin must occur during
the SCK low-time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a READ STATUS
REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0, the
WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during
the WRITE programming cycle.
The AT25080/160/320/640 is capable of a 32-byte PAGE WRITE operation. After each byte of
data is received, the five low order address bits are internally incremented by one; the high
order bits of the address will remain constant. If more than 32 bytes of data are transmitted,
the address counter will roll over and the previously written data will be overwritten. The
AT25080/160/320/640 is automatically returned to the write disable state at the completion of
a WRITE cycle.
NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction
and will return to the standby state, when CS is brought high. A new CS falling edge is
required to re-initiate the serial communication.

Table 6. Address Key

Address AT25080 AT25160 AT25320 AT25640
AN A9 - A0 A10 - A0 A11 - A0 A12 - A0
Don't Care Bits A15 - A10 A15 - A11 A15 - A 12 A15 - A13

10 AT25080/160/320/640
0675M–SEEPR–9/03
 AT25080/160/320/640

Timing Diagrams
Synchronous Data Timing (for Mode 0)
t CS
VIH
CS
VIL
t CSS t CSH

VIH
SCK t WH t WL
VIL

t SU tH

VIH
SI VALID IN
VIL

tV t HO t DIS

VOH
SO HI-Z HI-Z

VOL

WREN Timing

WRDI Timing

11
0675M–SEEPR–9/03
RDSR Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK

SI INSTRUCTION

DATA OUT
HIGH IMPEDANCE
SO 7 6 5 4 3 2 1 0
MSB

WRSR Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK

DATA IN
SI INSTRUCTION 7 6 5 4 3 2 1 0

HIGH IMPEDANCE
SO

READ Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK

BYTE ADDRESS
SI INSTRUCTION 15 14 13 ... 3 2 1 0

DATA OUT
HIGH IMPEDANCE
SO 7 6 5 4 3 2 1 0
MSB

12 AT25080/160/320/640
0675M–SEEPR–9/03
 AT25080/160/320/640
WRITE Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK

BYTE ADDRESS DATA IN

SI INSTRUCTION 15 14 13 ... 3 2 1 0 7 6 5 4 3 2 1 0

SO HIGH IMPEDANCE

HOLD Timing

CS

tCD tCD

SCK

t HD

t HD
HO LD

t HZ

SO
t LZ

13
0675M–SEEPR–9/03
AT25080 Ordering Information
Ordering Code Package Operation Range
AT25080-10PI-2.7 8P3 Industrial
AT25080N-10SI-2.7 8S1 (-40°C to 85°C)
AT25080T1-10TI-2.7 14A2
AT25080-10PI-1.8 8P3 Industrial
AT25080N-10SI-1.8 8S1 (-40°C to 85°C)
AT25080T1-10TI-1.8 14A2
Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.

Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
14A2 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
-2.7 Low Voltage (2.7V to 5.5V)
-1.8 Low Voltage (1.8V to 5.5V)

14 AT25080/160/320/640
0675M–SEEPR–9/03
 AT25080/160/320/640

AT25160 Ordering Information

Ordering Code Package Operation Range
AT25160-10PI-2.7 8P3 Industrial
AT25160N-10SI-2.7 8S1 (-40°C to 85°C)
AT25160T1-10TI-2.7 14A2
AT25160-10PI-1.8 8P3 Industrial
AT25160N-10SI-1.8 8S1 (-40°C to 85°C)
AT25160T1-10TI-1.8 14A2
Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.

Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
14A2 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
-2.7 Low Voltage (2.7V to 5.5V)
-1.8 Low Voltage (1.8V to 5.5V)

15
0675M–SEEPR–9/03
AT25320 Ordering Information
Ordering Code Package Operation Range
AT25320-10PI-2.7 8P3 Industrial
AT25320N-10SI-2.7 8S1 (-40°C to 85°C)
AT25320T1-10TI-2.7 14A2
Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.

Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
14A2 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
-2.7 Low Voltage (2.7V to 5.5V)

16 AT25080/160/320/640
0675M–SEEPR–9/03
 AT25080/160/320/640

AT25640 Ordering Information

Ordering Code Package Operation Range
AT25640-10PI-2.7 8P3 Industrial
AT25640N-10SI-2.7 8S1 (-40°C to 85°C)
AT25640T1-10TI-2.7 14A2
AT25640-10PI-1.8 8P3 Industrial
AT25640N-10SI-1.8 8S1 (-40°C to 85°C)
AT25640T1-10TI-1.8 14A2
Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.

Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
14A2 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
-2.7 Low Voltage (2.7V to 5.5V)
-1.8 Low Voltage (1.8V to 5.5V)

17
0675M–SEEPR–9/03
Packaging Information

8P3 – PDIP

1
E

E1

Top View c
eA

End View

COMMON DIMENSIONS
D (Unit of Measure = inches)
e
D1 SYMBOL MIN NOM MAX NOTE
A2 A
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
b2 L D1 0.005 3
b3 E 0.300 0.310 0.325 4
4 PLCS b E1 0.240 0.250 0.280 3
e 0.100 BSC
Side View
eA 0.300 BSC 4
L 0.115 0.130 0.1

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8P3, 8-lead, 0.300" Wide Body, Plastic Dual
8P3 B
R San Jose, CA 95131 In-line Package (PDIP)

18 AT25080/160/320/640
0675M–SEEPR–9/03
 AT25080/160/320/640

8S1 – JEDEC SOIC

E E1

N L

∅
Top View
End View
e B
COMMON DIMENSIONS
A
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 A 1.35 – 1.75
A1 0.10 – 0.25
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
D
E1 3.81 – 3.99
E 5.79 – 6.20
Side View e 1.27 BSC
L 0.40 – 1.27
∅ 0˚ – 8˚

Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

10/7/03
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Colorado Springs, CO 80906 8S1 B
R
Small Outline (JEDEC SOIC)

19
0675M–SEEPR–9/03
14A2 – TSSOP

L1

E1
E

End View
e COMMON DIMENSIONS
(Unit of Measure = mm)

Top View SYMBOL MIN NOM MAX NOTE

D 4.90 5.00 5.10 2, 5
E 6.40 BSC
D
A A2 E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC

Side View L 0.45 0.60 0.75

L1 1.00 REF

Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AB-1, for
additional information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate
burrs shall not exceed 0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not
exceed 0.25 mm (0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total
in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower
radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H. 12/28/01

TITLE DRAWING NO. REV.

2325 Orchard Parkway 14A2,14-lead (4.4 x 5 mm Body), 0.65 Pitch,
San Jose, CA 95131 14A2 A
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