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CSE 425 Fall Midterm 2020 Assessment

This document contains the details of a mid-term exam for a computer science course, including instructions that unfair means will lead to expulsion. It lists two questions, the first with four parts on direct memory access controllers, microprocessor status flags, interrupt vector tables, and data transfer modes. The second question has three parts on memory interfacing techniques for a microprocessor system, including linear vs full decoding and address waste with linear decoding.

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Md.Rakibul Islam
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127 views1 page

CSE 425 Fall Midterm 2020 Assessment

This document contains the details of a mid-term exam for a computer science course, including instructions that unfair means will lead to expulsion. It lists two questions, the first with four parts on direct memory access controllers, microprocessor status flags, interrupt vector tables, and data transfer modes. The second question has three parts on memory interfacing techniques for a microprocessor system, including linear vs full decoding and address waste with linear decoding.

Uploaded by

Md.Rakibul Islam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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United International University (UIU)

Dept. of Computer Science & Engineering (CSE)


Mid-Term Exam::Trimester::Fall 2020
Course Code: CSE 425 Course Title: Microprocessor, Microcontroller and Interfacing
Sec: (A, B, C) Total Marks: 20 Duration: 1hr
Any examinee found adopting unfair means would be expelled from the trimester/ program as per UIU disciplinary rules.

Question 1: Answer all the questions. (12 Marks)

a. Draw detail block diagram of Direct memory access (DMA) controller interfacing with [2]
microprocessor 8086 showing different buses.

b. Explain the value of the Status flags of the 8086 microprocessor after executing [3]
the first and second instruction (shown below).
1st instruction: MOV AL, 0AAH
2nd instruction: ADD AL, 0BCH

c. Explain the purpose of the Interrupt Vector Table. Illustrate the contents of an [2+1
Interrupt vector and explain the purpose of each part in one or two sentences. +1]
Calculate the memory address for the INT FH in the interrupt vector table.

d. Why data transfer from external peripheral device to microprocessor using Burst [3]
mode is faster than Cycle stealing mode. Explain with sequence diagrams.

Question 2: Answer all the questions. (8 Marks)

a. You have to design a computer system, which has a 16-bit microprocessor with 20-bit [2.5+
address bus and 52 KB of memory. Currently available single RAM chip has 12-bit 1.5+
address bus and 16-bit data bus. You can use either Linear decoding 1]
technique or Full decoding technique (use optimum design) for
interfacing. Based on your preferred choice, answer the following questions.
 Explain the reason of your preference (decoding technique) to implement this design
and draw the diagram.
 Suppose there are n number of addresses in a RAM chip then write down the 2nd,
𝒏 𝟏
( 𝟐 )th and(n-2)th address for accessing 0th, 2nd and 5th RAM chip by the
microprocessor.
 What is the maximum memory capacity, which could be interfaced with the
microprocessor under this configuration using your preferred decoding technique?
(Show necessary calculation)

b. How Linear decoding memory interfacing technique wastes address space? [2+1]
Explain in three to four sentences with example.

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