Recent Results On Stream Ciphers
Recent Results On Stream Ciphers
Subhamoy Maitra
26 August, 2020
Procedure
Alice and Bob share a stream of random data (keystream) Ki ,
where i = 0, 1, . . .
The plaintext stream Mi is XOR-ed with Ki to generate the
cipher stream Ci . [Ci = Mi ⊕ Ki ]
The cipher stream Ci is XOR-ed with Ki to generate the
plaintext stream Mi . [Mi = Ci ⊕ Ki ]
Alice and Bob may sit on a table and toss an unbiased coin
enough number of times to generate the keystream bits.
Once some portion of the keystream is used for encryption, it
will never be used again.
Not practical!
A practical solution!
Secret key fixed with the device (Where is the key stored?)
Use secret key during PRGA
Cost of non-volatile memory less
Reduce size of volatile memory
L
L
- b5 b4 b3 b2 b1 b0-
L
L
- b6 b5 b4 b3 b2 b1- b0
X0 = S15H kS14L ;
X1 = S11H kS9H ;
X2 = S7L kS5H ;
X3 = S2L kS0H ;
F (X0 , X1 , X2 )
W = (X0 ⊕ R1 ) R2 ;
W1 = R1 X1 ;
W2 = R2 ⊕ X2 ;
R1 = S(L1 (W1L kW2H ));
R2 = S(L2 (W2L kW1H ));
The S-Box:
S is composed by 4 juxtaposed 8 × 8 S-boxes,
S = (S0 , S1 , S0 , S1 ).
For S0 , its nonlinearity, differential uniformity, algebraic degree
and algebraic immunity are 96, 8, 5 and 2 respectively.
Suboptimal: for easy hardware implementation.
For S1 , its nonlinearity, differential uniformity, algebraic degree
and algebraic immunity are 112, 4, 7 and 2 respectively.
1
Hk (M) → tag : Universal hash function with collision probability 2b
No space constraint
ARX strategy: Add, Rotate, XOR
Add is the only nonlinear operation
Very fast in any standard processor
Speed of KSA vs Speed of PRGA
Design Strategy:
Randomness is achieved by the secret key and swapping. The
secret key is used upto this stage, not after that.
Design Strategy:
Swap continues, one deterministic and one pseudorandom index.
Double indexing Z = S[S[i] + S[j]] provides the nonlinearity.
The eSTREAM portfolio has been revised and the portfolio now
contains the following ciphers:
Designed by Hongjun Wu
[Scaled down version of HC-256 (FSE 2004)]
Synchronous stream-cipher with 32-bit word output per step
A software stream cipher, available at
http://www.ecrypt.eu.org/stream/hcp3.html
128-bit secret key
The key and IV setup takes about 27,300 clock cycles
Encryption speed is 3.05 cycles/byte on Pentium M processor
No cryptanalytic result yet other than the claimed security
conjectures by the designer
Two tables P and Q, each with 512 many 32-bit elements are
used as internal states of HC-128.
A 128-bit key array K [0, . . . , 3] and a 128-bit initialization
vector IV [0, . . . , 3] are used, where each entry of the array is a
32-bit element.
st denotes the keystream word generated at the t-th step,
t = 0, 1, 2, . . ..
where x = x (3) kx (2) kx (1) kx (0) is a 32-bit word with four bytes:
x (0) (least significant) , x (1) , x (2) and x (3) (most significant)
The key and IV are expanded into an array W [0, . . . , 1279] as:
K [i] 0 ≤ i ≤ 7;
IV [i − 8] 8 ≤ i ≤ 15;
W [i] =
f2 (W [i − 2]) + W [i − 7]+
f1 (W [i − 15]) + W [i − 16] + i 16 ≤ i ≤ 1279
Run 1024 steps and use the outputs to replace the table elements:
P[i] = (P[i] + g1 (P[i 3], P[i 10], P[i 511])) ⊕ h1 (P[i 12])
for i = 0 to 511
Q[i] = (Q[i] + g2 (Q[i 3], Q[i 10], Q[i 511])) ⊕ h2 (Q[i 12])
for i = 0 to 511
i = 0;
repeat until enough keystream bits are generated {
j = i mod 512;
if (i mod 1024) < 512 {
P[j] = P[j] + g1 (P[j 3], P[j 10], P[j 511]);
si = h1 (P[j 12]) ⊕ P[j];
}
else {
Q[j] = Q[j] + g2 (Q[j 3], Q[j 10], Q[j 511]);
si = h2 (Q[j 12]) ⊕ Q[j];
}
end-if
i = i + 1;
}
end-repeat
x x1 x2 x3 c k k1 k2
0 0 0
x x5 x6 x7 k3 c1
v0 v1
4
X = = .
x8 x9 x10 x11
t0 t1 c2 k4
x12 x13 x14 x15 k5 k6 k7 c3
c0 = 0x61707865, c1 = 0x3320646e,
c2 = 0x79622d32, c3 = 0x6b206574,
256-bit key k0 , . . . , k7
64-bit nonce v0 , v1
64-bit counter t0 , t1
Since this is with 256-bit keys, we can refer it as 256-bit
Salsa20.
One can use the same cipher with 128-bit key, where
ki = ki+4 , for 0 ≤ i ≤ 3
c0 = 0x61707865, c1 = 0x3120646e,
c2 = 0x79622d36, c3 = 0x6b206574.
One may note the little differences in c1 , c2 for the 128-bit
and 256-bit version.
Z = X + X (R) .
Hardware vs Software
Hardware vs Hardware (towards less gates in implementation)
Software vs Software (How many bytes/clock?)
Frequency of modification in Key/IV: relates to cost of Key
Scheduling Algorithm, encrypting long/short key stream
Reversibility (if not collision, if yes TMDTO)
Proof of security vs statistical analysis of algorithms
Issues of National/International Standardization
Authenticated Encryption with Associated Data (AEAD)