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Embedded Systems Internal Test Paper

This document contains a test for an embedded systems course with 7 multiple choice and short answer questions. The test covers topics like scheduling algorithms, embedded system development models, I2C bus structure, simulators and emulators, interrupt service routine handling in real-time operating systems, firmware embedding techniques, and the phases of the embedded product development life cycle. The test is divided into two parts with questions 1-4 in Part A and questions 5-7 in Part B.

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Jikku Thomas
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102 views1 page

Embedded Systems Internal Test Paper

This document contains a test for an embedded systems course with 7 multiple choice and short answer questions. The test covers topics like scheduling algorithms, embedded system development models, I2C bus structure, simulators and emulators, interrupt service routine handling in real-time operating systems, firmware embedding techniques, and the phases of the embedded product development life cycle. The test is divided into two parts with questions 1-4 in Part A and questions 5-7 in Part B.

Uploaded by

Jikku Thomas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Name………………………… Roll No……………………..

] ST. JOSEPH’S COLLEGE OF ENGINEERING AND TECHNOLOGY, PALAI.


(An ISO 9001:2015 Certified College)
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
B. TECH DEGREE SECOND INTERNAL TEST- June 2020
EIGHTH SEMESTER-Batch A&B
CS404 – EMBEDDED SYSTEMS

Time: 2 Hours Max. Marks: 50

PART A

Answer all questions

No. Question Marks K level CO & KL

Three processes with process IDs P1, P2, P3 with estimated


completion time 6,8, 2 milliseconds respectively, enters the
ready queue together in the order. Process P4 with estimated
execution completion time 4 milliseconds enters the ready
1
queue after 1 millisecond. (Assuming there is no I/O waiting
5 K3
for the processes) in non-pre-emptive SJF scheduling CO5 & K3
algorithm. Calculate the waiting time for each process and
average waiting time?
2
Discuss the merits and demerits of Waterfall model for 5 K2 CO6 & K2
embedded system development.
3 Describe I2C bus structure and its transaction process. 5 K2 CO6 & K2

4 Write short notes on (i) Simulator (ii) Emulator 5 K2 CO4 & K3

PART B

Answer all questions

No. Question Marks K level CO & KL

5 Explain the three methods of ISRs handling in the RTOSs 10 K2 CO5 & K3
with example
6 Explain the different techniques for embedding the firmware K2 CO4 & K3
10
into the target board of an embedded system?
State the different phases of Embedded Product CO6 & K2
7 Development Life Cycle. Explain briefly the function of 10 K2
each phase

Staff-in-charge Stream Coordinator HoD

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