CPES Modeling and Control Tutorial COMPEL 2018
CPES Modeling and Control Tutorial COMPEL 2018
i i
Ig Io
+ 3V g +
Vg Vo Vo
-
-
- V g1 + Zg I g1
Ir Io
- V g2 + Zg I g2
i
+
Co Vo
- V g3 + Zg I g3 -
i1 i1 i2 i3
Active filters
i2 STATCOM
i3
HVDC transmission station
DC-AC grid-interface
Vac
I ac
I* - Vo
Reg. I Modul. PWM + -
+ V*
G* o
Reg. V
+
Circuit and control diagram Input current waveform
June 25, 2018 IEEE COMPEL 2018 6
Three-Phase Applications: Grid-Interface Converters
Photovoltaic applications
Energy Storage
?
Input Switching Output
Source Load
Filter network Filter
Controller
Feedforward Feedback
𝑣 𝑡 𝑖 𝑡
𝑣⃗ 𝑣 𝑡 𝚤⃗ 𝑖 𝑡
𝑣 𝑡 𝑖 𝑡
Euclid Space:
c
𝑣⃗
vc
b
1 0 0
𝑢 0 𝑢 1 𝑢 0 vb
0 0 1 a
va
a
June 25, 2018 IEEE COMPEL 2018 14
Transformation Matrix
The transformation matrix γ
|| T / abc || 1
b a
1 1
1
2 2 β
T / abc
2
0
3
3 c
3 2 2
1 1 1
2 2 2 α
𝑣⃗ 𝑇 / · 𝑣⃗
𝚤⃗ 𝑇 / · 𝚤⃗
ic
R 0 0
𝑑𝚤⃗ R 0 R 0
𝑣⃗ 𝐑𝚤⃗ 𝐋 0 0 R
𝑑𝑡 𝑖
𝚤⃗ 𝑖
𝑑𝚤⃗ L 0 0
𝑖
𝑑𝑡
𝐋 𝐑𝚤⃗ 𝐋 𝑣⃗ L 0 L 0
0 0 L
June 25, 2018 IEEE COMPEL 2018 16
Example: State-Space Equations
Vm
Im
ia cos(t ) R 2 2 L2
i I cos(t 120 )
b m L
ic cos(t 120 ) arctan
R
i 3 cos(t )
i Im
2 sin(t )
id 3 cos
i Im
q 2 sin
q
v vd cos sin v
d v v
q sin cos
vq vd
t
v ( )d ( 0 )
0
Therefore
cos sin 0
|| Tdq0 / αβγ || 1
Tdq0 / sin cos 0
1
0 0 1 Tαβγ / dq0 T
dq0 / TT
dq0 /
𝑑𝚤⃗ 0 𝜔𝐿 𝑖 𝑑𝚤⃗
𝑣⃗ 𝐑𝚤⃗ 𝐋 𝑣⃗ 𝐑𝚤⃗ 𝑖
𝑑𝑡 𝜔𝐿 0 𝑑𝑡
𝑑𝚤⃗ 𝑑𝚤⃗
lim 0 lim 0
→ 𝑑𝑡 → 𝑑𝑡
va Vm
vB
vb 3
vC C R
CSI/BUCK RECTIFIER DC VOLTAGE RANGE
Vdc Vm
vc 2
san sbn scn
n
L p
Current Source Inverter (CSI)
sap sbp scp
vdc vc
3
Vdc Vm vb Load
2 va
vA vB vC
san sbn scn
n C
June 25, 2018 IEEE COMPEL 2018 23
Method of Modeling Switching Networks
Current bi-directional two-quadrant switch Switching Function
v i
1, v = 0, if switch s is closed
i v s =
s
0, i = 0, if switch s is open
v
i
Switching Constraints
Voltage source or capacitor cannot be shorted
Current source or inductor cannot be open
p idc
Defining: 1
Voltage-unidirectional single- ia sa
ib va 0 1
pole-double-throw switch sb
vb 1 vdc
Switching functions ic 0 sc
vc 0
si sip 1 sin ; i {a, b, c}
n
June 25, 2018 IEEE COMPEL 2018 25
Current-Unidirectional Three-Phase Switching Network
Topology p
Three-phase terminals are voltage controlled vA sap sbp scp idc
va
DC port is current controlled vB
vb
Six current-unidirectional, voltage-bi- vC vc
directional, switches san sbn scn
n
Allowed switching combinations:
p
sak sbk sck 1; k { p, n} idc
vA
va
Two single-pole-triple-throw (SPTT) vB
vb
current-unidirectional switches vC vc
n
June 25, 2018 IEEE COMPEL 2018 26
Switching Model—Line Variables
Boost Rectifier/Voltage Source Inverter
p idc
ia 1
sa
ib va 0 1
sb
vb 1 vdc
ic 0 sc
vc 0
Note that: 𝑆 𝑆 𝑆
… ;… 𝑣 𝑣 𝑣 ;…
June 25, 2018 IEEE COMPEL 2018 27
Relationship between Line-to-Line Current and Phase Current
ia
iab 𝑖 𝑖 𝑖
ib
ica 𝑖 𝑖 𝑖
ibc 𝑖 𝑖 𝑖
ic
𝑖 𝑖 𝑖 𝑖 𝑖 𝑖 2𝑖 𝑖 𝑖 3𝑖
Assuming that 𝑖 𝑖 𝑖 0
1 1 1
𝑖 𝑖 𝑖 Similarly 𝑖 𝑖 𝑖 𝑖 𝑖 𝑖
3 3 3
𝑖 𝑆 𝑖 𝑆 𝑖 𝑆𝑖 𝑆 𝑖 𝑖 𝑆 𝑖 𝑖 𝑆 𝑖 𝑖
𝑖
𝑖 𝑖 𝑆 𝑆 𝑖 𝑆 𝑆 𝑖 𝑆 𝑆 𝑆 𝑆 𝑆 𝑖
June 25, 2018 IEEE COMPEL 2018
𝑖 28
Switching Model – Line Variables
Boost Rectifier / Voltage Source Inverter
p idc
ia 1
sa
ib va 0 1 𝑣 𝑆 ·𝑣
sb
vb 1 vdc
ic 0 sc
vc 𝑖 𝑆 ·𝑖
0
n
Where:
𝑣 𝑣 𝑣 𝑆 𝑆 𝑆 𝑖
𝑣 𝑣 𝑣 𝑣 𝑆 𝑆 𝑆 𝑆 𝑖 𝑖
𝑣 𝑣 𝑣 𝑆 𝑆 𝑆 𝑖
n
Where:
𝑣 𝑣 𝑆 𝑖
𝑣 𝑣 𝑣 𝑆 𝑆 𝑖 𝑖
𝑣 𝑣 𝑆 𝑖
d iL d vC
Linear components vR RiR vL L iC C
dt dt
𝑆⃗ ·𝑣 𝑆⃗ ·𝑣 𝑑⃗ ·𝑣
𝑆⃗ · 𝚤⃗ 𝑆⃗ · 𝚤⃗ 𝑑⃗ · 𝚤⃗
v AB
d ab vdc
ibc 3L vdc
vBC
d bc vdc C R
d ab iab d bc ibc d ca ica
ica 3L
vCA
d ca vdc
𝚤̅ 𝑣̅ 0 𝜔 0 𝚤̅ 𝑑
𝑑 1 1
𝚤̅ 𝑣̅ 𝜔 0 0 𝚤̅ 𝑑 · 𝑣̅
𝑑𝑡 𝚤̅ 3𝐿 𝑣̅ 3𝐿
0 0 0 𝚤̅ 𝑑 dq0 coordinates
𝚤̅
𝑑𝑣̅ 1 𝑣̅
𝑑 𝑑 𝑑 · 𝚤̅
𝑑𝑡 𝐶 𝚤̅ 𝑅𝐶
iq 3L vdc
3Lid
vq C R
dq vdc
dd id dq iq d0 i0
i0 3L
v0
d0 vdc
C R
iq 3L 3Lid dd id dq iq
vq
dq vdc
𝑑 𝚤̅ 1 𝑣̅ 0 𝜔 𝚤̅ 1 𝑑
· 𝑣̅
𝑑𝑡 𝚤̅ 3𝐿 𝑣̅ 𝜔 0 𝚤̅ 3𝐿 𝑑
dq coordinates
𝑑𝑣̅ 1 𝚤̅ 𝑣̅
𝑑 𝑑 · 𝚤̅
𝑑𝑡 𝐶 𝑅𝐶
June 25, 2018 IEEE COMPEL 2018 39
Equivalent Circuits in dq0 Frame
id idc L
Boost Rectifier
id 3L 3Liq
Buck Rectifier
vd vd vdc
d d vdc vdc dd idc dd vd
vpn
C R dq vq
iq 3L 3Lid d d id d q iq
iq C R
vq vq do vo
d q vdc
dq idc
id 3L vd L idc id
3Liq C vq vd
dd vdc C R d d vd R
idc C vq d d idc C
v pn
CSI
d q vq
VSI
vdc vdc
iq
dd id dq iq iq 3L d o vo C vd vq
3Lid vq
R
dq vdc C R d q idc C
C vd
𝑓⃗ 𝑋, 𝑈 ≡ 0 𝑥⃗ 𝑋 𝑥⃗ 𝑢 𝑈 𝑢 𝑥⃗ 𝑋 𝑥⃗ 𝑢 𝑈 𝑢
𝑑𝑋 𝑑𝑥⃗ 𝑑𝑋 𝑑𝑥⃗ 𝑑𝑥⃗
0
𝑑𝑡 𝑑𝑡 𝑑𝑡 𝑑𝑡 𝑑𝑡
𝑑𝑥⃗ 𝜕𝑓⃗ 𝑥⃗, 𝑢 𝜕𝑓⃗ 𝑥⃗, 𝑢
≅ · 𝑥⃗ ·𝑢
𝑑𝑡 𝜕𝑥⃗ , 𝜕𝑢 ,
𝑥⃗ 𝐀 · 𝑥⃗ 𝐁·𝑢
C R
iq 3L 3Lid
dd id dq iq
vq
dq vdc
𝑥⃗ 𝐀 𝑥⃗ 𝐁 𝑢 𝐃 𝑣⃗
~ 3L ~
id 3Liq
v~d Dd v~dc
~ v~dc
dd Vdc
C R
~ ~ ~ ~
Dq iq
dd I d Dd id dq I q
~ ~
iq 3L 3L id
Dq v~dc
v~q
~
dq Vdc
~ ~ K iddq ( s z iddq )
id K iddd ( s z iddd 1 ) ( s z iddd 2 ) id
~ ~
dd ( s p1 ) ( s p 2 ) ( s p 2* ) dq ( s p1 ) ( s p 2 ) ( s p 2* )
40
60
20
40
0
20
-20
0 -40
200 200
150
100
100
0
50
0 -100
-50 -200
1 10 100 1000 10000 100000 1 10 100 1000 10000 100000
600
400
200
Imaginary
0
-200
-400
-600
-800
-40 -35 -30 -25 -20 -15 -10 -5 0
Real
sTdel sTdel 2
1
e sTdel 2 12
sTdel sTdel 2
1
2 12
Often choose: Tdel Tc Td Tq Tsampling Tswitching Total digital delay 2 Tswitching
June 25, 2018 IEEE COMPEL 2018 50
Outline
1. Introduction
2. Mathematical Framework
3. Switching Modeling and PWM
4. Average Modeling
5. Small-Signal Modeling
6. Closed-Loop Control
7. 3-Level Converters
8. Control System Synchronization
9. AC System Interactions
10. Electronic Synchronous Machine (Voltage Controlling Converter)
June 25, 2018 IEEE COMPEL 2018 51
AC Sweep in Switching Model Simulation (PLECS)
d q _ ref tf iq _ dq iq
d d _ ref tf iq _ dd iq
d q _ ref tf id _ dq id
http://www.keysight.com/en/pdx-x201771-pn-E5061B/ena-series-network-analyzer?cc=GB&lc=eng
June 25, 2018 IEEE COMPEL 2018 53
Software Frequency Response Analyser Tool
https://pixabay.com/en/photos/laptop/
http://www.ti.com/tool/SFRA#3
https://www.youtube.com/watch?v=8z8PpZdYh7U
https://store.ti.com/LAUNCHXL-F28379D-C2000-Delfino-MCUs-F28379D-LaunchPad-Development-Kit-P50584.aspx?HQS=ecm-tistore-promo-janlaunchpad-
null-store-LAUNCHXL-F28379D-wwe
June 25, 2018 IEEE COMPEL 2018 54
Current Loop Design—Boost Rectifier
id 3L 3Liq
vd d d vdc
C R vdc
iq 3L 3Lid d d id d q iq
vq d q vdc
dd dq
id iq
Digital Control Interface
id d dref d qref
vref
Hv Hid
idref
iq
v’dc
iqref Hiq
60
Magnitude [dB]
50
40
30
20
10 ~
id K iddd ( s z iddd 1 ) ( s z iddd 2 )
~
( s p1 ) ( s p 2 ) ( s p 2* )
-100
dd
-150
Phase [°]
-200
-250
-300
0.1 1 10 100 1000 10000 100000
Frequency [Hz]
60
Magnitude [dB]
50
40
30
20
10
~ *
180 iq K iqdq ( s z iqdq ) ( s z iqdq )
~
160
dq ( s p1 ) ( s p 2 ) ( s p 2* )
Phase [°]
140
120
100
80
0.1 1 10 100 1000 10000 100000
Frequency [Hz]
60
Magnitude [dB]
40
20
-20
-50
-100
Phase [°]
-150
-200
-250
-300
-350
0.1 1 10 100 1000 10000 100000
Frequency [Hz]
D channel loop-gain
Bandwidth is limited by delay (fsw=20kHz)
June 25, 2018 IEEE COMPEL 2018 58
Current Loop Gain
100
80
Magnitude [dB]
60
40
20
-20
-50
-100
-150
Phase [°]
-200
-250
-300
-350
0.1 1 10 100 1000 10000 100000
Frequency [Hz]
Q channel loop-gain
Bandwidth is limited by delay (fsw=20kHz)
June 25, 2018 IEEE COMPEL 2018 59
Current Regulation
5 5
Magnitude [dB]
0 0
-5 -5
-10 -10
-15 -15
-20 -20
0.1 1 10 100 1000 10000 100000
0 0
-50
-100 -100
Phase [°]
-150
-200
-200
-250 -300
-300
-350 -400
0.1 1 10 100 1000 10000 100000 0.1 1 10 100 1000 10000 100000
Frequency [Hz] Frequency [Hz]
~ ~
id iq
~ ~
idref iqref
i’q 3L/v’dc
𝑑 𝑑 𝑒 𝑑 3𝜔𝐿𝑖 /𝑣 𝑒 𝑑 3𝜔𝐿 𝑒 𝑖
𝑑 𝑑 𝑒 𝑑 3𝜔𝐿𝑖 /𝑣 𝑒 𝑑 3𝜔𝐿 𝑒 𝑖
June 25, 2018 IEEE COMPEL 2018 61
Decoupled D and Q Channels
0
vdc sTd
3L d d vdc 3ωLiq d d vdc 3ωL e iq 3ωLiq
id
vdc
vd
dd vdc vdc
C R
iq 3L dd id dq iq
vq
dq vdc vdc sTq
d q vdc 3ωLid d q vdc 3ωL e id 3ωLid
vdc
0
Similar to two parallel dc-dc boost converters after d and q decoupled
June 25, 2018 IEEE COMPEL 2018 62
Output Voltage Loop Design
10
5
Magnitude [dB]
-5
-10
-15
v~dc
-20
K ( s z RHP )
Gc ~
(s p L ) (s p H )
0
idref
-50
Phase [°]
-100
-150
-200
0.1 1 10 100 1000 10000 100000
Frequency [Hz]
Ki Ki
D-Channel Loop-Gain H id Kp H iq K p
s s
June 25, 2018 IEEE COMPEL 2018 69
Current Regulation
~ ~
id iq
~ ~
idref iqref
June 25, 2018 IEEE COMPEL 2018 70
AC Voltage Loop
Lac Rac
Vdc Cdc
Cac
Filter Filter
Ki
H vd Kp
DSP
3ωL idref
+
+
abc PI
iqref
‐
dq s
dq PI
+
‐ abc Ki
‐
3ωL H vq Kp
idref
PI
vdref
+
‐
s
dq
vqref
iqref +
PI ‐ ‐
abc
v~d v~q
~ ~
idref iqref
June 25, 2018 IEEE COMPEL 2018 72
Improving Voltage Source
DQ-Frame Decoupled Controller for VSI
vdref idref dd
+ PI + - PI +
- - - -
ωC 3ωL
vd Vdc
id
iq 3ωL
vq
ωC Vdc
+
-
+
+ -
+
+ dq
vqref PI iqref PI
Magnitude
10
0
(dB)
-10
-20
Zdd with dec Zdq
180
Phase 90
(deg) 0
-90
-180
20 without dec Z Zqq
qd
Magnitude
10
(dB)
0
-10 with dec
-20
180
90
Phase
(deg)
0
-90
-180
102 103 104 10 2 10 3 104
Frequency (Hz)
June 25, 2018 IEEE COMPEL 2018 74
Software Frequency Response Analyzer—STATCOM
LOAD
SOURCE
STATCOM
Grid
PC
Pole introduced by
discharging resistor
𝚤̃ 𝚤̃
𝑑 𝚤̃
June 25, 2018 IEEE COMPEL 2018 79
Q-Axis Control-to-Current Loop-Gain
𝚤̃ 𝚤̃
𝑑 𝚤̃
June 25, 2018 IEEE COMPEL 2018 80
Outline
1. Introduction
2. Mathematical Framework
3. Switching Modeling and PWM
4. Average Modeling
5. Small-Signal Modeling
6. Closed-Loop Control
7. 3-Level Converters
8. Control System Synchronization
9. AC System Interactions
10. Electronic Synchronous Machine (Voltage Controlling Converter)
June 25, 2018 IEEE COMPEL 2018 81
Vienna (Type) Rectifier Topology Used
AC Boost Main Neutral
DC-Bus
Mains Inductors Bridge Point Switch
+vdc
Ia +Van +vp
va
vb vn
vc
+vn
2
V
I
an
a
1.5
1 1 1 0 1 1
0.5
1 1 1 0
-0 . 5
-1
1 1 0 0 1 0 1 1 0
1 0 1 0 0 - 1 1 0 1 -1 . 5
-2
-2 . 5
0 0 0
0 0 .0 0 5 0.01 0.015 0 .0 2 0.025 0.03
0 1 1 1 0 0
1 1 1 1 1 1
1 0 0 0 - 1 - 1
0 0 1
1
1 0 1 V
an Avg
0.4
0.2
1 1 1 0 1 1 1 1 1 0
-0.2
-0.4
-0.8
-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016
2
V
I
an
a
1.5
1 1 1 0 1 1
0.5
1 1 1 0
-0 . 5
-1
1 1 0 0 1 0 1 1 0
1 0 1 0 0 - 1 1 0 1 -1 . 5
-2
-2 . 5
0 0 0
0 0 .0 0 5 0. 0 1 0.015 0 .0 2 0.025 0.03
0 1 1 1 0 0
1 1 1 1 1 1
1 0 0 0 - 1 - 1
0 0 1
1
1 0 1 V
an Avg
0.4
0.2
1 1 1 0 1 1 1 1 1 0
-0.2
-0.4
-0.8
v p vn v p vn
vk 0 signik 1 S k
2 2
vk0
d R 1 1 v p vn v p vn 1
ik ik v sk signik 1 S k v0 n
dt L L L 2 2 L
d 1 1
dt
vp/n 1 S k ik 1 signik idc
2C k a ,b,c C
vk 0 S kp v p S kn vn
Assumption:
Switching functions Skp comply with topological restrictions
of Vienna-type rectifiers
d
dt
R 1 1
1
ik ik v sk S kp v p S kn vn v0 n
L L L L
d R 1 1
1
ik ik v sk d kp v p d kn vn v0 n
dt L L L L
d 1 1
d
dt
vp
1
C
1
S kp ik idc
C dt
vp d kp ik idc
C k a ,b , c C
k a ,b , c
d 1 1
d
dt
vn
1
1
S kn ik idc
C k a ,b , c C dt
vn
C d knik idc
k a ,b , c
C
June 25, 2018 IEEE COMPEL 2018 87
500
Vd
[V] / [A]
200 Id
100 Iq
0
-100
5 10 15 20 25 30
800
700
600 Vdc
[V]
500 Vp
400 Vn
300
5 10 15 20 25 30
Time [ms]
1
ddp
0.5 dqp
ddn
0 dqn
dt n C qp d qn iq C idc
-0.5
0 0.5 1 1.5 2 2.5
June 25, 2018 IEEE COMPEL 2018 Time [ms] 88
D & Q Axes Current-Control Loop-Gains
Bode Diagram I d/Idref 0 Bode Diagram I q/Iqref 0
From: I d ref To: I d From: Iq ref To: Iq I q/Iqref 10
I d/Idref 10
80 80
I d/Idref 20 I q/Iqref 20
60 60
I d/Idref 30 I q/Iqref 30
Magnitude (dB)
Magnitude (dB)
40 40
I d/Idref 40 I q/Iqref 40
20 20 I q/Iqref 50
I d/Idref 50
0 I d/Idref 60 0 I q/Iqref 60
-20 -20
-40 -40
360 180
0
180
Phase (deg)
Phase (deg)
-180
0
-360
-180 -540
1 2 3 4 5 1 2 3 4 5
10 10 Frequency
10 (Hz) 10 10 10 10 Frequency
10 (Hz) 10 10
𝚤̃ 𝚤̃
𝚤̃ 𝚤̃
June 25, 2018 IEEE COMPEL 2018 89
Neutral-Point Loop-Gain and Output Impedance
Bode Diagram V/ Vref 0 Bode Diagram Zdc 0
From: DVref To: DV From: Idc To: Vdc
V/ Vref 10 Zdc 30
40 20
V/ Vref 20 Zdc 60
20
V/ Vref 30 10 Zdc 90
Magnitude (dB)
Magnitude (dB)
0
V/ Vref 40 Zdc 120
-20 0
V/ Vref 50 Zdc 150
-40 V/ Vref 60 Zdc 180
-10
-60
-80 -20
360 90
270 45
Phase (deg)
Phase (deg)
180 0
90 -45
0 -90
-90 -135
0 1 2 3 4 1 2 3 4 5
10 10 Frequency
10 (Hz) 10 10 10 10 Frequency
10 (Hz) 10 10
∆𝑣 𝑣
𝑍
∆𝑣 𝚤̃
June 25, 2018 IEEE COMPEL 2018 90
Bode Diagram Ydq 0
AC Terminal Input Admittance From: Vd From: Vq
Ydq 30
0
Ydq 60
To: Id
-100 Ydq 90
Ydq 120
-200
0
Ydq 180
-720 𝚤̃
0 𝑌
𝑣
To: Iq
-100
-200
720
To: Iq
-720
2 3 4 5 2 3 4 5
10 10 10 Frequency
10 10 (Hz) 10 10 10
s
va vb vc ia ib ic
idc d dc
Tabcdq iqc d qc Tdqabc
v dc
PLL
Tabcdq v c
PI
q 1
s
PLL finds the angle of the voltage source, so that controller can control the
variables in correct dq frame
Controller commands need to be transferred back to abc frame with correct angle
June 25, 2018 IEEE COMPEL 2018 93
SRF-PLL
Synchronous D-Q Frame PLL q 1
vS
v S vSd 1 vsq 1
vSa
vSb
v Sc
T v S T
dq 1 v Sq 1
vsd 1
d 1
'
v S vSd 1
vSa v S d 1
' '
vSb
v Sc
T v S T
dq 1
v Sq 1 k p ki
vsd 1
q 1
' vsq 1
DSP line-to- ~ s
+ + phase transf
iL
SVM
- + + ~s
abc - iq
θ
dα dβ dq PLL
v~qs
dd id iq idref
θ αβ ~s
dq dq Controller iqref iq
Negative incremental resistance
in q channel!
June 25, 2018 IEEE COMPEL 2018 98
Inverter Impedance with PLL and Current Control
Magnitude
0
(dB)
-50
90
Zdd Zdq
Phase 0
(deg) -90
-180
40
s
20 Vd
Magnitude
s
0 Id
(dB)
Zout_il_PLL_50Hz
-20 Zqd Zout_il_PLL_100Hz
Zqq
Zout_il_PLL_200Hz
-40
90 400 Hz Line
0 Frequency
Phase
(deg)
-90
-180
100 10 2
10 100
4
102 104
Frequency (Hz)
June 25, 2018 IEEE COMPEL 2018 100
Outline
1. Introduction
2. Mathematical Framework
3. Switching Modeling and PWM
4. Average Modeling
5. Small-Signal Modeling
6. Closed-Loop Control
7. 3-Level Converters
8. Control System Synchronization
9. AC System Interactions
10. Electronic Synchronous Machine (Voltage Controlling Converter)
June 25, 2018 IEEE COMPEL 2018 101
Balanced Three-Phase AC System Small-Signal Stability Analysis
Impedance based small-signal analysis for AC system
250 v
sd
200
Votlage [V]
Votlage [V]
150
100
50
vsq
0
-500 0.01 0.02 0.03 0.04 0.05
Load 1 Time [sec]
…
like in DC systems
Zo Zi
Load n
POL MD
dc distr.
ωLSisq isd + vd s
Z dd s
id s
vsd vd id
vcd C ωCSvcq iq 0
S
-
RS LS vq s
isq + Z qd s
vsq
ωLSisd id s iq 0
vcq iq
CS ωCSvcd
- vq s
Z qq s
iq s id 0
vd s Z dd s Z dq s id s vd s
v s Z s Z s i s Z dq s
iq s
q qd qq q id 0
Characteristic Loci
4 1 ( j ) 2 ( j )
2
Imaginary
0
-2
Return ratio is:
-4
Z dds Z dqs Ydds Ydds
L ( s ) Z S s YL ( s )
Ydds
-1 0 2 4 6 8 10
Z qds Z qqs Ydds Real
L11 ( s ) L12 ( s )
Ls Eigenvalues of L(s) =
L ( s ) L ( s ) 𝟏 𝟐
21 22
June 25, 2018 IEEE COMPEL 2018 105
Balanced Three-Phase AC System Small-Signal Stability—
Generalized Nyquist Criterion
id
600
400
Return ratio is:
200 iq
Z dds Z dqs Ydds Ydds
L ( s ) Z S s YL ( s ) 0 0.1 0.2 0.3 0.4
Z qds Z qqs Ydds Ydds Time [s]
L11 ( s ) L12 ( s )
Ls Eigenvalues of L(s) =
L ( s ) L ( s ) 𝟏 𝟐
21 22
June 25, 2018 IEEE COMPEL 2018 106
Selected Types of System-Level Dynamic Interactions: Constant Power Load
Power hyperbola - Static
POL MD P ZSeq
dc distr.
Z Seq Z MD
dc Load
POL MD
dc distr. Incremental
Negative Resistor
in dd-impedance channel
dc Load
POL MD
dc distr.
PVC ESC
ZPVC
ac distr.
ac Load IBC El. Motor
dc Load
POL MD
dc distr.
PVC ESC
ac distr.
ac Load IBC El. Motor
68°
dc Load 31°
POL MD
dc distr.
DC 0
AC
PV Farm -40
5 10 15 20 25 30
Time [s]
June 25, 2018 IEEE COMPEL 2018 112
Outline
1. Introduction
2. Mathematical Framework
3. Switching Modeling and PWM
4. Average Modeling
5. Small-Signal Modeling
6. Closed-Loop Control
7. 3-Level Converters
8. Control System Synchronization
9. AC System Interactions
10. Electronic Synchronous Machine (Voltage Controlling Converter)
June 25, 2018 IEEE COMPEL 2018 113
Average Model of a Power Electronics Converter
- Voltage Source Converter (VSC)-
PV DC-DC Is
L
Power vdc C
Electronics
Converter vd
abc
vq
Modulation 1/s PI dq
θe
dd dq PLL
What is a relationship dq Transformation
id r s L
with a synchronous
+
-
machine model? + ωeLiq v
Idc dd vdc
vdc - d
Is d d id d q iq
G C iq rs L
+
-
+ dq vdc ωeLid v
Dynamic (average) - q
+
Tm
-
ω eψ q
kf J Te
r Q iQ iq rs
Mechanical
subsystem LQ Lq vq
ψq
+
-
June 25, 2018
Electrical subsystem ωeψd IEEE COMPEL 2018 115
Model of a Synchronous Generator - Salient-pole Rotor (Anisotropic) -
Boiler High-, Medium-, and Low-Pressure Turbines
d-axis
Total Moment of Inertia
valve
Tm J Stator
+
-
Ld ω L ivd Electrical
L+D
ψ'd Ω e γ q
vd subsystem can
e' e/p
Mech.input ΩΩ =Tω - be combined
ψd
+
TTmm
-
ψ'd id ψ'q iq ω eψ q and “coupled”
kkff J Te iq r s L γ to an electrical
r Q iQ iq rs
+
-
equivalent of
Mechanical
+ ψ' Ω
q
ω e L γ id v the mechanical
- q
subsystem LQ L q v q subsystem…
ψq
+
-
June 25, 2018
Electrical subsystem ωeψd IEEE COMPEL 2018 116
Supplementary slide
The machine equations can be rewritten into the following form, defining flux
derivatives per rotor position rather than time (the main reason for this reformatting is
to factor out the term dependent on the angular speed):
d d d e d d d
vd rs id e q rs id e q e rs id p ( d q )
d e dt d e d e
d q d e d q d q
vq rs iq e d rs iq e d e rs iq p( d )
d e dt d e d e
vd rs id d'
vq rs iq q'
Where:
d d
d' p q
d e
d q
p
'
d
q
d
e
June 25, 2018 IEEE COMPEL 2018 117
Supplementary slide
Furthermore, active power at the machine terminals comprises following
components: joules losses, rate of change of the energy accumulated in the
magnetic field, and mechanical power converted to electrical:
d d d q
Pdq (i i ) rs id
2
d
2
q iq e ( d iq q id ) (id2 iq2 ) rs P gap
dt dt
Assuming lossless electromechanical conversion from rotor to stator, all of the
power (except joules losses) is delivered from the rotor (Pgap). Lumping this power
into the form of an “equivalent” torque, it could be written:
1 d d
Pgap d q e
Te id iq ( d iq qid ) id d iq q
' ' '
dt dt
+
-
can now be applied
+ ψ'd Ω ω e L γi q v to a converter!
Ω Te' - r L d
id s γ
Tm ψ'd id ψ'q iq
+
Flux
Flux
-
Lγ ω L i Electrical
kf J + iψ q' r
Ω s e γ q relationships
relationships
subsystem can
Ω Te' d vd
+
-
- added…
beadded…
combined
Tm ψ'd id ψ'q iq + ψ' Ω ω e L γ id v and “coupled”
and pp
q q
……and
kf J ωωe e
- r
iq s L γ to an electrical
self-
self-synchronization
synchronization
+
-
equivalent of
θeθe + ψ' Ω idiωd eLγiidqiq
ωω
1/s
1/s q vq the mechanical
e eisispptimes
times -
higher
higherthan thanΩΩ
ψψ'd 'd ( s()s )LL( s()s ) i i GG( s()s ) vsubsystem…
dd dd dd v
FF
ψψ'q 'q vvFF
June 25, 2018
q (q s()s)LLq (q s()s ) iqiq IEEE COMPEL 2018 119
Electronic Synchronous Machine
DC-DC
Is L
PV Power vdc
Electronics
C
Converter
+
-
J Tm Te k f 1/K
dt K + dd vdc ωeLiq v
vdc Idc - d
Is d d id d q iq
G C iq r s L
+
-
dvdc + dq vdc ωeLid v
C I s I dc Gvdc - q
dt
id iq
However, for emulation of dd
the particular synchronous
vF
Desired machine dynamics
machine: dq
June 25, 2018 IEEE COMPEL 2018 120
Supplementary slide
-25
d ( s ) Ld ( s ) id G ( s ) vF -40
-45 Lq ( j ), Lq ( s )
Measured point-by-point*
q ( s ) Lq ( s ) iq Curve-fitted transfer function 30
0
Additionally, mechanical dynamics estimated from -30
two slow-down tests (in order to solve for kf and J ): 0
150 -80
100 Ω = pωe 45
0
50 Tm
-45
kf J Te -90
2 4 6 8 10
Time [s] 10-4 10-2 10 0 10 2
Frequency [Hz]
June 25, 2018 *IEEE guide for standstill frequency response (SSFR) testing - Std.115A-1987 IEEE COMPEL 2018 121
Virtual Inertia
DC-AC
600 µF L1=250 µH L2=250 µH LL RL ΔRL
DC
Power vdc
Supply Power
Electronics
vdc
actual Converter 35µF vab
2
+vbc
2
+vca
2
sw
C(s) Modulation - +
30 kW Voltage Source ∑ Vref
vdcdesired Tdq abc θe θe T
Hv
Converter (VSC) abc dq
1/K id i q vF
ωe dd dq desired
vdc ψd (s), ψq (s), L1, L2
RD I dc / Vdc (1 sRD C ) 1/s θe
C (s) vdc
actual
LL RL ΔRL
Motor Induction Synch.
Drive Motor Generator
vab
2
+vbc
2
+vca
2
sw
+
vF
-
- +
30 kW Synchronous
∑ Vref
Generator Hv
+ - + - +
J = 0.32 [kgꞏm2] vF
2
C(s) Modulation 2
Vo_ref
-
∑
Vo_ref ∑
vdcdesired T θe θe T
CJekv 80 mF Hv dq/abc abc/dq Hv
1/K id iq vF
ωe dd dq
vdcdesired ψd (s), ψq (s), L1, L2
Output Impedance plots 1/s θe v actual
dc
20 15
Zdd Zdq
Ph. [deg] Mag. [dB]
10
10
0
-10 5 ZoGen
90
45
180
ZoCon (600 µF)
0 150
ZoCon (Virtual Inertia)
20
Zqd Zqq
Ph. [deg] Mag. [dB]
5
0
-5
0 The same “machine-like”
-10 -20 dynamics seen from AC
135 90
90
side of power converter
45 0 achieved!
0
-90
10 0 10 2 10 0 10 2
June 25, 2018 Frequency [Hz] Frequency [Hz] IEEE COMPEL 2018 123
Experimental Demonstration of the Equivalence
20 20
idq [A]
idq [A]
16 16
Capacitance
12 equivalent to 12
240 machine inertia: 240
220 J = 0.32 [kgꞏm2] 220
vdq [V]
vdq [V]
200 200
180 Model Output 180 Model Output
160
Experiment Experiment
160
11 12 13 14 11.5 12 12.5 13 13.5 14 14.5
Time [s] C ekv
80 mF Time [s]
ωve dc[rad/s]
[rad/s]
Ωe [rad/s]
178
356 J 356
365
[V]
176
352 Compared to 352
360
174
348 348
C 600 F AC output frequency
ω
180
374 15 179