EECS 151/251A


Fall 2017

Digital Design and
Integrated Circuits
Instructors:
Weaver and Wawrzynek

Lecture 8

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 Administration
❑ Exam in One Week
❑ Take here in class and with an extra
30 minutes (5:30-7:30).
❑ Covers topics: beginning through 2/6.

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Overview of Physical Implementations
The stuff out of which we make systems.
❑ Integrated Circuits (ICs)
▪ Combinational logic circuits, memory elements, analog
interfaces.
❑ Printed Circuits (PC) boards
▪ substrate for ICs and interconnection, distribution of CLK,
Vdd, and GND signals, heat dissipation.
❑ Power Supplies
▪ Converts line AC voltage to regulated DC low voltage levels.
❑ Chassis (rack, card case, ...)
▪ holds boards, power supply, fans, provides physical
interface to user or other systems.
❑ Connectors and Cables.
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Printed Circuit Boards
❑ fiberglass or ceramic
❑ 1-25 conductive layers
❑ ~1-20in on a side

❑ IC packages are soldered down.

Multichip Modules (MCMs)

• Multiple chips directly connected to a substrate. (silicon, ceramic,
plastic, fiberglass) without chip packages.

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Integrated Circuits ❑ Primarily Crystalline Silicon
❑ 1mm - 25mm on a side
❑ 100 - 20B transistors
❑ (25 - 250M “logic gates”)
❑ 3 - 10 conductive layers
❑ 2018 state-of-the-art feature size
7nm = 0.007 x 10-6 m
❑ “CMOS” most common -
complementary metal oxide
semiconductor
Chip in Package
• Package provides:
– spreading of chip-level signal
paths to board-level
– heat dissipation.
• Ceramic or plastic with gold

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 From Gates to Circuits
❑ Digital abstraction
❑ CMOS abstraction
❑ Switch logic
❑ Transient properties

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 CMOS abstraction

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CMOS Devices
❑ MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

Top View
Cross-section View

The gate acts like a capacitor. A high voltage on the gate

attracts charge into the channel. If a voltage exists
between the source and drain a current will flow. In its
simplest approximation, the device acts like a switch.
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 CMOS Transistors – State-of-the-Art

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 MOS Transistor as a Switch

MOS Transistor A Switch!

G
|VGS| |VGS| ≥ |VT| R
on

S D S D

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 ON/OFF Switch Model of MOS Transistor

G
|VGS|

S D

Ron

S D S D
|VGS| < |VT| |VGS| ≥ |VT|

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 Drain versus Source - Definition

MOS transistors are symmetrical devices

(Source and drain are interchangeable)

Source is the node w/ the lowest voltage

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 A More Realistic Switch

G Transistors in the
|VGS| sub 100 nm age

S D

Ron
Roff
S D S D
|VGS| < |VT| |VGS| > |VT|

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 A Logic Perspective

NMOS Transistor
G
VGS > 0

S D
X Ron
Y Z
Y=Z if X=1

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 A Complementary Switch

X Ron
Y Z
Y=Z if X=0

PMOS Transistor
G
VGS < 0

S D

Source is the node w/ the highest voltage!

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 The CMOS Inverter: A First Glance

V DD

V in V out

CL

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The Switch Inverter

First-Order DC Analysis

V DD V DD

Rp VOL = 0
VOH = VDD
V out
V out VM = f(Rn, Rp)
Rn

V in = V DD V in = 0

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 Switch logic

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Static Logic Gate

▪ At every point in time (except during the switching transients)

each gate output is connected to either VDD or VSS via a low
resistive path.

▪ The output of the gate assumes at all times the value of the
Boolean function implemented by the circuit (ignoring, once
again, the transient effects during switching periods).


Example: CMOS Inverter

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 Building logic from switches

A B AND
Series X Y
Y = X if A AND B

A
OR
Parallel X Y
Y = X if A OR B
B
(output undefined if condition not true)

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Logic using inverting switches

A B NOR
Series X Y Y = X if A AND B

=A+B

A
NAND
Parallel Y = X if A OR B 

X Y
= AB
B

(output undefined if condition not true)

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 Static Complementary CMOS
VDD

In1
Inverting switches
…
In2 PUN
InN
F(In1,In2,…InN)
In1
…

In2 PDN Non-Inverting switches

InN

PUN and PDN are dual logic networks

PUN and PDN functions are complementary
Dual Graphs

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Complementary CMOS Logic Style

❑ PUN is the dual to PDN


(can be shown using DeMorgan’s Theorems)

A + B = AB
AB = A + B
❑ Static CMOS gates are always inverting

AND = NAND + INV

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Example Gate: NAND

❑ PDN: G = AB ⇒ Conduction to GND

❑ PUN: F = A + B = AB ⇒ Conduction to VDD
❑ G(In1,In2,In3,…) ≡ F(In1,In2,In3,…)

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Example Gate: NOR

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 Complex CMOS Gate
OUT = D + A • (B + C) OUT = D • A + B • C

B
A
C

D
OUT
A
D
B C

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 Non-inverting logic

VDD

In1
Non-Inverting switches
…

In2 PUN
InN Why is this
F(In1,In2,…InN)
a bad idea?
In1
Inverting switches
…

In2 PDN
InN

PUN and PDN are dual logic networks

PUN and PDN functions are complementary

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 Switch Limitations

VDD VDD
S Good 1 D Bad 1
VDD
0 → VDD
D S 0 → VDD - VTn
VGS
CL CL
VDD → 0 VDD → |VTp|
D VGS S
CL CL
VDD
S Good 0 D Bad 0

Tough luck …
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 Transmission Gate
❑ Transmission gates are the way to build “switches” in CMOS.
❑ In general, both transistor types are needed:
❑ nFET to pass zeros.
❑ pFET to pass ones.
❑ The transmission gate is bi-directional (unlike logic gates).

❑ Does not directly connect to Vdd and GND, but can be combined with
logic gates or buffers to simplify many logic structures.
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 Transmission-gate Multiplexor
s
2-to-1 multiplexor:
c = sa + s’b

Switches simplify the c

implementation:
s a
a
c
b
s’ Compare the cost to logic gate
implementation.
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 4-to-1 Transmission-gate Mux
❑ The series connection of pass-
transistors in each branch
effectively forms the AND of s1
and s0 (or their complement).

❑ Compare cost to logic gate

implementation

Any better solutions?

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 Alternative 4-to-1 Multiplexor
❑ This version has less
delay from in to out.

❑ In both versions, care

must be taken to avoid
turning on multiple paths
simultaneously (shorting
together the inputs).

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 Tri-state Buffers
Tri-state Buffer:

“high
impedance” (output
disconnected)

Variations:

transmission gate
Inverting buffer useful in
Inverted enable
implementation

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 Tri-state Buffers
=0
=0
1

=1
Tri-state buffers are used when
Tri-state buffers multiple circuits all connect to a
enable “bidirectional” common wire. Only one circuit at a
connections. time is allowed to drive the bus.
All others “disconnect” their
=1
0 outputs, but can “listen”. =0

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 Tri-state Based Multiplexor
Multiplexor
Transistor Circuit for inverting
multiplexor:

If s=1 then c=a else c=b

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 Latches and Flip-flops
Positive Level-sensitive latch:

Positive
LatchEdge-triggered flip-flop
Transistor Level:
built from two level-sensitive Latch Implementation:
latches:
clk’

clk’
clk

clk

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 Summary:

Complimentary CMOS Properties

❑ Full rail-to-rail swing

❑ Symmetrical VTC
❑ No (…) static power dissipation
❑ Direct path current during switching

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 Digital abstraction

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Noise and Digital Systems

❑ Circuit needs to works despite “analog” noise

▪ Digital gates can and must reject noise
▪ This is actually how digital systems are defined

❑ Digital system is one where:

▪ Discrete values mapped to analog levels and back
▪ Elements (gates) can reject noise
– For “small” amounts of noise, output noise is less than input
noise
▪ Thus, for sufficiently “small” noise, the system acts as if it
was noiseless
▪ This is called regeneration

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 Bridging the digital and the analog worlds

❑ How to represent 0’s and

1’s in a world that is analog?

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From MIT 6.012 Spring 2007, Lecture 11
Ideal Inverter

Ideal inverter returns well defined logical outputs (0 or V+) even in the
presence of considerable noise in VIN (from voltage spikes, crosstalk, etc.)

⇒ signal is regenerated! 41
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From MIT 6.012 Spring 2007, Lecture 11
 “Real Inverter”

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From MIT 6.012 Spring 2007, Lecture 11
 Valid Input Ranges

If range of output values VOL to VOH is wider than the range of

input values VIL to VIH, then the inverter exhibits some noise
immunity. (|Voltage gain| > 1)
Quantify this through noise margins.
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From MIT 6.012 Spring 2007, Lecture 11
Definition of Noise Margins

“1”
VOH Noise margin high:
NMH
Undefined VIH NMH = VOH – VIH
Region
NML VIL Noise margin low:
VOL NML = VIL – VOL
“0”
Gate Gate
Output Input
(Stage M) (Stage M+1)
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 Simulated Inverter VTC (Spice)

2.5
❑ VOH =
2
❑ VOL =
1.5 ❑ VIL =
V (V)

VIH =
out

1
❑

❑ NMH =
0.5

❑ NML =
0
0 0.5 1
V (V)
1.5 2 2.5
❑ VM =
in

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