5 4 3 2 1

JCPU1B
D R10;R11 put on U4 side D
R10
A28 CLK_CPU_DMI_R 0_0402_5% 1 2
C26 BCLK A27 1 2 CLK_CPU_DMI <15>
CLK_CPU_DMII#_R 0_0402_5%

MISC

CLOCKS
<19> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
R11
AN34
SKTOCC# A16 2 R12 1 1K_0402_5%
+V1.05S_VCCP DPLL_REF_CLK A15 2 R13 1 1K_0402_5%
DPLL_REF_CLK# +V1.05S_VCCP

T48 H_CATERR# AL33

CATERR#
R9 1
62_0402_5%

THERMAL
AN33 R8 H_DRAMRST#
<19,42> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
2

R15

DDR3
MISC
56_0402_5%
H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 2 R16 1 140_0402_1%
<42,48> H_PROCHOT# PROCHOT# SM_RCOMP[0] A5 SM_RCOMP1 2 R17 1 25.5_0402_1%
SM_RCOMP[1] A4 SM_RCOMP2 2 R18 1 200_0402_1%
SM_RCOMP[2]
AN32 DDR3 Compensation Signals
<19> H_THRMTRIP# THERMTRIP#

+V1.05S_VCCP
AP29 XDP_PRDY# T97
PRDY# AP27 XDP_PREQ# T98
PREQ# XDP_TMS R20 2 1 51_0402_5%
AR26 XDP_TCK XDP_TDI R21 2 1 51_0402_5% PU/PD for JTAG signals
C R22 TCK AR27 XDP_TMS XDP_TDO R23 2 @ 1 51_0402_5% C

PWR MANAGEMENT
TMS

JTAG & BPM

1 2 H_PM_SYNC_R AM34 AP30 XDP_TRST#
<16> H_PM_SYNC PM_SYNC TRST# 2 1 51_0402_5%
XDP_TCK R24
0_0402_5% AR28 XDP_TDI XDP_TRST# R25 2 1 51_0402_5%
TDI AP26 XDP_TDO
0_0402_5%
0_0402_5%1 R26 2 H_CPUPWRGD_R AP33 TDO
<19> H_CPUPWRGD UNCOREPWRGOOD
2

R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5%

DBR# +3VS
1 R27 1 2 PM_DRAM_PWRGD_R V8
@ C549 130_0402_5% SM_DRAMPWROK
10K_0402_5%
AT28 XDP_BPM#0 T49
100P_0402_50V8J BPM#[0] AR29 XDP_BPM#1 T90
1

2 BPM#[1] AR30 XDP_BPM#2 T91

EMI Reserve BUF_CPU_RST# AR33 BPM#[2] AT30 XDP_BPM#3 T92
RESET# BPM#[3] AP32 XDP_BPM#4 T93
BPM#[4] AR31 XDP_BPM#5 T94
BPM#[5] AT31 XDP_BPM#6 T95
BPM#[6] AR32 XDP_BPM#7 T96
BPM#[7]

TYCO_2013620-2_IVY BRIDGE
+3VALW

1 Buffered reset to CPU

C33
0.1U_0402_16V4Z
+1.5V_CPU_VDDQ
2 +3VS
B B
1

1 R880@ 2
<16> SYS_PWROK
0_0402_5% R30
U1 200_0402_5% +V1.05S_VCCP
1
C34
5

0.1U_0402_16V4Z
2

1 R161 2 1
P

+3VS B 2
10K_0402_5% 4 PM_SYS_PWRGD_BUF R32
2 O 75_0402_5%
<16> PM_DRAM_PWRGD A
G

5
1

74AHC1G09GW_TSSOP5 R34 U2
2
3

@ 43_0402_1% 1 3V

P
R33 BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC
39_0402_5% Y 2 PCH_PLTRST#
A PCH_PLTRST# <18>
1

G
SN74LVC1G07DCKR_SC70-5
1 2

3
D R35 @
2 Q1 @ 0_0402_5%
<10> RUN_ON_CPU1.5VS3#
G 2N7002H_SOT23-3
2

S
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

JCPU1C JCPU1D
<13> DDR_B_D[0..63]

AB6 AE2
<12> DDR_A_D[0..63] SA_CLK[0] AA6 M_CLK_DDR0 <12> SB_CLK[0] AD2 M_CLK_DDR2 <13>
C5 SA_CLK#[0] V9 M_CLK_DDR#0 <12> C9 SB_CLK#[0] R9 M_CLK_DDR#2 <13>
DDR_A_D0 DDR_B_D0
DDR_A_D1 D5 SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> DDR_B_D1 A7 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1
D DDR_A_D5 C6 SA_DQ[4] SA_CLK[1] AB5 M_CLK_DDR1 <12> DDR_B_D5 A8 SB_DQ[4] SB_CLK[1] AD1 M_CLK_DDR3 <13> D
DDR_A_D6 C2 SA_DQ[5] SA_CLK#[1] V10 M_CLK_DDR#1 <12> DDR_B_D6 D9 SB_DQ[5] SB_CLK#[1] R10 M_CLK_DDR#3 <13>
DDR_A_D7 C3 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> DDR_B_D7 D8 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13>
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] RSVD_TP[1] AA4 DDR_B_D11 G1 SB_DQ[10] RSVD_TP[11] AA2
DDR_A_D12 F9 SA_DQ[11] RSVD_TP[2] W9 DDR_B_D12 G5 SB_DQ[11] RSVD_TP[12] T9
DDR_A_D13 F7 SA_DQ[12] RSVD_TP[3] DDR_B_D13 F5 SB_DQ[12] RSVD_TP[13]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] RSVD_TP[4] AA3 DDR_B_D17 J8 SB_DQ[16] RSVD_TP[14] AB1
DDR_A_D18 K1 SA_DQ[17] RSVD_TP[5] W10 DDR_B_D18 K10 SB_DQ[17] RSVD_TP[15] T10
DDR_A_D19 J1 SA_DQ[18] RSVD_TP[6] DDR_B_D19 K9 SB_DQ[18] RSVD_TP[16]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
K2 SA_DQ[22] SA_CS#[0] AL3 DDR_CS0_DIMMA# <12> K7 SB_DQ[22] SB_CS#[0] AE3 DDR_CS2_DIMMB# <13>
DDR_A_D23 DDR_B_D23
DDR_A_D24 M8 SA_DQ[23] SA_CS#[1] AG1 DDR_CS1_DIMMA# <12> DDR_B_D24 M5 SB_DQ[23] SB_CS#[1] AD6 DDR_CS3_DIMMB# <13>
DDR_A_D25 N10 SA_DQ[24] RSVD_TP[7] AH1 DDR_B_D25 N4 SB_DQ[24] RSVD_TP[17] AE6
DDR_A_D26 N8 SA_DQ[25] RSVD_TP[8] DDR_B_D26 N2 SB_DQ[25] RSVD_TP[18]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
N9 SA_DQ[29] SA_ODT[0] AG3 M_ODT0 <12> M2 SB_DQ[29] SB_ODT[0] AD4 M_ODT2 <13>
DDR_A_D30 DDR_B_D30
M_ODT1 <12> M_ODT3 <13>

DDR SYSTEM MEMORY B

DDR_A_D31 M7 SA_DQ[30] SA_ODT[1] AG2 DDR_B_D31 M1 SB_DQ[30] SB_ODT[1] AD5

DDR SYSTEM MEMORY A

DDR_A_D32 AG6 SA_DQ[31] RSVD_TP[9] AH2 DDR_B_D32 AM5 SB_DQ[31] RSVD_TP[19] AE5
DDR_A_D33 AG5 SA_DQ[32] RSVD_TP[10] DDR_B_D33 AM6 SB_DQ[32] RSVD_TP[20]
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
C DDR_A_D37 AH6 SA_DQ[36] C4 DDR_A_DQS#0 DDR_A_DQS#[0..7] <12> DDR_B_D37 AN2 SB_DQ[36] D7 DDR_B_DQS#0 DDR_B_DQS#[0..7] <13> C
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D47 AL8 SA_DQ[46] DDR_B_D47 AR5 SB_DQ[46]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
DDR_A_D49 AN11 SA_DQ[48] D4 DDR_A_DQS0 DDR_A_DQS[0..7] <12> DDR_B_D49 AJ11 SB_DQ[48] C7 DDR_B_DQS0 DDR_B_DQS[0..7] <13>
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D58 AL15 SA_DQ[57] DDR_B_D58 AR14 SB_DQ[57]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
DDR_A_D60 AL14 SA_DQ[59] DDR_B_D60 AT12 SB_DQ[59]
DDR_A_D61 AK14 SA_DQ[60] AD10 DDR_A_MA0 DDR_A_MA[0..15] <12> DDR_B_D61 AN15 SB_DQ[60] AA8 DDR_B_MA0 DDR_B_MA[0..15] <13>
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
AE10 SA_MA[6] W6 DDR_A_MA7 AA9 SB_MA[6] R2 DDR_B_MA7
B <12> DDR_A_BS0 AF10 SA_BS[0] SA_MA[7] V1 DDR_A_MA8 <13> DDR_B_BS0 AA7 SB_BS[0] SB_MA[7] T5 DDR_B_MA8 B
<12> DDR_A_BS1 V6 SA_BS[1] SA_MA[8] W5 DDR_A_MA9 <13> DDR_B_BS1 R6 SB_BS[1] SB_MA[8] R3 DDR_B_MA9
<12> DDR_A_BS2 SA_BS[2] SA_MA[9] AD8 DDR_A_MA10 <13> DDR_B_BS2 SB_BS[2] SB_MA[9] AB7 DDR_B_MA10
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
<12> DDR_A_CAS# AD9 SA_CAS# SA_MA[13] V5 <13> DDR_B_CAS# AB8 SB_CAS# SB_MA[13] R5
DDR_A_MA14 DDR_B_MA14
<12> DDR_A_RAS# AF9 SA_RAS# SA_MA[14] V7 DDR_A_MA15 <13> DDR_B_RAS# AB9 SB_RAS# SB_MA[14] R4 DDR_B_MA15
<12> DDR_A_WE# SA_WE# SA_MA[15] <13> DDR_B_WE# SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

+1.5V

@ R36 1 2 DRAMRST_CNTRL
<15> DRAMRST_CNTRL_PCH DRAMRST_CNTRL <10>
1

0_0402_5%
1 2 R37 R40 0_0402_5%
1K_0402_5%

R38
2

1K_0402_5%
S

H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2
<6> H_DRAMRST# DDR3_DRAMRST# <12,13>
2

Q2
R39 LBSS138LT1G_SOT-23-3
G
2

4.99K_0402_1%
1

A A

DRAMRST_CNTRL

1
C35
Eiffel used 0.01u Security Classification Compal Secret Data Compal Electronics, Inc.
Module design used 0.047u Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title
.047U_0402_16V7K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/7) DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 7 of 60

5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

CFG2

1
R41
1K_0402_1%

2
D D

Interl request AH26 short GND

JCPU1E check on EVT phase PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

AH27 PAD T13 CFG2
AK28 VCC_DIE_SENSE AH26 1 2 socket pin map definition
AK29 CFG[0] VSS_DIE_SENSE
CFG2 AL26 CFG[1] R60 0_0402_5% 0:Lane Reversed
CFG4
CFG5
AL27
AK26
AL29
CFG[2]
CFG[3]
CFG[4] RSVD28
L7
AG7
* CFG4
CFG6 AL30 CFG[5] RSVD29 AE7
CFG[6] RSVD30

1
CFG7 AM31 AK2
AM32 CFG[7] RSVD31
AM30 CFG[8] W8 @ R42

CFG
AM28 CFG[9] RSVD32 1K_0402_1%
+VCC_GFXCORE_AXG AM26 CFG[10]

2
AN28 CFG[11] AT26
+VCC_CORE AN31 CFG[12] RSVD33 AM33
AN26 CFG[13] RSVD34 AJ27
CFG[14] RSVD35
2

AM27
R252 AK31 CFG[15]
AN29 CFG[16]
49.9_0402_1% CFG[17]
2

Display Port Presence Strap

R253
1

49.9_0402_1% T8
C RSVD37 J16 C
1 : Disabled; No Physical Display Port
VCC_AXG_VAL_SENSE AJ31 RSVD38 H16 CFG4 * attached to Embedded Display Port
1

R82 1 @ 2 100_0402_1% VSS_AXG_VAL_SENSE AH31 VAXG_VAL_SENSE RSVD39 G16

VCC_VAL_SENSE AJ33 VSSAXG_VAL_SENSE RSVD40
R88 1 2 100_0402_1% VSS_VAL_SENSE AH33 VCC_VAL_SENSE
@
VSS_VAL_SENSE 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
Need PWR add new circuit on 1.05V(refer CRB) AJ26 AR35
RSVD5 RSVD_NCTF1 AT34

RESERVED
RSVD_NCTF2 AT33
VSS_AXG_VAL_SENSE RSVD_NCTF3 AP35 CFG6
RSVD_NCTF4 AR34
RSVD_NCTF5 CFG5
VSS_VAL_SENSE

1
F25
Check F24 RSVD8
RSVD9
@ R43 @ R44
2

F23 1K_0402_1% 1K_0402_1%

R255 R257 D24 RSVD10 B34
G25 RSVD11 RSVD_NCTF6 A33
49.9_0402_1% 49.9_0402_1%

2
G24 RSVD12 RSVD_NCTF7 A34
E23 RSVD13 RSVD_NCTF8 B35
1

D23 RSVD14 RSVD_NCTF9 C35

C30 RSVD15 RSVD_NCTF10
A31 RSVD16
B30 RSVD17
B29 RSVD18
D30 RSVD19 AJ32
B31 RSVD20 RSVD51 AK32
INTEL 12/28 recommand RSVD21 RSVD52 PCIE Port Bifurcation Straps
A30
to add RC120, RC121, RC122, RC123 C29 RSVD22
RSVD23
Please place as close as JCPU1 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B J20
B18 RSVD24
BCLK_ITP
BCLK_ITP#
AN35
AM35 CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B

RSVD25 disabled
01: Reserved - (Device 1 function 1 disabled ; function
J15 AT2 2 enabled)
RSVD27 RSVD_NCTF11 AT1
RSVD_NCTF12 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AR1
RSVD_NCTF13

B1 CFG7
KEY

1
@R45
@ R45
1K_0402_1%

TYCO_2013620-2_IVY BRIDGE

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion

A
0: PEG Wait for BIOS for training A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/7) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 8 of 60
5 4 3 2 1
 5 4 3 2 1

JCPU1F POWER +V1.05S_VCCP

+VCC_CORE

EDS v1.5 QC=94A 8.5A

DC=53A
AG35
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
D AG31 VCC4 VCCIO3 AC10 D
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF34 VCC11 VCCIO10 J12
AF33 VCC12 VCCIO11 J11
AF32 VCC13 VCCIO12 H14
AF31 VCC14 VCCIO13 H12
AF30 VCC15 VCCIO14 H11
AF29 VCC16 VCCIO15 G14
AF28 VCC17 VCCIO16 G13
AF27 VCC18 VCCIO17 G12

PEG AND DDR

AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD34 VCC21 VCCIO20 F12
AD33 VCC22 VCCIO21 F11
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AD27 VCC28 VCCIO26 D13
AD26 VCC29 VCCIO27 D12
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
AC33 VCC32 VCCIO30 C13
AC32 VCC33 VCCIO31 C12
AC31 VCC34 VCCIO32 C11
AC30 VCC35 VCCIO33 B14
C AC29 VCC36 VCCIO34 B12 C
AC28 VCC37 VCCIO35 A14
AC27 VCC38 VCCIO36 A13
AC26 VCC39 VCCIO37 A12
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44 +V1.05S_VCCP
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
1
CORE SUPPLY

Y34 VCC51
Y33 VCC52 C99
Y32 VCC53 .1U_0402_16V7K
VCC54

1
Y31 2
Y30 VCC55 R46
Y29 VCC56
VCC57 75_0402_5%
Y28
Y27 VCC58
VR_SVID_CLK series-resistors close to VR

2
Y26 VCC59
V35 VCC60
V34 VCC61 AJ29 H_CPU_SVIDALRT# 1 R47 2 43_0402_1%
SVID

V33 VCC62 VIDALERT# AJ30 H_CPU_SVIDCLK 1 2 R48 VR_SVID_ALRT# <55>

0_0402_5%
V32 VCC63 VIDSCLK AJ28 1 2 R49 VR_SVID_CLK <55>
H_CPU_SVIDDAT 0_0402_5%
V31 VCC64 VIDSOUT VR_SVID_DAT <55>
V30 VCC65
V29 VCC66 2 1 130_0402_5%
VCC67
R50 +V1.05S_VCCP 0.1uF on power side
V28
B V27 VCC68 B
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
U27 VCC78
U26 VCC79
R35 VCC80 +VCC_CORE
R34 VCC81
R33 VCC82
VCC83

1
R32
R31
R30
VCC84
VCC85
Trace Impedance =27-33 ohm R51
100_0402_1%
R29
R28
VCC86
VCC87
Trace Length Matc < 25 mils
SENSE LINES

2
R27 VCC88 AJ35 VCCSENSE_R 1 2 R52 0_0402_5%
R26 VCC89 VCC_SENSE AJ34 VSSSENSE_R 1 2 R53 VCCSENSE <55>
0_0402_5%
P35 VCC90 VSS_SENSE VSSSENSE <55>
P34 VCC91
VCC92 10/19 Update to @ for PWR modification.

1
P33
P32 VCC93 B10 1 R66 @2 R54
P31 VCC94 VCCIO_SENSE A10 1 VCCIO_SENSE <52,53>
VSSIO_SENSE_L R74 2VSSIO_SENSE 100_0402_1% 100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO 10_0402_1%
P29 VCC96 @

2
P28 VCC97
VCC98 R74 & R79 put together +V1.05S_VCCP
P27
P26 VCC99 R79
A VCC100 2 1 A
VSSIO_SENSE_L <53>
10_0402_1%
10/19 Add off page to PWR side.
VSS_SENCE 100ohm +-1% pull-down to GND near processor

TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/7) PWR,BYPASS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V_CPU_VDDQ
@ J1 Q6

1
1 2 D LBSS138LT1G_SOT-23-3
R668 1 2 DRAMRST_CNTRL

1
PAD-OPEN 4x4m +VREF_DQ_DIMMA G DRAMRST_CNTRL <7>
1 2 R55 C92 @ +VREF_DQ_DIMMB R670@ S

3
<46,53,54> SUSP 0_0402_5% 220_0402_5% .1U_0402_16V7K 1 2 0_0402_5%~D +V_DDR_REFA_R
11/03 update @ 2 1 2 0_0402_5%~D +V_DDR_REFB_R
to 82K U3 R671@

12
DMN3030LSS-13_SOP8L-8 D

1
+3VALW +VSB 8 1 AP4800 Q3 2 RUN_ON_CPU1.5VS3#

1
7 2 2N7002_SOT23 G D
D 6 3 Id=9.6A @ S DRAMRST_CNTRL 2 R353 R64 D

3
1
5 G 1K_0402_1% 1K_0402_1%

1
R56 S @ @

2
@ R667 82K_0402_5% Q9

4
100K_0402_5% LBSS138LT1G_SOT-23-3
11/03 update

2
2
RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3 1 R885 2
to 0.047u M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

1
15K_0402_1% 1

1
D D +VCC_GFXCORE_AXG
1 2 2 Q7 @ 2 Q4 R57 C97
<42,53> CPU1.5V_S3_GATE
0_0402_5% @ R58 G 2N7002_SOT23 G 2N7002_SOT23 330K_0402_5% 0.047U_0402_25V7K

1
S S @ 2

2
1 2 R616
<25,42,46,51,52,53,54> SUSP#
0_0402_5% @ R59 10_0402_1%

2
RUN_ON_CPU1.5VS3# <6> VCC_AXG_SENSE <55>
POWER RUN_ON_CPU1.5VS3

1
Check
+VCC_GFXCORE_AXG JCPU1G R89 @
Q5-orignal part
100_0402_1% AP2302GN-HF_SOT23-3
AT24 AK35
SV-QC: 50A SB523020210 +1.5V

SENSE
LINES

2
AT23 VAXG1 VAXG_SENSE AK34 +1.5V_CPU_VDDQ
VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <55>
AT21
SV-DC(GT2): 33A VAXG3

2
G
AT20 PMV45EN_SOT23-3
AT18 VAXG4 R626 Q5 @
VAXG5

1
AT17 10_0402_1% 3 1
AR24 VAXG6

D
AR23 VAXG7 R67 R62 @
+V_SM_VREF should

2
AR21 VAXG8 1K_0402_1% 1K_0402_1%
AR20 VAXG9 have 20 mil trace width

2
AR18 VAXG10 AL1 +V_SM_VREF_CNT 1 R61 @2 +V_SM_VREF
C
AR17 VAXG11 SM_VREF 0_0402_5% C
VAXG12

1
AP24 1

VREF
AP23 VAXG13
AP21 VAXG14 C98 R78 R63 @
AP20 VAXG15 B4 +V_DDR_REFA_R .1U_0402_16V7K 1K_0402_1% 1K_0402_1%
AP18 VAXG16 SA_DIMM_VREFDQ D1 +V_DDR_REFB_R 2

2
AP17 VAXG17 SB_DIMM_VREFDQ
AN24 VAXG18
AN23 VAXG19
AN21 VAXG20
AN20 VAXG21 +1.5V_CPU_VDDQ
AN18 VAXG22
5A

DDR3 -1.5V RAILS

AN17 VAXG23 +1.5V +1.5V_CPU_VDDQ
AM24 VAXG24 AF7

GRAPHICS
AM23 VAXG25 VDDQ1 AF4 C396 @
AM21 VAXG26 VDDQ2 AF1 .1U_0402_16V7K
VAXG27 VDDQ3 1
AM20 AC7 1 1 1 1 1 1 1 2
VAXG28 VDDQ4

10U_0603_6.3V6M
C117

10U_0603_6.3V6M
C118

10U_0603_6.3V6M
C119

10U_0603_6.3V6M
C120

10U_0603_6.3V6M
C121

10U_0603_6.3V6M
C122
AM18 AC4 + C123
AM17 VAXG29 VDDQ5 AC1 330U_2.5V_M C129 @
AL24 VAXG30 VDDQ6 Y7 .1U_0402_16V7K
AL23 VAXG31 VDDQ7 Y4 2 2 2 2 2 2 2 1 2
AL21 VAXG32 VDDQ8 Y1
AL20 VAXG33 VDDQ9 U7 C96
AL18 VAXG34 VDDQ10 U4 .1U_0402_16V7K
AL17 VAXG35 VDDQ11 U1 1 2
AK24 VAXG36 VDDQ12 P7
AK23 VAXG37 VDDQ13 P4 C95
AK21 VAXG38 VDDQ14 P1 .1U_0402_16V7K
AK20 VAXG39 VDDQ15 1 2
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
AJ21 VAXG44
AJ20 VAXG45 +VCCSA
B
AJ18 VAXG46 6A B

AJ17 VAXG47 M27 +VCCSA

AH24 VAXG48 VCCSA1 M26
SA RAIL

VAXG49 VCCSA2 1 1 1 1 1

10U_0603_6.3V6M
C124

10U_0603_6.3V6M
C125

10U_0603_6.3V6M
C126

10U_0603_6.3V6M
C127
AH23 L26
AH21 VAXG50 VCCSA3 J26 + C128 @
AH20 VAXG51 VCCSA4 J25 330U_D2_2.5VY_R9M
AH18 VAXG52 VCCSA5 J24 2 2 2 2
AH17 VAXG53 VCCSA6 H26 2
VAXG54 VCCSA7 H25
VCCSA8 @
1.8V RAIL

H23
+1.8VS VCCSA_SENSE +VCCSA_SENSE <52> +3VS +3VALW
R69 0_0805_5% 1.2A 1 @ 2
1 2 +1.8VS_VCCPLL B6 R68 0_0402_5%
VCCPLL1

2
A6 C22
MISC

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <52>

22U_0805_6.3V6M
C154

22U_0805_6.3V6M
C345

10U_0603_6.3V6M
C130

1U_0402_6.3V6K
C131

1U_0402_6.3V6K
C132

@ 1 1 1 1 1 A2 C24 R75 R76 @

VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <52>
10K_0402_5% 10K_0402_5%

@ @

1
2 2 2 2 2 A19 H_VCCP_SEL 1 2
VCCIO_SEL VCCP_PWRCTRL <52>
R77 0_0402_5%
TYCO_2013620-2_IVY BRIDGE
IVY Bridge drives VCCIO_SEL low
VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
A A

Security Classification Compal Secret Data

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/7) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 10 of 60
5 4 3 2 1