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VHDL Testbench Code For The Single-Port RAM

This document contains VHDL testbench code for testing a single-port RAM component. It includes the component declaration for the RAM, defines signals for the RAM inputs and outputs, and generates a clock signal. It then instantiates the RAM component and includes two processes - one to generate the clock signal and another stimulus process that first reads then writes data to different addresses in the RAM over multiple clock cycles.

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Souvik Halder
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173 views2 pages

VHDL Testbench Code For The Single-Port RAM

This document contains VHDL testbench code for testing a single-port RAM component. It includes the component declaration for the RAM, defines signals for the RAM inputs and outputs, and generates a clock signal. It then instantiates the RAM component and includes two processes - one to generate the clock signal and another stimulus process that first reads then writes data to different addresses in the RAM over multiple clock cycles.

Uploaded by

Souvik Halder
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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--VHDL Testbench code for the single-port RAM

-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects


-- VHDL project: VHDL code for a single-port RAM
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-- VHDL testbench code for the single-port RAM
ENTITY tb_RAM_VHDL IS
END tb_RAM_VHDL;

ARCHITECTURE behavior OF tb_RAM_VHDL IS

-- Component Declaration for the single-port RAM in VHDL

COMPONENT Single_port_RAM_VHDL
PORT(
RAM_ADDR : IN std_logic_vector(6 downto 0);
RAM_DATA_IN : IN std_logic_vector(7 downto 0);
RAM_WR : IN std_logic;
RAM_CLOCK : IN std_logic;
RAM_DATA_OUT : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;

--Inputs
signal RAM_ADDR : std_logic_vector(6 downto 0) := (others => '0');
signal RAM_DATA_IN : std_logic_vector(7 downto 0) := (others => '0');
signal RAM_WR : std_logic := '0';
signal RAM_CLOCK : std_logic := '0';

--Outputs
signal RAM_DATA_OUT : std_logic_vector(7 downto 0);

-- Clock period definitions


constant RAM_CLOCK_period : time := 10 ns;

BEGIN

-- Instantiate the single-port RAM in VHDL


uut: Single_port_RAM_VHDL PORT MAP (
RAM_ADDR => RAM_ADDR,
RAM_DATA_IN => RAM_DATA_IN,
RAM_WR => RAM_WR,
RAM_CLOCK => RAM_CLOCK,
RAM_DATA_OUT => RAM_DATA_OUT
);

-- Clock process definitions


RAM_CLOCK_process :process
begin
RAM_CLOCK <= '0';
wait for RAM_CLOCK_period/2;
RAM_CLOCK <= '1';
wait for RAM_CLOCK_period/2;
end process;

stim_proc: process
begin
RAM_WR <= '0';
RAM_ADDR <= "0000000";
RAM_DATA_IN <= x"FF";
wait for 100 ns;
-- start reading data from RAM
for i in 0 to 5 loop
RAM_ADDR <= RAM_ADDR + "0000001";
wait for RAM_CLOCK_period*5;
end loop;
RAM_ADDR <= "0000000";
RAM_WR <= '1';
-- start writing to RAM
wait for 100 ns;
for i in 0 to 5 loop
RAM_ADDR <= RAM_ADDR + "0000001";
RAM_DATA_IN <= RAM_DATA_IN-x"01";
wait for RAM_CLOCK_period*5;
end loop;
RAM_WR <= '0';
wait;
end process;

END;

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