WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS Chandra Shankar, Sajai Vir Singh

A New Trans-admittance Mode Biquad Filter using MO-VDTA

CHANDRA SHANKAR1, SAJAI VIR SINGH2
1
Dept. of Instrumentation and Control Engineering
JSS Academy of Technical Education Noida, 201301, INDIA
[email protected]
2
Dept. of Electronics and Communication Engineering
Jaypee Institute of Information Technology, Noida, 201304, INDIA
[email protected]

Abstract: - In this paper, a new trans-admittance-mode biquad filter configuration based on two multi output
voltage differencing transconductance amplifiers (MO-VDTAs) as newly active elements is proposed which
also consists of two grounded MOS resistors and two capacitors with one of the capacitor is being permanently
grounded. The proposed configuration is competent of realizing trans-admittance-mode low pass (LP), band
pass (BP), high pass (HP), band reject (BR) and all pass (AP) filtering responses. Moreover, the proposed
circuit offers several excellent features such as electronic tunability of pole frequency and quality factor, low
active and passive sensitivity and low power consumption. To justify the theoretical analysis, the proposed
circuit is simulated using PSPICE in 0.35μm CMOS technology from TSMC.

Key-Words: - VDTA, TAM, Biquad, Filter, Analog signal processing, Tunable.

1 Introduction conductance amplifier (VDTA) [22] current

differencing trans-conductance amplifier (CDTA)
In the last few decades, numerous number of [23] etc., as current-mode active elements in the
current-mode active elements have been introduced implementation and perform nicely with respect to
and gained significant attention to implement analog various TAM filtering functions realization but
biquad filters used for analog signal processing unfortunately, they still suffer from one or more
applications due to having their high performance following drawbacks.
attributes such as wider signal bandwidth, low (i) Use of more number of active and /or passive
power consumption, larger dynamic range, better elements [15-21].
linearity, simple circuitry and requirement of lesser (ii) Use of excessive number of floating passive
on chip area [1-26] with respect to voltage-mode components [16-18, 23]
counterpart. Biquad filters with voltage input(s) and
(iii) Voltage input signal (s) is not applied at high
current output(s) are termed as trans-admittance-
impedance terminal [15-17, 23].
mode (TAM) filters and suitable for the applications
where conversion of voltage signal into current (iv) Incompetent of realizing all five standard
signal is required. Such applications find usages in filtering functions [16-20, 22].
receiver baseband block of modern radio system, (v) Lack of electronic tunability of filter parameters
D/A converters and optical receivers etc [15-16]. [16-18, 21].
Literature survey has shown that comparatively (vi) Use of more than minimum number of
limited work has been proposed in the domain of capacitors (two) required to realize various filtering
TAM filter. In the available literature most of the functions [15].
circuits uses single input multi output (SIMO)
configuration to realize TAM filter [15-22] while Moreover, it is also noted from Table 1 that
remaining circuit uses multi input single output only three input single output TAM circuit based on
(MISO)[23] configuration. Details comparative two CDTAs as active element can realize all the five
study among them is discussed in Table 1 which standard filtering function [23]. However, it uses
reveals that the various proposed TAM filter circuits four passive elements (two resistors and two
uses (CII) [16], four terminal floating nuller (FTFN) capacitors) among them three are being floating (not
[17], operational transconductance amplifier grounded), for realizing all five filtering functions.
(OTAs) [19-20], voltage differencing trans- In addition, none of the voltage input signal is

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Table 1. Comparison of different TAM filters with proposed TAM filter circuit

References [15] [16] [17] [18] [19] [20] [21] [22] [23] Proposed

Features

No. & type of

2 CCCCTA 3 CCII 3 PFTFN 5 DCC-DVCC 4 OTA 4 OTA 3 CCCII 2 VDTA 2 CDTA 2 VDTA
active element

No. & type of

3C 3R, 2C 3R, 2C 2C , 1R 2C 2C 2C 2C 2R, 2C 2R, 2C
passive element

No. of Floating
passive element NIL 4 (2R+2C) 4 (2R+2C) 3(2R+1C) NIL NIL NIL NIL 3(2R+1C) 1 (1C)

SIMO/MISO SIMO SIMO SIMO SIMO SIMO SIMO SIMO SIMO MISO MISO

Voltage I/P
applied at high
NO NO NO YES YES YES YES YES NO YES
impedance
terminal (s)

Realization type LP,BP,HP, LP,BP,HP, LP,BP,HP, LP,BP,HP,

LP,BP,HP LP,BP,HP LP,BP,HP LP,BP,HP LP,BP,HP LP,BP,HP
AP, BR AP, BR AP,BR AP,BR

Electronic
YES NO NO NO YES YES NO YES YES YES
tunability

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V P 
applied at high impedance terminals. Keeping above  I z   g mF − g mF 0  
discussion in the mind, we have proposed a new I  =  0 ± g mS   
VN (1)
three input single output trans-admittance mode  X±   0
VZ 
filter which uses two MO-VDTAs, two grounded
MOS resistors , two capacitors and can realize all Both transconductance parameters gmF and gmS of
five filtering response (LP, HP, BP,BR,AP) in trans- VDTA are controlled by biasing current IBF and IBS
admittance-mode. The circuit enjoys an electronic of VDTA, respectively. The VDTA shown in fig.1
adjustment property of pole frequency ( ωo ) as well is realized using CMOS implementation and shown
as bandwidth independent of Q0 and possesses low in Fig.2. For CMOS implementation of VDTA
active and passive sensitivity performance. The realized as shown in Fig.2, gmF and gmS can be
performance of proposed circuit is verified by mathematically related by following equations.
PSPICE simulations.
W
2 VDTA Description g mF = I BF µnCox ( ) M 1, M 2 (2)
L
VDTA is one of the new active element which is
first introduced by A. Yesil, F. Kacar and H. W
Kuntman in 2011[24] and offers the advantage of its g mS = I BS µnCox ( ) M 5, M 6 (3)
electronic tuning ability through two L
transconductance parameters. Moreover, this device
can be operated in both current as well as voltage- Where µn is the effective carrier mobility of NMOS
modes, providing flexibility to the circuit designers transistor and Cox is the gate-oxide capacitance per
[24-26]. MO-VDTA is modified version of unit area. (W/L)M1, M2 and (W/L) M5, M6 are the aspect
conventional VDTA which can be obtained from ratio of M1, M2 and M5, M6 NMOS transistor
VDTA by inserting additional transconductance pairs, respectively.
outputs. It’s symbolic diagram is shown in Fig.1
where P, N are two input terminals and Z, X+, X- 3 Proposed TAM Filter and Its
are the output terminals. Each input and output Analysis
terminals in VDTA have high impedance. Voltage
difference between P and N (VP – VN) is transferred The proposed TAM filter configuration is shown in
to a current at terminals Z (IZ) by transconductance Fig.3 which employs two MO-VDTAs , two
parameters (gmF) of VDTA. Further voltage across grounded resistors (R1 and R2) and two capacitances
Z terminal is also transferred to a current at (C1 and C2) with one of the capacitor (C1) is being
terminals X+ and X- (IX+ and IX-) by other permanently grounded. In the proposed
transconductance parameters (gmS) of VDTA. The configuration as shown in Fig.3, each grounded
voltage current relationship between various input resistor (Ri, where i=1, 2) has been realized by using
and output terminals of MO-VDTA can be parallel connection of two NMOS transistors (MR1
described in the following matrix equation. and MR2). Thus, the equivalent resistance can be
calculated by

1
Ri = (4)
WMRi
2 µ n C ox (Vci − VT )
LMRi

Where VT is the threshold voltage of the NMOS

WMRi
transistor. Vci is the biased voltage and
L MRi
Fig.1: Block diagram of MO-VDTA stands for aspect ratio of NMOS transistor used in
the resistance realization. Routine analysis of the
proposed circuit of Fig.3, yields the expression of
current output (Iout) on applying voltage inputs (Vin1,
Vin2, Vin3 ) can be derived as

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Fig.2: Implementation of MO-VDTA using CMOS transistors

Fig.3: Proposed three input single output TAM Biquad filter

g mF 1 g mF 2 g mS1 R1 sg
V1 − mF 2 V2 + s 2V3
C1C 2 C2
I out = g mS 2 (5)
g g R g g g g RR
s 2 + s mF 2 mS 2 1 + mF 1 mS1 mF 2 mS 2 1 2
C2 C1C 2

Where gmFi and gmSi (i=1,2) denotes the first and (Iout) with following appropriate selection of input
second transconductance gains of ith VDTA, voltage signal.
respectively. It is seen from the above equation that (i) If V1=V2=0 and V3=Vin , a biquadratic TAM HP
the proposed filter circuit used as three input single filter can be realized.
output (TISO) configuration and realizes all five
(ii) If V1=V3=0 and V2=Vin, a biquadratic TAM BP
standard filter functions in TAM at current output
filter can be realized.

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(iii) If V2=V3=0 and V1=Vin, a biquadratic TAM LP V P 

filter can be realized.  I z   β F g mF − β F g mF 0  
(iv) If V2=0, V1=V3=Vin, and gmS2R2=1, a I  =  0 ± β S g mS   
V N (12)
 X±   0
VZ 
biquadratic TAM BR filter can be realized.
(v) If V1=V2= V3=Vin , gmS2R1=1 and gmS2R2=1, a
biquadratic TAM AP filter can be realized. Where βFi and βSi are the tracking error for the first
and second stages of the ith MO-VDTA (i=1,2).
The pole frequency (ω0 ) , the quality factor (Q0) and With consideration of above non ideal errors we
bandwidth (BW) ω0/Q0 of each filtering response further reanalyze the proposed circuit of Fig.3. The
can be expressed as: following non-ideal filter transfer function and its
filter parameters can be obtained as.
g mF 1 g mF 2 g mS1 g mS 2 R1 R2
ω0 = (6)
β F 1β F 2 β S 1 g mF 1 g mF 2 g mS 1 R1
C1C 2 V1 −
C1C2
s β F 2 g mF 2
g mF 1 g mS1 R2 C 2 V2 + s 2V3
Q0 = (7) C2 (13)
g mF 2 g mS 2 R1C1 I out = β S 2 g mS 2
β β g g R
s 2 + s F 2 S 2 mF 2 mS 2 1 +
C2
g mF 2 g mS 2 R1
BW = (8) β F 1β S 1β F 2 β S 2 g mF 1 g mS 1 g mF 2 g mS 2 R1 R2
C2 C1C2

If we select gmF1 = gmF2 = gmF and gmS1 = gmS2 = gmS

in the design procedure, then equations (6)-(8) can
be further simplified as β F 1 β S1 β F 2 β S 2 g mF 1 g mS1 g mF 2 g mS 2 R1 R2
ω0 = (14)
C1C 2
R1 R2
ω0 = g mF g mS (9)
C1C2
β F 1 β S 1 g mF 1 g mS1 R2 C 2
Q0 = (15)
β F 2 β S 2 g mF 2 g mS 2 R1C1
R2C2
Q0 = (10)
R1C1 β F 2 β S 2 g mF 2 g mS 2 R1
BW = (16)
C2
g mF g mS R1
BW = (11)
C2 It is evident from equation (13)-(16) that the filter
parameters such as pass band gain, ω0 , Q0 and BW
It is clear from equations (9)-(11) that both filter of various TAM filtering responses of the proposed
parameters ω0 and BW can be electronically tuned circuit may be slightly changed due to effect of
independent of Q0 by varying either gmF (IBF) or gmS tracking errors of VDTAs but these deviation can be
(IBS) or both. Furthermore, Q0 can also be minimized by adjusting the electronic controllable
electronically tuned independent of ω0 by trans-conductance parameters.
maintaining the product of R1 and R2 as constant that
can be done by adjusting the bias voltage of MOS The active and passive sensitivities of ω0 and
transistors used in resistors at appropriate levels. Q0 for the proposed filter in Fig.3 are derived and
given in equations (17)-(20).
4 Non Ideal Effects and Sensitivity
Analysis: 1 ω0 1
S βωF01 , β S=
1 ,βF 2 ,βS 2
=, S R1 , R2 ,
Taking the effects of non-ideal characteristics of the 2 2
MO-VDTA into consideration, the current and 1 (17)
voltage relations between various ports of VDTA S gωmF0 1 , gmS 1 , gmF 2 , gmS 2 =
can be rewritten as: 2

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1 simulation results showing the large signal transient

S Cω10 = S Cω20 = − (18) responses of LP and BP outputs are shown in Fig.6
2 where a load of 2.79KΩ resistor was used to obtain
1 Q0 1 the output across LP and BP responses.
S βQF01 , β S 1=
, g mF 1 , g mS 1 =, S R2 ,C2 (19) Furthermore, the total harmonic distortion results
2 2 for LP and BP responses are shown in Fig.7 which
clearly shows that the THD values of the proposed
1 1 filter for LP output was found in the range of .68 to
S βQF01 , β S 2 , gmF 1 , gmS 2 =
− , S RQ10,C1 =
− (20) 1.94% for sinusoidal input voltage signal of constant
2 2 amplitude of 40mV and variable frequency between
500KHz to 5MHz whereas the THD values for the
Consequently, all of the component sensitivities of BP output remain in the range of 2.62 to 4.33 for the
ω0 and Q0 are within 0.5 in magnitude which is low. sinusoidal input voltage of constant frequency of
2.51MHz and variable amplitude between 10mV to
5 Simulation Results 150mV.

In order to verify the performance of the Lastly, Monte-Carlo analysis is also

proposed filter as per discussion in the section 3, the performed to observe the tolerance variation of
circuit of Fig.3 has been simulated using CMOS capacitive components on the performance of
implementation of VDTA (shown in Fig. 2), by frequency response and pole frequency of the
using standard CMOS model parameters of 0.35µm proposed circuit. The TAM BP output with 10%
technology from TSMC as given in Table 2. The tolerance variation in C1 = C2 = 25 pF has been
supply voltages were selected as VDD = -VSS = 1.0V simulated for the presentation. The simulation was
and +Vci = -Vci = 1.07V. The passive and active done simultaneously for five runs. The
components values were taken as R1 = R2 = 2.79KΩ, corresponding results are shown in Fig.8. These
C1 = C2 = 25pF and gmF1 = gmF2 = gmS1 = gmS2 ≈ results demonstrate that capacitive tolerances
376.67µA/V (IBF1 = IBF2 = IBS1 = IBS2 = 40 µA), which (deviation) do not severely affect the circuit
results in total power consumption of about .992mW performance in term of frequency response and pole
of the proposed circuit. The transistors aspect ratio frequency.
of the VDTA as described in Table 3 was used in
this simulation. Fig. 4 shows the simulated trans- 6 Conclusion
admittance-mode gain and phase responses of LP, A new single input three output TAM biquad
HP, BP, BR and AP for the proposed trans- universal filter has been described in this paper
admittance -mode biquad filter as shown in Fig.3. which consits of only two MO-VDTAs, two
From the simulation results, the pole frequency was grounded MOS resistors, two capacitors with one of
obtained as 2.51 MHz which is nearly same as the which is permanentaly grounded and can realizes
calculated value of 2.52 MHz. In Fig. 5, various BP LP, BP, HP, BR and AP filtering responses. In
and LP filtering responses for proving the feature of addition, the proposed circuit offers the following
electronic tunability of pole frequency independent advantages.
of Q0 are shown which were obtained by (i) Realization of all the five standard filtering
simultaneous variation of all transconductance responses in trans-admittance-mode with out
parameters of VDTAs as gmF1 = gmF2 = gmS1 = gmS2 = requiring any inverted type and/or scaled type
266.33uA/V, 376.67uA/V, 532.67uA/V (IBF1 = IBF2 voltage input signal(s).
= IBS1 = IBS2 = 20µA, 40µA, 80µA) for a constant (ii) Use of grounded resistors which is easily
Q0=1. Three pole frequencies variation were
realized using only two MOS transistors.
obtained as 1.25MHz, 2.51MHz and 5.02 MHz,
(iii) Availability of each trans-admittance filtering
respectively.
output explicitly at high impedance output.
(iv) Two of the voltage inputs are applied on
Next, the transient behaviour of LP and BP
high impedance input ports.
outputs for the proposed filter was also investigated
(v) All active and passive sensitivities are low and
by applying an appropriate sinusoidal input voltage
with in 0.5 in magnitude.
signal having peak to peak amplitude of 80mV at
(vi) Low power consumption of 0.992mW.
frequency of 200 KHz in case of LP and 100 mV at
frequency of 2.51 MHz in case of BP. The

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(vii) Provide the feature of electronic tunability With above mentioned features it is very suitable to
of filter parameters. realize the proposed circuit in monolithic chip to use
(viii) Provide the canonical structure. in battery powered, portable electronic equipments
such as wireless communication system devices.

(a)

(b)

(c)

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(d)

(e)

Fig.4: Gain and phase response of the (a) LP (b) HP (c) BP (d) BR (e) AP for proposed TAM filter of Fig.3

(a)

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(b)

Fig.5 Electronic controllability of ω0 of (a) BP response at Q0=1 (b) LP response at Q0=1

(a)

(b)
Fig.6 (a) Transient behavior of LP output for a sinusoidal input of 500KHz frequency (b) Transient
behavior of BP output for a sinusoidal input of 2.51MHz frequency of proposed circuit in Fig.3

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(a) (b)
Fig.7 %THD of (a) LP Filter (b) BP filter

Fig.8 Montecarlo analysis of BP filter with 10% tolerance variation in capacitance

Table 2. Transistor Model parameters of 0.35 um TSMC file

Table 3. Transistors aspect ratios of CMOS implementation
.MODEL NMOS NMOS(LEVEL=3 TOX=7.9E-9
of MO-VDTA of Fig.2
+NSUB=1E17 GAMMA=0.5827871 PHI=0.7
+VTO=0.5445549 DELTA=0 UO=436.256147
MOS Transistors Aspect Ratio
+ETA=0 THETA=0.1749684 +KP=2.055786E-4
+VMAX=8.309444E4 KAPPA=0.2574081
+RSH=0.0559398 NFS=1E12 TPG=1 XJ=3E-7
M1,M2,M5,M6 16.1/.7
+LD=3.162278E-11 WD=7.04672E-8
+CGDO=2.82E-10 CGSO=2.82E-10 CGBO=1E-10
M3,M4 28/.7
+CJ=1E-3cvfr54 PB=0.9758533 MJ=0.3448504
+CJSW=3.777852E-10 MJSW=0.3508721)
M7-M14 8.5/.7
.MODEL PMOS PMOS (LEVEL =3 TOX = 7.9E-9 M15-M20 7/.7
+NSUB=1E17 GAMMA=0.4083894 PHI=0.7
+VTO=-0.7140674 DELTA=0 UO=212.2319801 MRi (i=1,2) for MOS 3/1
+ETA=9.999762E-4 THETA=0.2020774 resistance realization
+ KP=6.733755E-5 VMAX=1.181551E5 KAPPA=1.5
+ RSH=30.0712458 NFS=1E12 TPG=-1 XJ=2E-7
+LD=5.000001E-13 WD=1.249872E-7 References:
+CGDO=3.09E-10 CGSO=3.09E-10 [1] C. Toumazou, F. J. Lidgey and D. G. Haig,
+ CGBO=1E-10 CJ=1.419508E-3 PB=0.8152753 Analogue IC design: the current-mode approach,
+MJ=0.5 CJSW=4.813504E-10 MJSW=0.5) London, UK, Peteregrinus Ltd., 1990.

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 WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS Chandra Shankar, Sajai Vir Singh

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