Chapter 5

RF power amplifiers

The last stage in a transmitter path is the power amplifier (PA). No more signal processing
takes place after the PA, thus putting stringent demands on the PA. Furthermore, efficient
RF PAs are highly desirable in battery-operated systems, since PAs typically dominate
the power consumption of the system. This chapter focuses on the design of bipolar and
MOS PAs and discusses principles to improve the linearity of a PA.

5.1 SPECIFICATION
In an RF front end, the last step between up-conversion of the baseband signal
to the radio frequency and the antenna is amplification of the RF signal. One
or more levels of delivered power to the antenna have been specified for each
telecommunication standard. For instance, for the Bluetooth wireless standard,
transmit class 2 refers to 0 dBm output power, while for UMTS, the specification
is 24 dBm. The latter specification means that the amplifier must deliver a
serious amount of power to the load (i.e. the antenna), hence the commonly
used name power amplifier.

5.1.1 Efficiency
When a specification reads that an output power must be delivered to the
load, the amplifier itself must generate much more power. The front end will
normally be followed by a diplexer or duplexer with some losses that
must be overcome by the power amplifier. Furthermore, the amplifier has a
certain efficiency it costs power from the supply line to produce power at the
output node. Define the DC input power as and the RF output power as

145
146 CIRCUIT DESIGN FOR RF TRANSCEIVERS

then the output efficiency is defined as

A more realistic measure of efficiency is the power added efficiency (PAE) that
takes into account the amount of power that is delivered to the input,

where is the power gain. Nowadays, amplifier efficiencies range from

35% to 55%. Consequently, for a specification of 0 dBm delivered power, the
amplifier should be able to dissipate 5 dBm. When considering battery-operated
handheld sets, the power efficiency of the amplifier is definitely a main concern.

5.1.2 Generic Amplifier Classes

Power amplifiers can be divided into classes based on their achieved efficiency
[1], [2], [3]. Consider the simplified NMOS power amplifier of Figure 5.1. The
behavior of the amplifier is determined by the input signal, the load impedance
and conduction angle. The six most well known classes will be discussed briefly
with reference to Figure 5.2.

Class A. The transistor of the amplifier is biased and driven so that it is

always in active mode. In this way, the distortion will be small at the cost
of large currents and voltages. This latter aspect results in a high power
consumption, reducing the efficiency of the amplifier. This is even more
 RF power amplifiers 147

true because the amplifier consumes power when there is no output signal.
The maximum theoretically obtainable efficiency is 35% for resistive load
and 50% for inductive load.
Class B. To increase the efficiency, the transistor can be made active only
half of the time, at the cost of an increased distortion. To still have low
distortion levels, the bias currents are chosen to be small and the transistor
is normally in its saturation mode instead of in the linear mode [4], [5].
Class C. A further increase in efficiency can be obtained by leaving the
transistor unbiased and driving it far into linear mode. Class C is usually
considered when the conduction angle of the transistor is smaller than 180
degrees. The transistor is still operating as a current source. The efficiency
is depends on the conduction angle and as the angle reduces the efficiency
increases. However, a reduction in conduction angle means that the current
drive capability is reduced, resulting in a lower output power. Theoretically,
a conduction angle of 180 degrees, i.e. Class B, gives 78.5% efficiency.
A conduction angle of 90 degrees gives an efficiency of 90%. The output
signal does not follow the input signal, the amplifier behaves non-linearly
and the distortion levels are high. This type of amplifier can be used in the
case of frequency modulated signals. To obtain a reasonable output sine
wave, the single transistor amplifier is loaded with an RLC tank, where the
R represents the load, i.e. the antenna input impedance.
Class D. The difference between Class C and D lies in the fact that Class D
uses at least two transistors, but neither is forced to simultaneously support
both voltage and current. In theory, one can reach 100% efficiency, but in
practical applications the efficiency is comparable to Class C. The disad-
vantage of class D compared to Class C is in the synchronization of the two
(or more) switches.
Class E. Basically, a resonance network is used to allow switching when
the voltage is low [6]. More precisely, the switching device, i.e. the power
transistor, becomes active when the slope of the voltage and current are both
almost zero or almost zero. Consequently, even with mis-timing, the loss
is low and therefore high efficiency rates can be achieved. The resonance
network is placed between the output of the transistor and the load, and the
resonance frequency is at the fundamental RF frequency. The drawback of
this approach is the sometimes extreme output peak voltage. This class of
operation is most often used in RF mobile transmitters [7], [8].
Class F. If we combine the single switch of Class C with the square wave
voltage approach of Class D, we obtain Class F. A resonance circuit at
148 CIRCUIT DESIGN FOR RF TRANSCEIVERS

the third harmonic of the RF frequency is placed at the output of the single
transistor to flatten out the voltage and “shape” it like a square wave voltage.
Class F can also be considered as Class B with resonances on both the
fundamental and the third harmonic, shaping the voltage waveform to a
square waveform.

The classes discussed can also be related to the conduction angle and input
signal overdrive. This is indicated in Figure 5.3. For small input signals, the
RF PA of Figure 5.1 can operate in class A, AB, B or C, depending on the
conduction angle. The conduction angle is determined primarily by the DC
gate bias. The efficiency can be improved by reducing the conduction angle
and moving in the direction of class C at the expense of lower output power.
An alternative is to increase the gate overdrive until the PA operates as a switch,
while keeping the same conduction angle.
 RF power amplifiers 149

5.1.3 Heating
Frequent battery operation is one obvious reason behind the need to increase
power efficiency. The higher the efficiency, the longer the standby time and talk
time. One other important reason to search for optimal efficiency is the heating
problem . The maximum output power is preferably not limited by the heat it
can dissipate. The ratio between the maximum output power and the dissipated
power is Suppose a power transistor is able to dissipate 1 W safely,
without any heating problems. When the device is used in a Class A operation,
the maximum output power is 0.54 W. However, if the device operates in class
C, the maximum output power becomes 3 W, but at the same heating. A much
larger output power with the same heating constraint is therefore possible in
Class C compared to Class A.
The thermal resistance is defined as

where is the maximum peak junction temperature and is the case tem-
perature, normally 25°C. Parameter is determined by the reliability of the
transistor in the process. From and the maximum is calculated.
The parameter is less in a ceramic package than in a plastic package. The die
in a ceramic package can therefore have a higher than in a plastic package,
in both cases being the same. For plastic packages the maximum tempera-
ture is 150° to 175°C and 200°C for ceramic, assuming that is higher. It is
150 CIRCUIT DESIGN FOR RF TRANSCEIVERS

important to notice that the thermal resistance of a power amplifier depends on

the layout of the chip (number of active areas), the thickness of the silicon chip
the die attachment process, and the thickness of the package.

5.1.4 Linearity
Some telecommunication standards modulate the data in the frequency domain,
like the GFSK modulation scheme used in Bluetooth, for instance. For the
amplifier, the output amplitude does not have to follow the input amplitude;
non-linear amplification is allowed. However, other standards only modulate
the data or also modulate it in the amplitude domain, (see UMTS with the
modulation scheme, for instance). It then becomes important for
the amplifier to be linear; the amplitude information may not be distorted. We
have already touched on the fact that linearity becomes an issue in the case of
amplitude modulated signals. The trade-off between efficiency and linearity for
the simplified amplifier of Figure 5.1 is determined by the gate voltage The
output drain voltage is a linear relation of in the case of class A operation.
The power dissipation is found to be where is the current through
the device. In this case we have a highly linear, low efficiency power amplifier.
Increasing the gate overdrive will reduce the power dissipation. The transistor
then acts as an on-off switch and, assuming there is no overlap between the drain
current and the voltage, the power dissipation becomes zero, and is therefore
100% efficient. However, the output voltage and current are distorted square
waves and the amplifier is therefore no longer linear. A switched mode amplifier
will be highly efficient, but also highly non-linear.
A non-linear amplifier causes amplitude modulation to amplitude modulation
(AM-AM) behavior for an amplitude modulated input signal. Assume we can
model the amplifier’s gain as

The amplitude of the input signal will also be amplified with the higher order
coefficients, resulting in

and thus AM-AM behavior occurs. If the coefficients are complex, amplitude
modulation to phase modulation (AM-PM) behavior will also occur. These two
behaviors obviously should be minimized to allow proper detection of the real
amplitude information.
A specification which is closely related to linearity is the adjacent channel
power ratio (ACPR). This specification defines the amount of power transmitted
 RF power amplifiers 151

at a certain offset frequency normally the adjacent channel, compared

to the power transmitted in the channel of interest, P

For the EDGE cellular standard, at an offset of 30 kHz, the maximum allowed
transmitted power is –30 dB, while the transmitted power is set to 0 dB, yielding
an ACPR of 30 dB. Obviously, the more non-linear the amplifier, the higher the
power levels in adjacent channels will be due to the cross modulation.

5.1.5 Ruggedness
Ruggedness is the ability to withstand electrical overstress without failure or
degradation. The ruggedness is normally tested under some prescribed condi-
tions: output overvoltage, input overdrive and mismatch load conditions. For
bipolar RF power amplifiers, the two main techniques known to improve the
ruggedness of the circuit, are collector ballasting and emitter ballasting. The
former technique uses a thicker collector epitaxial region to support collector
base depletion. This results in series resistance under each active area before
these active areas are connected in parallel by the low ohmic substrate. There
is consequently more voltage drop over, and better current distribution through,
the active area. The price to pay is a decrease in efficiency. In emitter ballasting,
several lumped resistors are added on each emitter site before they are placed
in parallel. The effect is a lower gain but higher collector-emitter saturation
voltage.

To obtain reasonable efficiency figures and high linearity, we can apply lin-
earization techniques. Conceptually we can use a highly non-linear amplifier
to amplify the phase information. The amplitude information is added by mod-
ulating the power supply of the amplifier or by adding in phase shifted signals.
One other approach is to pre-distort the input signal to correct for the non-linear
behavior of the amplifier. A few possible implementations of these approaches
will be discussed in the following sections. We will start with the discussion
on silicon integrated RF power amplifiers.

5.2 BIPOLAR PA DESIGN

Monolithic RF power amplifiers have traditionally been the territory of GaAs
technologies. Recently, efforts have been made to design power amplifiers for
the lower mobile-phone frequency band using Si technologies. It is the GSM
bands at 900 and 1800 MHz that are the first targets here [9], [10]. Although
some of the designs are still hybrid solutions, the demands are for monolithic
152 CIRCUIT DESIGN FOR RF TRANSCEIVERS

implementations of the power amplifiers in standard bipolar processes. The

advantages are clear: low cost and ease of integration with other mainstream
Si-based circuits. In this section we discuss a monolithic silicon-based power
amplifier [11]. The application field is the USA PCS-CDMA standard. The
modulation scheme of the CDMA system requires the PA used in the handset
to be highly linear. This makes it very challenging to design a highly efficient
monolithic PCS-CDMA PA using Si technologies, due to their inherently high
substrate loss and parasitics.
A simplified schematic diagram of a standard biased PA is shown in Figure
5.4. The PA consists of two common-emitter stages The output-
matching network consists of capacitors C3 to C5, inductors L2, and two
transmission lines (CPWs). The input matching network consists of capacitors
C6 and C7 and a transmission line (CPW). In Figure 5.4, and
are ground inductors from bonding wires. L1 and L2 are off-chip
inductors. The interstage-matching network consists of an on-chip capacitor
C1 and the off-chip inductor L1 realized using a bonding wire and a PCB trace.
C2 is an on-chip bypass capacitor.
This biasing scheme for provides a near-constant low-frequency (1 MHz)
small-signal impedance presented at the base of and a nearly linear control
of the collector’s quiescent current of as shown in Figure 5.5 where
When and are biased into class AB operation, however, its large-
signal RF impedance presented at the base of at 1.9 GHz is capacitive,
and is much larger than its counterpart as shown in Figure 5.6. Also shown in
Figure 5.6 is the PAs output power versus RF input signal levels. We can see
that the two-stage PA starts to saturate at the output power close to 600 mW.
This is due to the fact that as the output power increases, the average voltage
drop across the bias impedance increases. This, in turn, causes a reduction in
the base-emitter voltage of and therefore pushes it into saturation [12].
Figure 5.7 shows a simplified schematic of a PA using an impedance-
controllable biasing scheme to bias It is identical to the PA shown in
Figure 5.4 except for the biasing scheme for The biasing scheme com-
prises two current-mirror subcircuits: one consisting of transistors and
and the other consisting of transistors and If I class and I bias are
chosen correctly, this biasing scheme is capable of providing independent con-
trol of bias impedance and class of operation of Whereas I bias controls
the output impedance of the bias circuit, I class controls the quiescent current
of the output stage. This proposed biasing scheme allows the output stage to
be adjusted for optimum efficiency and linearity.
 RF power amplifiers 153

Its mechanism of controlling the quiescent current is explained below. Ne-

glecting base currents, we have

and since and have the same current, we then have

154 CIRCUIT DESIGN FOR RF TRANSCEIVERS
 RF power amplifiers 155

By choosing Rb2 and Rb3 properly, this leads to

when

The current flowing in must flow in and because and form

a current mirror. Since I class controls the current flowing in it therefore
dictates the quiescent current in that in turn controls the quiescent current
in the output transistor The mechanism of I bias’s controlling the output
impedance of the biasing circuit can be explained in a similar fashion. By
properly scaling the emitter area ratios between transistor pairs, we can readily
control the quiescent current of the output stage and the output impedance of
the bias circuit. This helps us to optimize the efficiency of the output stage
while maintaining the required linearity.
Figures 5.8 and 5.9 show the collector’s quiescent current of and low-
frequency (1 MHz) small-signal impedance of the impedance-controllable bi-
asing scheme presented at the base of the output stage as functions of I class
and I bias. For simplicity, Rb3 is set to zero (Rb3 = 0) in this analysis. We can
see that the control current Iclass in both biasing schemes has a similar effect
on the quiescent current of and the bias impedance: there is near-constant
bias impedance and nearly linear control of the quiescent current. Further-
more, the control current I bias provides an additional means to adjust the bias
impedance, and only slightly changes the quiescent current.
It is of more interest to see its large-signal impedance presented at the base
of at 1.9 GHz. Figure 5.10 shows the RF impedance of the impedance-
controllable biasing scheme and the output power, as a function of the input
signal level. For a fair comparison, the sizes of and and the bias
conditions have been set identical to those for the PA discussed above. There
are several advantages of using the impedance -controllable biasing scheme.
Firstly, it presents low impedance at the base of Secondly, its large-signal
impedance is inductive and not far off from its low-frequency small-signal
values. This helps interstage matching by cancelling part of the capacitive base
impedance of Thirdly, it helps increase output power due to its low RF
impedance. As seen in Figure 5.10, the PA only starts to saturate at the output
power close to 1 W. This is a significant improvement over that of the PA with
the conventional biasing scheme.
The PA with the impedance-controllable biasing scheme was implemented
in a Philips BiCMOS process (QUBiC3) featuring 30 GHz NPNs,
CMOS and high value poly resistors. The emitter area of is 128 times
156 CIRCUIT DESIGN FOR RF TRANSCEIVERS

A photomicrograph of the die with an area of about

is shown in Figure 5.11. The PA was first tested at 1.9 GHz using a three-stub
tuner in the output to benchmark its performance. Both the input and output
stages were biased in a class AB operation. The PAs ACPR and PAE versus the
output power are shown in Figure 5.12. A spectrum analyzer from Rohde &
Schwarz was used in the ACPR measurements. With the output matched using
 RF power amplifiers 157

the tuner, the PA delivers 28.1 dBm output power with 24.5 dB gain, 31.5%
PAE and –45 dBc ACPR. It is worth noting that in this PA, there is a valley
with quite a steep slope in the ACPR curve. This indicates that we can improve
ACPR margins with a slight back-off from the highest output power level.
The tuner was then replaced by surface-mount components on the FR-4
test board. The PA was again tested at 1.9 GHz with a slightly lower base
158 CIRCUIT DESIGN FOR RF TRANSCEIVERS

bias voltage for the input stage to enhance its PAE. I class and I bias were
readjusted to compensate drops in PAE and gain due to the insertion loss from
the surface-mount components. The PAs ACPR and PAE versus the output
power are shown in Figure 5.13. With the input and output matching networks
using the low-cost surface-mount components on the FR-4 test board, the PA
delivers 28.2 dBm output power with 21.5 dB gain, 30% PAE and –45 dBc
ACPR. The same steep slope can be seen in the ACPR curve near the peak output
power level. At lower output power levels, there is a peak almost reaching the
ACPR limit (-45 dBc) in the ACPR curve due to the lower bias in the input
stage.
Figure 5.14 shows an actual ACPR measurement of the PA matched with the
surface-mount components at its highest linear output power level. A 10 dB
attenuator and a coaxial cable were used in the output. Their combined mea-
sured attenuation is 10.8 dB. This attenuation plus the reading of 17.45 dBm
channel power adds up to 28.25 dBm output power. We can see that whereas
the ACPR reaches its specified limit of –45 dBc, the alternate-channel-power
ratio has large margins over its specification of –56 dBc. The effectiveness of
the impedance-controllable biasing scheme has been verified in these measure-
ments.
In this section, we have shown that it is possible to design a linear power
amplifier in standard Si-technology. A monolithic Si PCS-CDMA power am-
plifier was designed which was capable of delivering 28.2 dBm output power
RF power amplifiers 159
160 CIRCUIT DESIGN FOR RF TRANSCEIVERS

with 30% power-added efficiency (PAE) and –45 dBc adjacent-channel-power

ratio (ACPR) at 1.9 GHz and 3.6 V supply voltage. The PA was implemented
in a 30 GHz BiCMOS process.

5.3 CMOS PA DESIGN

We have seen in the previous section that monolithic Si bipolar power amplifiers
are capable of delivering output powers in the range of 25 dBm to 30 dBm. Many
wireless LAN standards require, however, lower output powers. The Bluetooth
communications protocol, for instance, has three classes of transmitter power
requirements: Class 1 (20 dBm), Class 2 (4 dBm) and Class 3 (0 dBm). The
low radio power requirements for this protocol have prompted heavy research
interest in the area of using CMOS to implement the RF power amplifier.
We will demonstrate a CMOS RF power amplifier capable of meeting the
requirement specifications of the Bluetooth Class 1 standard [13]. Since Blue-
tooth employs a constant envelope modulation scheme, we have focused on
achieving the required high saturated power while maximizing PAE. We have
set our goal to attain 20 dBm saturated output power with a gain of 20 dB and
an associated PAE of more than 35%.
We have employed a single-ended two-stage common-source topology with
on-chip interstage matching for the design of our power amplifier (Figure 5.15).
For accurate simulation purposes, we have used the RF MOS transistor models
as discussed in Chapter 1.
The supply voltage limit is 2.5 V for the CMOS technology. In the
design enough headroom has been alloted to allow for process/chip assembly
variations. This headroom is realized by designing the PA to achieve a required
 RF power amplifiers 161

output power of 24 dBm at 2 V supply. A 1.5 mm output stage biased close

to class A region has been used along with a 0.5 mm driver biased in deep
class AB region. These transistor dimensions are needed to deliver the output
power at a load impedance. Meeting the above specification would allow
direct interface on the same chip to the 0 dBm transceiver to meet the Class 1
transmission requirements. For a cost effective solution, we have minimized the
number of off-chip components and also avoided a flip-chip configuration. The
ground inductance on the MOSFET sources due to the bond wires was set at an
achievable value of 0.2 nH for both stages while performing these simulations.
Resistive gate biasing is adopted to prevent unwanted oscillations. We have
used the bondwire inductance for the driver stage drain connection along with
an on-chip ring capacitor structure to provide the interstage matching. Input and
output matching was done using lumped element components for simulation
purposes.
The simulated performance of this two stage design at 2 V supply voltage
is shown in Figure 5.16. The design can provide 31.5 dB of small-signal gain
and a saturated power of 24 dBm can be obtained with 55% PAE.
Special care has been taken to generate the layout of the chip. Both the driver
and output stages have been built up from a 20 finger interdigitated unit cell of
width resulting in a gate finger length of (see also Chapter
1) . The substrate is tied to the source of the unit cell to prevent any substrate
bias effects. The RF signal path is kept as short as possible between the stages
162 CIRCUIT DESIGN FOR RF TRANSCEIVERS

and multiple ground pads are used to minimize the ground inductance from
bondwires for the stages.
The 10 pF interstage matching capacitance has been formed with five 2
pF unit capacitors. We have designed a ring capacitor instead of using the
multilayer fringe capacitor structure as discussed in Chapter 1. The ring shaped
structure minimizes the occupied chip area (Figure 5.17). The ring capacitor
utilizes both the cross-over capacitance and the fringe capacitance between
multi-level interconnect metals in minimum geometry configurations in our
CMOS technology to achieve a high capacitance density (2 to 3 times) compared
to a conventional metal-sandwich structure.
Post-layout simulation results, which include the effect of parasitic capaci-
tances extracted from the layout are shown in Figure 5.18. As seen from this
figure, the most prominent effect of the parasitics is a degradation in the small
 RF power amplifiers 163

signal gain by almost 5 dB due to extra gate-drain capacitance for the two stages
from the layout. However, the original saturated power and PAE can still be
obtained using a higher input level.
The power amplifier was fabricated in a five metal level low resis-
tivity substrate CMOS process. The silicon was thinned down to
to help reduce the ground bondwire lengths. The die was then bonded
to the PCB using a conducting glue which also provides a well defined ground
to the backside of the chip. Bond wires were used to connect the bondpads to
the respective traces on the PCB as shown in Figure 5.19.
Large signal loadpull measurements were then performed on the power am-
plifier using a Focus Microwaves Loadpull system. Figure 5.20 shows the
measured output power and gain at 2.4 GHz for the power amplifier as a func-
tion of the input power level for three supply voltage levels. It can be seen that
the saturated output power of 22 dBm for a supply voltage of 2 V is about 2
dB lower than simulated results with an associated PAE of 47%. This is due
to a higher than designed value for the drain bondwire inductance of the driver
along with a slightly undersized driver stage which results in a premature power
gain drop-off. Both of these shortcomings can be easily remedied by a simple
redesign of the PCB and an increase in the size of the driver stage. For the
current design, at a supply voltage to 2.5 V, we can achieve a saturated output
power of +24 dBm. The output stage and the driver draw supply currents of
184 mA and 28 mA respectively at this output power level resulting in an asso-
164 CIRCUIT DESIGN FOR RF TRANSCEIVERS
 RF power amplifiers 165

ciated PAE of 48%. This is the same as the total drain efficiency since the gain
of the circuit is larger than 20 dB. A plot of the saturated output power and the
associated PAE is shown in Figure 5.21 as a function of the supply voltage.
Issues of significance in the area of RF CMOS power amplifier design in-
clude catastrophic gate oxide breakdown and the effect of hot carrier induced
device degradation on the RF performance of the amplifier. The hot carrier
effect is a phenomenon where under high electric fields near the drain, the
channel electrons can cause damage to the Si-SiO2 interface thereby increasing
threshold voltage, decreasing transconductance and degrading MOSFET per-
formance. So far, CMOS RF power amplifier papers have not reported on the
hot carrier effect even though they are operated at DC+RF voltage levels ex-
ceeding the recommended DC limit. Although DC/transient reliability testing
has been performed to study hot carrier induced degradation [14], [15], [16],
there have been no studies on hot carrier effects under large signal steady state
RF operation in CMOS.
We have studied the effect of hot carriers on the saturated output power of
the designed power amplifier. The supply voltage limit for this technology
from a hot carrier standpoint is 2.5 V DC. We operated our power amplifier at
166 CIRCUIT DESIGN FOR RF TRANSCEIVERS

Vdd=2.25 V to deliver 23 dBm initial output power. However, under saturated

large signal operation, the instantaneous RF voltage swing at the drain of our
transistor can reach upto 4.5 V (2 times well exceeding the DC limit for
this technology.
As seen from Figure 5.22, there is no catastrophic destruction of the power
amplifier. However, output power of the amplifier decreases with an exponential
time constant indicative of classical hot carrier degradation and levels off after
about 70 hours of testing indicating that all the created trap sites at the interface
have been filled by electrons. The original performance can be recovered by
increasing the gate bias. This indicates that the degradation is mainly due to an
increase in threshold voltage of the MOSFETs. An increase of the gate bias by
0.2 V results in a Pout of 22.9 dBm and a PAE of 46.5%.

5.4 LINEARIZATION PRINCIPLES

Several linearization techniques have been developed over the past few years
to enhance the linearity of existing power amplifiers. Linear power amplifiers
have become important, mainly due to the use of spectrally efficient modulation
schemes, where the envelope is varying. The need for multi-carrier base-station
transmitters instead of single-carrier base-station transmitters also raised the
need for linearization techniques. Multi-carrier systems are more flexible and
have lower costs than their single-carrier counterparts.
 RF power amplifiers 167

There are basically two principles for linearization: feedforward or additive

correction and feedback or multiplicative correction. Both techniques are shown
in Figure 5.23. In additive correction, the correction unit (CU) produces a
signal equal to assuming that and A is
the gain of the power amplifier. Consequently, the output signal is the linear
amplified input signal. The main drawback of this technique is that the summing
of signals takes place when the signals have been amplified. Summing of
high powers or voltages/currents is therefore needed, but is often difficult to
realize. Because additive correction is a feedforward loop, PA and CU must
track each other, meaning that one must monitor the PA and adapt the CU when
necessary, otherwise the summing will be on the wrong signals in time. An
advantage of this technique is the fact that the order of the total non-linearity does
not increase. This is in contrast to multiplicative correction, where the order
increases, because the CU is now in front of the PA and thus the non-linearity of
the CU is also amplified. The output signal is determined by • A

and, if F is implemented as a feedback loop, we obtain

where is the feedback gain.
It is worth noticing that, assuming a fixed maximum output power, lineariza-
tion gives lower efficiency values than when no linearization techniques are
used. Another important parameter is the adjacent channel power ratio, reflect-
ing the unwanted amount of power which is delivered in the adjacent channel.
168 CIRCUIT DESIGN FOR RF TRANSCEIVERS

If we fix this ratio, linearization techniques give better efficiency and allow
higher output powers.
In the following sections, we will discuss a few promising linearization tech-
niques, such as predistortion, phase-correction and envelope elimination and
restoration (EER). The list of examples is not exhaustive, but it gives a good
overview of the state-of-the-art in RF power amplifiers and transmitter concepts.

5.4.1 Predistortion Technique

The basic idea behind predistortion is to distort the signal with the image of the
spectral distortion behavior of the power amplifier. Amplifying this predistorted
signal using the PA results in a clean spectral output signal. This approach was
proposed by Stapleton [17]. The simplest method would be to use a non-linear
device in front of the amplifier, to produce the inter-modulation products in
anti-phase to those of the amplifier in open loop configuration. This non-linear
device can be placed in the RF part of the transmitter, and we refer to this princi-
ple as RF predistortion (see Figure 5.24). The advantage of RF predistortion is
in the simplicity of the circuits needed at the cost of limited performance. Due
to the wide band operation, both the intermodulation and harmonic distortion
can be tackled. As can be seen in Figure 5.24, the predistortion can also be
 RF power amplifiers 169

applied at IF or baseband, and is as such referred to as modulation predistor-

tion. In general, the predistortion works on complex signals and reduces the
inter-modulation harmonics. The main advantage is that the correction can be
done in the digital domain, resulting in low power consumptions. If the PD is
applied to the base band signal, and thus to the I and Q path, this technique is
sensitive to gain and phase unbalance. DC offset in the quadrature modulator
also influences the performance. If the PD is applied at IF, and thus after the
quadrature modulator, the imbalance of gain and phase do not play a significant
role. However, a costly IF and/or RF filter is required to shape the spectrum.
Let us assume that complex baseband predistortion is applied to linearize
the power amplifier. A possible block diagram is shown in Figure 5.25, where
different non-linear functions have been used for the in-phase and quadrature-
phase. The predistorter creates a signal the distorted version from the
modulated input signal The output of this signal due to amplification
is and this signal is fed back to the baseband by means of a bandpass
filter (BPF) to separate the out-of-band signal power from the wanted signal.
The out-of-band power is then averaged by the power detector and used by the
controller to generate the predistortion correction signals and both also
depending on the magnitude of the input signal. Assume

where
170 CIRCUIT DESIGN FOR RF TRANSCEIVERS

The controller controls the values for to The predistorter’s complex

gain can now found to be

and signal is derived as

From this expression, we can observe the dependency of to up to

the fifth degree. If the coefficients and are chosen properly, the third and
fifth order intermodulation distortion can be reduced. In a similar way as in
(5.12), let us define

for the envelope of a predistorted signal. We can model the amplifier’s complex
gain as

where coefficients and stem from the complex power series. Now the
output of the amplifier can be written as

Note that both and depend only on the power of their

input signals, but not on their phase. As y(t) in (5.21) contains only modu-
lated amplitude information, the equation describes amplitude modulation to
amplitude modulation (AM-AM) behavior. Because the coefficients are com-
plex, the equation also describes an amplitude modulation to phase modulation
(AM-PM) characteristic.
 RF power amplifiers 171

Combining (5.25) with (5.18) yields

and the complex gain of the overall system is found to be

On the other hand, we may model the whole amplifier by a complex power
series, and if we truncate after the fifth order term, we obtain

The output voltage is therefore also given by

and therefore, by equating (5.26) and (5.29)

Solving the right hand side of (5.30) and re-ordering the zeroth, first- and
second-order terms yields the relations

where denotes the complex conjugate of The third order term depends on
the amplifier gain coefficients and and the same holds for the fifth order
term plus the additional coefficient Therefore, by an appropriate choice of
the predistortion coefficients and it is possible to reduce or eliminate
the third- and fifth-order inter modulation products. The need of the feedback
loop in Figure 5.25 is now clear: the loop finds the appropriate values for the
coefficients and and automatically takes care of process and temperature
variations.
172 CIRCUIT DESIGN FOR RF TRANSCEIVERS

Figure 5.26 shows an example of measurement results when a broadband

predistortion technique is applied to a 30 W power amplifier and measured under
two tone conditions at 1.8 GHz. A 20 dB suppression of the third harmonic is
achieved. In Figure 5.27, a 120 W power amplifier for IS-95 CDMA was tested.
A 10 dB suppression is gained at an offset of 750 kHz. Both measurements
show that predistortion is a possible linearization technique for modest degrees
of linearity improvement.

5.4.2 Phase-Correcting Feedback

Suppose that the input to the power amplifier has a constant envelope and a
varying phase. The amplitude modulation is achieved by varying the supply
voltage. In such a configuration, the power amplifier can operate in class E. As
the supply voltage is varied to modulate the output voltage, the drain voltage of
 RF power amplifiers 173

the output transistor will also vary, see Figure 5.1. Consequently, the transistors’
capacitances will change, and thus the phase of the output signal changes. This
mechanism is an example of amplitude-to-phase modulation, and the resulting
phase distortion can be in the range of 20 to 40 degrees.
Utilizing a phase correcting feedback mechanism can help to reduce the
phase distortion to the level of a few degrees. A block diagram of this feedback
principle is shown in Figure 5.28. In this block diagram, it is not only the PA
which introduces AM-to-PM distortion, but also the limiting amplifier, needed
to limit the output of the PA to a fixed value. Let us denote the AM-to-PM
distortion for the PA by and for the limiting amplifier by where
is the Laplace operator. Define the phase of the input signal and output signal
as and respectively. Finally, assume a first order low pass loop
174 CIRCUIT DESIGN FOR RF TRANSCEIVERS

filter to have a first order feedback loop with a transfer function H(s), resulting
in a feedback loop transfer equal to

The system is therefore stable. Constant K represents the sensitivity of the

phase detector and the phase shifter together. The relationship between the
input and output phase is now given as

with the error signal

Because H(s) has a lowpass transfer characteristic, the loop appears as a high-
pass filter for the distortion of the PA. The pole of the filter must be placed such
that the bandwidth of the filter is larger than the bandwidth of the amplitude
 RF power amplifiers 175

modulated signal. Suppose that this amplitude modulated signal has a band-
width of 50 kHz. Then setting the loop filter bandwidth to 200 kHz means that
the loop transfer characteristic can be approximated by where
is the filter gain. The PA distortion is therefore reduced by a factor
The phase error due to the limiting amplifier only has a minor attenuation of
Assuming to be equal to 20, then the phase distortion of 20
and 40 degrees reduces to 0.95 and 1.9°. Assuming a maximum phase error at
the output, then the maximum allowed phase error of the limiting amplifier can
be found from (5.34).
An example of phase-correcting feedback can be found in [18]. The design
was realized in a GaAs MESFET process. The limiting amplifier
consists of a series-parallel limiting cell followed by several saturating gain
stages as shown in Figure (5.29). The limiting cell contains a passive stage
consisting of two back-to-back parallel diodes (M3 and M4) and a resistor
(M1 and M2). A passive stage is needed, since the output of a PA can swing
higher than the supply voltage. For positive voltages, M1 acts as a diode-
connected MESFET while M2 behaves like a current source. Similarly, for
negative voltages, M2 acts as a diode-connected MESFET while M1 behaves
like a current source. For small signal levels M1 and M2 behave like a resistor.
Phase errors in the order of 1 to 2° can be achieved at a reasonable power
dissipation. The saturated gain stage must ensure that the output voltage has a
fixed level for all input values. Several stages are usually needed. Each stage is
176 CIRCUIT DESIGN FOR RF TRANSCEIVERS

based on an inverter and is AC coupled to the next stage by means of capacitor

C. Together with resistor R, the capacitor determines the load of the previous
stage and provides a relatively constant load under amplitude variations.
The phase detector is based on a Gilbert active mixer configuration as de-
picted in Figure 5.30. Capacitors C are implemented on-chip to provide small
high frequency loads for M1 to M2 and M3 to M4, which act as switches. The
resistors R provide large loads for the DC component of the switched current.
If the phase difference between and is 90°, then the differential output
equals zero. When both input signals are in-phase or 180 degrees out of
phase, each mixer is completely turned on and the output reaches its maximum
absolute value. The sensitivity of the phase detector is given by

where I is the current through the resistor.

The phase shifter is based on a varactor-tuned LC network to retain the am-
plitude of the signal waveform. Two such networks are used, one connected
to the source and one to the drain of a MESFET. The resonant frequency in
the drain-tuned circuit will increase while that of the source-tuned network de-
creases. Consequently, a negative phase shift is obtained in the source network
and an equal positive phase shift in the drain network.
 RF power amplifiers 177

A microphotograph of the feedback loop is shown in Figure 5.31. To reduce

parasitics, interconnections were laid out in the highest metal layer. The power
amplifier, in this case a class E end stage preceded by a class F stage, is on a
separate module. Measurement results on the complete system are shown in
Figure (5.32). For a load, the amplifier delivers more than 400 mW at
2.4 V supply voltage. The efficiency is above 60%, but drops rapidly for the
phase-corrected system if the supply voltages decreases The power amplifier
has a phase error of more than 20 degrees. The feedback loop reduces this error
to 4 degrees. Phase corrected feedback loops clearly help to reduce the resulting
phase error due to the power amplifier. The additional power consumption due
to the loop is in the order of 20 mW.

5.4.3 Envelope Elimination and Restoration (EER)

The principle of first eliminating the envelope of the RF input signal to generate
a constant-amplitude signal which is passed through a non-linear PA, while in
the meantime extracting the amplitude information, amplifying it separately
and then recombining it with the phase information, dates back to the fifties
[19], [20]. Because a constant amplitude signal passes through the non-linear
amplifier, the phase information will hardly be distorted. A switched mode
power amplifier can therefore be used, allowing high efficiency figures. The
extracted amplitude information passes through a highly linear amplifier, but
because this signal does not contain any RF component, the realization of such
an amplifier is simplified. A simplified block diagram of envelope elimination
178 CIRCUIT DESIGN FOR RF TRANSCEIVERS

and restoration (EER) is shown in Figure 5.33. A switching power supply has
been used to amplify the low frequency amplitude information. Recombination
of phase and magnitude has been realized by direct modulation of the power
supply of the power amplifier. A feedback path closes the loop and guarantees
tracking between the RF output amplitude and RF input signal. In this way,
errors introduced by the switching power supply block and mismatches between
the phase and magnitude paths, can be eliminated.
There are some possible drawbacks in this concept. Firstly, the limiting am-
plifier can introduce AM-to-PM errors, from which this system cannot recover.
Secondly, there are two signal paths and the delay in the RF signal path (i.e. the
phase path) is substantially shorter than that of the low frequency magnitude
path. This delay causes intermodulation distortion and, for two equal input
tones, this distortion is expressed by
 RF power amplifiers 179

where BW is the bandwidth of the RF signal, and is the delay mismatch.

For two tones that are 200 kHz apart and a required IM of –40 dBc, this yields
a maximum delay of 200 ns. Thirdly, the bandwidth of the switching power
amplifier is related to its efficiency. For high efficiency figures, this bandwidth
is rather small, in the order of a few tenths of kHz.
Su demonstrated that the concept of EER can work pretty well [21]. They
implemented the envelope detector, limiting amplifier, attenuator and switching
power supply in a CMOS technology and tested the concept on three
different amplifiers. They considered the performance of a 3.3 V GaAs PA
under AMP conditions (Figure 5.34). Under normal conditions, this PA can
reach 40% efficiency (peak PAE). However, to fulfil the linearity requirements
of the North American Digital Cellular (NADC) standard (employing
modulation), the PA must be backed off by 4 dB, yielding a PAE of
16% at 25 dBm output power,.(see cross mark in Figure 5.34). Using the EER
concept, this PA can reach a PAE of 35% at 29 dBm output power. A similar
improvement can be seen with a 4.8V GaAs PA (see Figure 5.34). In [21]
a CMOS PA was also tested under EER conditions. A measured
constellation diagram under normal conditions was compared to the diagram
in the case of EER. The linearized system achieved a phase error of 1.3° rms,
and a magnitude error of 2.5% rms.
180 CIRCUIT DESIGN FOR RF TRANSCEIVERS

5.4.4 Cartesian Feedback

The last technique to be discussed is an example of modulation feedback called
Cartesian feedback. At the output of the amplifier, the transmitted signal is
decomposed into the distorted I and Q signals This information is then used
to adapt the I and Q signals at the input of the amplifier. A schematic of this
approach is shown in Figure 5.35.
The feedback loop has a delay compared to the direct signal path. A phase
shifter is therefore needed in the feedback path. The delay in the loop limits
the bandwidth over which the loop can operate. A few 100 kHz bandwidth can
normally be achieved, allowing this technique to be used in telecommunica-
tion standards with a relatively small channel bandwidth and spacing, such as
DAMPS for instance. As an example, measurement results for
this standard are depicted in Figure 5.36 and 5.37. A 30 dB improvement has
been achieved.
 RF power amplifiers 181

Although measurements show good results, there are some major problems
when using Cartesian feedback loops. Classical Cartesian feedback is a ho-
modyne solution technique. As in Figure 5.35, the VCO operates at the same
frequency as the PA, which gives the potential problem of pulling. The output
182 CIRCUIT DESIGN FOR RF TRANSCEIVERS

of the PA couples back to the VCO. A super heterodyne solution can be used
to prevent this, requiring a band-pass filter. Due to the required suppression,
SAW-filters are needed which introduce large delays and we end up with a small
modulation bandwidth of a few hundred Hertz. Besides the problem of the loop
bandwidth, SAW filters are discrete components and are expensive.

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184 CIRCUIT DESIGN FOR RF TRANSCEIVERS

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