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Parity Genr & Check Expt7

This document describes the implementation of a 3-bit parity generator and checker. It defines a parity bit as an extra bit that makes the total number of 1s in a binary message either even or odd. A parity generator is used at the transmitter to generate the parity bit, while a parity checker is used at the receiver to detect errors. It provides truth tables and logic equations for a 3-bit odd parity generator and checker. The conclusion states that a 3-bit odd parity generator and checker were implemented and verified using the Logisim software.

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Kaji Kin
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397 views3 pages

Parity Genr & Check Expt7

This document describes the implementation of a 3-bit parity generator and checker. It defines a parity bit as an extra bit that makes the total number of 1s in a binary message either even or odd. A parity generator is used at the transmitter to generate the parity bit, while a parity checker is used at the receiver to detect errors. It provides truth tables and logic equations for a 3-bit odd parity generator and checker. The conclusion states that a 3-bit odd parity generator and checker were implemented and verified using the Logisim software.

Uploaded by

Kaji Kin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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OBJECTIVE:- IMPLEMENTATION OF 3 BIT PARITY GENERATOR AND CHECKER

EQUIPMENT REQUIRED

1. Power Supply
2. Computer
3. Logisim

THEORY

Parity Bit:- A parity bit is an extra bit in any binary message to make the total number of 1’s either odd or
even. We need to add the parity bit to a signal. This is done by the Parity generator.

Parity Generator:- A parity generator is a combinational logic circuit we use in the generation of the
parity bit. It is present at the transmitter end to generate the parity bit. Later it combines with the message
signal.

Parity Checker:- A parity checker is a circuit that checks the parity (number of 1s) of the message signal.
The Parity checker is present at the receiver end for error detection through parity bit count.

3-bit Odd Parity Generator

Suppose at the transmitting end now we have a 3-bit message signal, and we wish to transmit it using odd
parity. Then, the parity bit generated, P, would be as a result of odd parity generation. The total number of
1s in the input bits must be odd for the odd parity bit. If the total number of 1s in input bits is odd, then P
gets the value 0, and if it is even then, P is assigned the value 1.

Truth Table

3 Bit Message Odd Parity Bit Generator


A B C P
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

Solving the truth table for all the cases where P is 1 using Sum-of-Products method:

P = A ⊕ (B ʘ C)
3 Bit Odd Parity Checker 

Suppose at the transmitting end odd parity bit is generated, and we have three input message signal. The
parity checker circuit is fed all these four bits to check for possible errors. Since the transmitting end is
working with odd parity, the number of 1’s at received by the checker circuit must be odd.

An error occurs on the even number of 1’s at the receiver’s end; that is, the message signal has become
distorted.

Truth Table

4 Bit Received Message Parity error check Cp


A B C P Cp
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

If the four-bit received message consists of an odd number of 1 means, no error has occurred. If it
contains an even number of 1 means, an error has occurred.

E=AʘBʘCʘD

OBSERVATION
 Implementation of 3 bit parity generator

 Implementation of 3 bit parity checker

CONCLUSION

Hence, 3 bit odd parity generator and checker is generated and verified using Logisim.

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