Improved LDMOS for ESD Protection of High Voltage

BCD Process
SHEN Hong-yu, DONG Shu-rong*,XU Ze-kun, HU Tao, Guo Wei, Huang Wei
1
ESD Lab, College of Information Science and Electronic Engineering, Zhejiang University，Hang Zhou , Zhe Jiang 310027,China

Abstract-LDMOS is widely used as an ESD protection device. In high

voltage BCD technology. However, due to the use of low
concentration medium voltage well in HV process, the LDMOS is
easily damaged by the Kirk effect under ESD stress, and the
robustness is very low. A novel LDMOS is proposed in this work by
using a high concentration well to surround the drain intraditional
LDMOS, which, achieves a high ESD robustness with a current level
of 0.76A,and the Ron is reduced from the original 25Ω to 6.25Ω. In
other hand ,in order to save the area, the conventional LDMOS-SCR
has been improved by the drain terminal segment, which make the
improved LDMOS-SCR maintain a high robustness while the device
area is smaller than that of the conventional LDMOS-SCR, thereby
improving the area efficiency. Fig.1 conventional LDMOS
Keywords-ESD ， LDMOS ， LDMOS-SCR ， High Voltage BCD
Process，robustness. However, due to the use of low-concentration medium-voltage
wells in the LDMOS structure, LDMOS is easily damaged by the
Kirk effect [10] under ESD stress, and the robustness is very low.
I． Introduction The Kirk effect means that under transient high current, the
boundary of the depletion region in the low concentration MVNW
High-voltage (HV) integrated circuit (IC) in Bipolar-CMOS will advance to below the N+ region of the drain, forming a strong
DMOS (BCD) technology are extensively used for power electric field region and causing breakdown damage. Fig.2 shows
management applications, automotive electronics, display driver a typical TLP test curve of 12V LDMOS. An obvious feature is
circuits and so on [1-3]. The electrostatic discharge (ESD) is a that the device is broken after a hysteresis, and the secondary
tough issue for HV IC [4]. Because HV ICs generally operate in breakdown current is only 0.26A. A common way to enhance
high current and high voltage environments, the reliability of the conventional LDMOS is to increase the width of the device. Due
device is very high, which requires full consideration of on-chip to the comprehensive consideration of current drive capability and
ESD protection. Laterally-diffused metal–oxide semiconductor ESD protection capability, the width of LDMOS sometimes needs
(LDMOS) transistors are often used as output drivers. What is thousands of μm. A novel scheme that can improve the robustness
more, LDMOS transistors are also widely used as ESD protection of LDMOS without increasing device area is proposed in this
devices [1-2]. However, the efficiency of LDMOS used as ESD paper.
protection device is vulnerable to ESD stresses, which are often
due to the inhomogeneous triggering of the parasitic bipolar
junction transistor (BJT) and base push out effect. [5]
The n-LDMOS structure which commonly used for high
voltage I/O is shown in Fig.1, The difference with normal NMOS
is that a medium voltage N-Well (MVNW) and a medium voltage
P-Well (MVPW) are used in n-LDMOS .Compared with
conventional NW and PW, MVNW and MVPW have lower
doping concentrations, so the withstand voltage capability under
DC is improved. [6-8]High-voltage BCD process can have a
variety of operating voltage devices according to actual needs,
such as 12V, 24V, 40V. The higher the operating voltage, the
lower the concentration of the well used.[9] Under different
processes, the STI part may be replaced by field oxygen isolation.
It is also because of the high withstand voltage of the BCD process
that it is widely used as the main process for the fabrication of high
voltage devices.

Fig .2 Typical TLP test curve of LDMOS under HV BCD process

Authorized licensed use limited to: Viettel Group. Downloaded on December 29,2020 at 02:34:52 UTC from IEEE Xplore. Restrictions apply.
 II． Improved LDMOS with N-Well

From the analysis of the cause of LDMOS failure, the low

robustness of the basic LDMOS structure under ESD stress is
mainly due to the propulsion of the depletion region under high
current, and the root cause of this failure is the low doping of the
medium voltage N-well Therefore, it is conceivable to cover the
N+ region of the drain terminal with NW having a concentration
higher than MVNW, so that when the boundary of the depletion
region in the MVNW is advanced to the MVNW/NW boundary,
the propulsion speed is slowed, thereby delaying the occurrence of
breakdown damage. In turn, the robustness of LDMOS under ESD
stress is increased.Fig.3 is a schematic diagram of the improved
LDMOS structure.

Fig.4 LDMOS TLP curve with or w/o N-Well

Fig.3 LDMOS with NW at the drain terminal

Fig.4 shows the TLP test results for 12V conventional LDMOS
and LDMOS with NW at the drain terminal. It can be seen that the
trigger voltages of the two structures are all about 17.5V.
However, the It2 increased significantly from the 0.26A to 0.76A,
which is nearly three times that of the original. In addition, the Ron
has been reduced from the original 25Ω to 6.25Ω, which is only a
quarter of the original. At the same time, in order to confirm the
DC voltage resistance of the LDMOS containing the NW at the
drain terminal, we performed a DC voltage scan. As shown in Fig.
5, it can be seen that the breakdown voltage under DC voltage is
Fig.5 DC I-V plot of LDMOS with NW at the drain terminal
about 17.5V. In summary, the LDMOS with NW at the drain
terminal does not deteriorate the DC characteristics, can safely
withstand the operating voltage of 12V, and at the same time can
improve the robustness by nearly 3 times compared with the III． Drain-terminal Segmented LDMOS-SCR
conventional LDMOS.
It can be seen from the results of the TLP test that the LDMOS Another improvement is derived from LDMOS-SCR, which
with NW at the drain terminal is positively enhanced in both inserts a P+ implant between the drain and gate of the LDMOS to
robustness and Ron, and this is attributed to the fact that the Kirk form a SCR path, thereby significantly reducing the holding
effect of the original LDMOS is weakened by the addition of NW. voltage. The layouts of LDMOS and LDMOS-SCR are shown in
The most worrying aspect in the process of device improvement is Fig. 6.An extra P+ stripe is inserted in the left of N+ region at the
the effect on the DC characteristics of the device after the addition drain side of LDMOS-SCR in contrast to LDMOS, thus the
of NW. Since the doping concentrations of MVNW and MVPW in LDMOS-SCR has a special current discharge path through the
the LDMOS are lower than those of the conventional NW and PW, parasitic SCR and its Vh can be significantly reduced.[11]
the withstand voltage capability under direct current is improved.
As mentioned before, the high-voltage BCD process can have
multiple operating voltage devices, depending on actual needs.
The higher the operating voltage, the lower the concentration of
the well used. Therefore, the introduction of NW may weaken the
DC withstand voltage capability of the device, resulting in its
inability to operate at normal operating voltages. Fortunately, DC
voltage scanning the 12V LDMOS with NW at the drain terminal
has a breakdown voltage of 17.5V. This shows that adding NW to
LDMOS can improve the ESD performance of the device while
ensuring DC compression capability. Whether this improved idea
can be more widely applied to improve the ESD performance of
medium voltage well devices is worthy of further investigation.
Fig 6 Layout of the experimental devices. (a)LDMOS and(b) LDMOS-SCR

Authorized licensed use limited to: Viettel Group. Downloaded on December 29,2020 at 02:34:52 UTC from IEEE Xplore. Restrictions apply.
 However, due to the robustness problem, the conventional hysteresis SCR path with a secondary failure current of about
LDMOS-SCR adopts a multi-finger structure to improve the 1.6A.Therefore, the drain-terminal segmented LDMOS-SCR can
robustness of the device, which results in a greatly increased reduce the single device area while maintaining the strong
layout area of the LDMOS-SCR device compared to the original robustness of the conventional LDMOS-SCR. In addition, the
LDMOS. In order to minimize the device area while ensuring that trigger voltage of both device structures is about 25V, and the
the robustness of the device is not impaired, a new LDMOS-SCR device has a significant snap-back after it is turned on. Compared
structure is needed with the conventional LDMOS-SCR, the drain-terminal
As shown in Fig. 7(a), the double-finger LDMOS-SCR in the segmented LDMOS-SCR is more stable, and the Ron of the two is
form of a regular layout. Compared to the conventional LDMOS 5.5Ω and 6.1Ω.
structure, the layout area is increased due to the addition of two P+ However, the holding voltage of two types of LDMOS-SCR are
implants. In order to save the area, the LDMOS structure of the around 5V, which is generally lower than the operating voltage of
source-drain segment shown in Figure 7(b) is proposed. the device under the high-voltage BCD process, which may cause
latch-up problems. How to maintain the high robustness of
LDMOS-SCR while effectively improving the latch-up resistance
remains to be further studied.

Fig.7 double-finger LDMOS-SCR(a) and drain-terminal segmented

LDMOS-SCR(b)

In this paper, based on the double-finger LDMOS-SCR, a layout

optimization method for segmenting the drain-terminal is
Fig.8 TLP curve of conventional LDMOS, LDMOS-SCR and drain-terminal
proposed, so that the LDMOS-SCR structure can be formed segmented LDMOS-SCR
without increasing the area of the conventional LDMOS structure.
The design of this new structure is to make full use of the vertical
area of the layout, and to change the originally horizontally
arranged drain to a longitudinal segmented structure. This not only IV． Conclusions of the Study
ensures that the parasitic SCR structure can be formed to improve
the robustness, but also reduces the layout area. Here is an example In this paper, based on the shortcomings of the weak robustness
of analyzing a single interdigital finger. of the LDMOS under the high voltage BCD process, the Kirk
When the device is subjected to a strong ESD pulse, it will effect of n-LDMOS is weakened by using NW to surround the N+
experience three different regions of operation.（1）Reverse PN region of the drain terminal, which enhances the robustness of the
breakdown region: the PN junction formed by P-Body/DNW has device. From the TLP test results, The robustness of LDMOS with
breakdown first, the ESD induced transient current goes through NW is increased by 3 times, and the Ron is only a quarter of the
DNW and P-Body. (2) Parasitic bipolar region: as the voltage original. By improving the LDMOS-SCR by the drain terminal
drops on the P-Body resistance is about 0.8 V, the N+ implantation segment, it maintains the robustness of the conventional
in source terminal begins to inject electrons into P-Body and the LDMOS-SCR while reducing the individual device area.
electrons that transit the P-Body are collected by DNW. Then the However, since the holding voltage of the two types of
bipolar transistor formed by N+ implant region, P-Body and DNW LDMOS-SCR is about 5V, it is still possible to cause latch-up
begins to conduct. (3) SCR region: As the ESD induced current problems. Therefore, how to improve the low holding voltage of
increases further, the electrons drift in the N-Body will cause LDMOS-SCR requires further research.
severe impact ionization which leads to the avalanche injection
near the drain terminal N+ implantation. The holes generated by
avalanche impact ionization will drift to the P+ implant region Acknowledgments
from its left side. Then the P+ implant region can inject holes into
the N-Body, from its right side, which leads to the parasitic SCR This work was supported by the following programs: National
formed by P+ implant region, N-Body, P-Body and source N+ Natural Science Foundation of China (Nos. U1613202,
implant region conducting. [12]It can be seen that the device can U1609210) ,Zhejiang science and technology plan
still form a complete LDMOS-SCR device structure after No.2018C01037.We would like to acknowledge the kindly
segmenting the drain terminal. technical support from ESDEMC Technology LLC.
Fig.8 shows the TLP testing results. It can be seen that the
conventional LDMOS-SCR and the drain-terminal segmented
LDMOS-SCR have similar performances, and can form a deep
Authorized licensed use limited to: Viettel Group. Downloaded on December 29,2020 at 02:34:52 UTC from IEEE Xplore. Restrictions apply.
 REFERENCES

[1] Ker, Ming Dou , and K. H. Lin . "Double Snapback Characteristics in

High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection
Design." Electron Dev Lett, IEEE, 25 (2004), pp. 640-642
[2] J. Zheng, Y. Han, H. Wong, B. Song, S. Dong, F. Ma, et al. "Robust and
area-efficient nLDMOS-SCR with waffle layout structure for high-voltage
ESD protection." Electron Lett, 48 (2012), pp. 1629-1630
[3] Q. Li, W.D. Wang, H.O. Li, X.M. Wei “High voltage silicon power device
structure with substrate bias. “Electron Lett, 47 (2011), pp. 1394-1396
[4] Tai-Hsiang L, Lu-An C, Tien-Hao T, Kuan-Cheng S. Design of modified ESD
protection structure with low-trigger and high-holding voltage in embedded
high voltage CMOS process. in: 2011 IEEE international reliability physics
symposium (IRPS); 2011. p. 4C.1.1–4.
[5] K Keppens B, Mergens MPJ, Cong Son T, Russ CC, Van Camp B, Verhaege
KG. ESD protection solutions for high voltage technologies. Electrical
overstress/electrostatic discharge symposium; 2004. EOS/ESD‘04.2004. p.
1-10.
[6] Duvvury, Charvaka,et al. "Lateral DMOS design for ESD robustness."
International Electron Devices Meeting IEEE, 1993.
[7] Liu Zhiwei, J.J. Liou. "Silicon-Controlled Rectifier Stacking Structure for
High-Voltage ESD Protection Applications." IEEE Electron Device Letters
31.8(2010):845-847.
[8] A. Gendron, G. Chai "New high voltage ESD protection devices based on
bipolar transistors for automotive applications." Electrical
Overstress/electrostatic Discharge Symposium IEEE, 2011.
[9] M.P.J. Mergens "Analysis of lateral DMOS power devices under ESD stress
conditions." IEEE Trans Electron Dev, 47 (2000), pp. 2128-2137.
[10] A. W. Ludikhuize, "Kirk effect limitations in high voltage IC's," in Power
114Semiconductor Devices and ICs International Symposium, Davos, 1994,
pp. 249-252.
[11] Liang H , Gu X , Xiao S , et al. A modified LDMOS device with improved
ESD protection performance[J]. 2014, 9(6):700-702.
[12] Jie Zeng, Shurong Dong, Lei Zhong, Guo Wei, Yan. Han, Weicheng. Liu, et
al.,"An area-efficient LDMOS-SCR ESD protection device for the I/O of
power IC application," Microelectronics Reliability, vol. 54, pp. 1173-1178,
Jun-Jul 2014.

Authorized licensed use limited to: Viettel Group. Downloaded on December 29,2020 at 02:34:52 UTC from IEEE Xplore. Restrictions apply.