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LM25085, LM25085-Q1
SNVS593J – OCTOBER 2008 – REVISED NOVEMBER 2014

LM25085 / -Q1 42V Constant On-Time PFET Buck Switching Controller

1 Features 3 Description
1• LM25085-Q1 is an Automotive Grade product that The LM25085 is a high efficiency PFET switching
is AEC-Q100 Grade 1 Qualified (-40°C to 125°C regulator controller that can be used to quickly and
easily develop a small, efficient buck regulator for a
Operating Junction Temperature)
wide range of applications. This high voltage
• Wide 4.5V to 42V Input Voltage Range controller contains a PFET gate driver and a high
• Adjustable Current Limit Using RDS(ON) or a voltage bias regulator which operates over a wide
Current Sense Resistor 4.5V to 42V input range. The constant on-time
• Programmable Switching Frequency to 1MHz regulation principle requires no loop compensation,
simplifies circuit implementation, and results in ultra-
• No Loop Compensation Required fast load transient response. The operating frequency
• Ultra-Fast Transient Response remains nearly constant with line and load variations
• Nearly Constant Operating Frequency with Line due to the inverse relationship between the input
and Load Variations voltage and the on-time. The PFET architecture
allows 100% duty cycle operation for a low dropout
• Adjustable Output Voltage from 1.25V voltage. Either the RDS(ON) of the PFET or an external
• Precision ±2% Feedback Reference sense resistor can be used to sense current for over-
• Capable of 100% Duty Cycle Operation current detection.
• Internal Soft-Start Timer Device Information(1)
• Integrated High Voltage Bias Regulator PART NUMBER PACKAGE BODY SIZE (NOM)
• Thermal Shutdown LM25085-Q1 HVSSOP (8) 3.00 mm x 3.00 mm
VSSOP (8) 3.00 mm x 3.00 mm
2 Applications LM25085 WSON (8) 3.00 mm x 3.00 mm
• Automotive Infotainment HVSSOP (8) 3.00 mm x 3.00 mm
• Battery/Super Capacitor Chargers (1) For all available packages, see the orderable addendum at
• LED Drivers the end of the datasheet.

Simplified Schematic

4.5V to 42V CVCC

Input LM25085
VIN VIN VCC
CADJ
CIN
ADJ
GND RT RADJ
PGATE L1
Q1
SHUTDOWN RT
VOUT
ISEN
COUT
D1 Cff RFB2
GND
GND
FB

RFB1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM25085, LM25085-Q1
SNVS593J – OCTOBER 2008 – REVISED NOVEMBER 2014 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 12
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 16
3 Description ............................................................. 1 8 Application and Implementation ........................ 17
4 Revision History..................................................... 2 8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 17
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 24
6.1 Absolute Maximum Ratings ..................................... 4 10 Layout................................................................... 24
6.2 Handling Ratings - LM25085 .................................... 4 10.1 Layout Guidelines ................................................. 24
6.3 Handling Ratings - LM25085-Q1 .............................. 4 10.2 Layout Example .................................................... 24
6.4 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 25
6.5 Thermal Information .................................................. 4 11.1 Device Support .................................................... 25
6.6 Electrical Characteristics........................................... 5 11.2 Related Links ........................................................ 25
6.7 Typical Characteristics .............................................. 7 11.3 Trademarks ........................................................... 25
7 Detailed Description ............................................ 11 11.4 Electrostatic Discharge Caution ............................ 25
7.1 Overview ................................................................. 11 11.5 Glossary ................................................................ 25
7.2 Functional Block Diagram ....................................... 11 12 Mechanical, Packaging, and Orderable
Information ........................................................... 25

4 Revision History
Changes from Revision I (April 2013) to Revision J Page

• Added Device Information and Handling Rating tables, Feature Description, Device Functional Modes, Application
and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and
Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section ............. 1

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5 Pin Configuration and Functions

HVSSOP-PowerPad™
8-Lead DGN0008A WSON
Top View 8-Lead NGQ0008A
Top View
Exposed Pad on Bottom
Connect to Ground
ADJ 1 8 VIN

ADJ 1 8 VIN RT 2 7 VCC

RT 2 7 VCC

FB 3 6 PGATE FB 3 6 PGATE

GND 4 5 ISEN
GND 4 5 ISEN

VSSOP Exposed Pad on Bottom

8-Lead DGK0008A Connect to Ground
Top View

ADJ 1 8 VIN

RT 2 7 VCC

FB 3 6 PGATE
GND 4 5 ISEN

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Current Limit Adjust - The current limit threshold is set by an external resistor from VIN to ADJ in
ADJ 1 I
conjunction with the external sense resistor or the PFET’s RDS(ON).
On-time control and shutdown - An external resistor from VIN to RT sets the buck switch on-time and
RT 2 I
switching frequency. Grounding this pin shuts down the controller.
Voltage Feedback from the regulated output - Input to the regulation and over-voltage comparators.
FB 3 I
The regulation level is 1.25V.
GND 4 - Circuit Ground - Ground reference for all internal circuitry.
Current sense input for current limit detection. Connect to the PFET drain when using RDS(ON) current
ISEN 5 I
sense. Connect to the PFET source and the sense resistor when using a current sense resistor.
PGATE 6 O Gate Driver Output - Connect to the gate of the external PFET.
Output of the gate driver bias regulator - Output of the negative voltage regulator (relative to VIN) that
VCC 7 O biases the PFET gate driver. A low ESR capacitor is required from VIN to VCC, located as close as
possible to the pins.
Input supply voltage - The operating input range is from 4.5V to 42V. A low ESR bypass capacitor
VIN 8 I
must be located as close as possible to the VIN and GND pins.
Exposed Pad - Exposed pad on the underside of the package (HVSSOP-PowerPAD-8 and WSON
EP -
only). This pad is to be soldered to the PC board ground plane to aid in heat dissipation.

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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
See MIN MAX UNIT
VIN to GND -0.3 45 V
ISEN to GND -3 VIN + 0.3 V
ADJ to GND -0.3 VIN + 0.3 V
RT, FB to GND -0.3 7 V
VIN to VCC, VIN to PGATE -0.3 10 V

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.

6.2 Handling Ratings - LM25085

MIN MAX UNIT
Tstg Storage temperature range -65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2
kV
pins (1)
V(ESD) Electrostatic discharge
Charged device model (CDM), per JEDEC specification 750
V
JESD22-C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Handling Ratings - LM25085-Q1

MIN MAX UNIT
Tstg Storage temperature range -65 150 °C
Human body model (HBM), per AEC Q100-002 (1) 2 kV
V(ESD) Electrostatic discharge Charged device model (CDM), per Corner pins 1, 4, 5, 8 750
V
AEC Q100-011 Other pins 750

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Voltage 4.5 42 V
Junction Temperature −40 125 °C

6.5 Thermal Information

LM25085 LM25085 / LM25085
Q-1
THERMAL METRIC (1) VSSOP HVSSOP- WSON UNIT
PowerPAD
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 153 54.1 44.8
RθJC Junction-to-case (top) thermal resistance 52.5 49.1 39.4
RθJB Junction-to-board thermal resistance 71.9 26.7 11.6
°C/W
ψJT Junction-to-top characterization parameter 4.6 1.3 0.3
ψJB Junction-to-board characterization parameter 70.8 26.5 11.6
RθJC(bot) Junction-to-case (bottom) thermal resistance 29 3.6 5.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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6.6 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature
range, unless otherwise stated. VIN = 24V, RT = 100kΩ unless otherwise stated. (See (1)).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN PIN
(2)
IIN Operating Current Non-Switching, FB = 1.4V 1.25 1.75 mA
(2)
IQ Shutdown Current RT = 0V 175 300 µA
(3)
VCC REGULATOR
VCC(reg) VIN - VCC Vin = 9V, FB = 1.4V, ICC = 0mA 6.9 7.7 8.5 V
Vin = 9V, FB = 1.4V, ICC = 20mA 7.7 V
Vin = 42V, FB = 1.4V, ICC = 0mA 7.7 V
UVLOVcc VCC Under-Voltage Lock-Out VCC Increasing 3.8 V
Threshold
UVLOVcc Hysteresis VCC Decreasing 260 mV
VCC(CL) VCC Current Limit FB = 1.4V 20 40 mA
PGATE PIN
VPGATE(HI) PGATE High Voltage PGATE Pin = Open VIN -0.1 VIN V
VPGATE(LO) PGATE Low Voltage PGATE Pin = Open VCC VCC+0.1 V
VPGATE(HI)4.5 PGATE High Voltage at Vin = 4.5V PGATE Pin = Open VIN -0.1 VIN V
VPGATE(LO)4.5 PGATE Low Voltage at Vin = 4.5V PGATE Pin = Open VCC VCC+0.1 V
IPGATE Driver Output Source Current VIN = 12V, PGATE = VIN - 3.5V 1.75 A
Driver Output Sink Current VIN = 12V, PGATE = VIN - 3.5V 1.5 A
RPGATE Driver Output Resistance Source current = 500mA 2.3 Ω
Sink current = 500mA 2.3 Ω
CURRENT LIMIT DETECTION
IADJ ADJUST Pin Current Source VADJ = 22.5V 32 40 48 µA
VCL OFFSET Current Limit Comparator Offset VADJ = 22.5V, VADJ - VISEN -9 0 9 mV
RT PIN
RTSD Shutdown Threshold RT Pin Voltage Rising 0.73 V
RTHYS Shutdown Threshold Hysteresis 50 mV
ON-TIME
tON – 1 On-Time VIN = 4.5V, RT = 100kΩ 3.5 5 7.15 µs
tON – 2 VIN = 24V, RT = 100kΩ 560 720 870 ns
tON - 3 VIN = 42V, RT = 100kΩ 329 415 500 ns
tON - 4 Minimum On-Time in Current Limit VIN = 24V, 25mV Overdrive at ISEN 55 140 235 ns
(4)

OFF-TIME
(4)
tOFF(CL1) Off-Time (Current Limit) VIN = 12V, VFB = 0V 5.35 7.9 10.84 µs
tOFF(CL2) VIN = 12V, VFB = 1V 1.42 1.9 3.03 µs
tOFF(CL3) VIN = 24V, VFB = 0V 8.9 13 17.7 µs
tOFF(CL4) VIN = 24V, VFB = 1V 2.22 3.2 4.68 µs
REGULATION AND OVER-VOLTAGE COMPARATORS (FB PIN)
VREF FB Regulation Threshold 1.225 1.25 1.275 V
VOV FB Over-Voltage Threshold Measured With Respect to VREF 350 mV
IFB FB Bias Current 10 nA

(1) All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
(2) Operating current and shutdown current do not include the current in the RT resistor.
(3) VCC provides self bias for the internal gate drive.
(4) The tolerance of the minimum on-time (tON-4) and the current limit off-times (tOFF(CL1) through (tOFF(CL4)) track each other over process
and temperature variations. A device which has an on-time at the high end of the range will have an off-time that is at the high end of its
range.
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Electrical Characteristics (continued)

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature
range, unless otherwise stated. VIN = 24V, RT = 100kΩ unless otherwise stated. (See (1)).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SOFT-START FUNCTION
tSS Soft-Start Time 1.4 2.5 4.3 ms
THERMAL SHUTDOWN
TSD Junction Shutdown Temperature Junction Temperature Rising 170 °C
THYS Junction Shutdown Hysteresis 20 °C

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6.7 Typical Characteristics

Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 24V.

Figure 1. Efficiency (Circuit Of LM25085 Typical Application) Figure 2. Input Operating Current vs. VIN

Figure 3. Shutdown Current vs. VIN Figure 4. VCC vs. VIN

Figure 5. VCC vs. ICC Figure 6. On-Time vs. RT And VIN

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Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 24V.

Figure 7. Off-Time vs. VIN And VFB Figure 8. Voltage At The Rt Pin

Figure 9. Adj Pin Current vs. VIN Figure 10. Input Operating Current vs. Temperature

Figure 11. Shutdown Current vs. Temperature Figure 12. Vcc vs. Temperature

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Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 24V.

Figure 13. On-Time vs. Temperature Figure 14. Minimum On-Time vs. Temperature

Figure 15. Off-Time vs. Temperature Figure 16. Current Limit Comparator Offset vs. Temperature

Figure 17. Adj Pin Current vs. Temperature Figure 18. Pgate Driver Output Resistance vs. Temperature

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Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 24V.

Figure 19. Feedback Reference Voltage vs. Temperature Figure 20. Soft-Start Time vs. Temperature

Figure 21. Rt Pin Shutdown Threshold vs. Temperature

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7 Detailed Description

7.1 Overview

The LM25085 is a PFET buck (step-down) DC-DC controller using the constant on-time (COT) control principle.
The input operating voltage range of the LM25085 is 4.5V to 42V. The use of a PFET in a buck regulator greatly
simplifies the gate drive requirements and allows for 100% duty cycle operation to extend the regulation range
when operating at low input voltage. However, PFET transistors typically have higher on-resistance and gate
charge when compared to similarly rated NFET transistors. Consideration of available PFETs, input voltage
range, gate drive capability of the LM25085, and thermal resistances indicate an upper limit of 10A for the load
current for LM25085 applications. Constant on-time control is implemented using an on-time one-shot that is
triggered by the feedback signal. During the off-time, when the PFET (Q1) is off, the load current is supplied by
the inductor and the output capacitor. As the output voltage falls, the voltage at the feedback comparator input
(FB) falls below the regulation threshold. When this occurs Q1 is turned on for the one-shot period which is
determined by the input voltage (VIN) and the RT resistor. During the on-time the increasing inductor current
increases the voltage at FB above the feedback comparator threshold. For a buck regulator the basic relationship
between the on-time, off-time, input voltage and output voltage is:
VOUT tON
Duty Cycle = = = tON x FS
VIN tON + tOFF

where
• Fs is the switching frequency (1)
Equation 1 is valid only in continuous conduction mode (inductor current does not reach zero). Since the
LM25085 controls the on-time inversely proportional to VIN, the switching frequency remains relatively constant
as VIN is varied. If the input voltage falls to a level that is equal to or less than the regulated output voltage Q1 is
held on continuously (100% duty cycle) and VOUT is approximately equal to VIN.
The COT control scheme, with the feedback signal applied to a comparator rather than an error amplifier,
requires no loop compensation, resulting in very fast load transient response.
The LM25085 is available in both an 8 pin HVSSOP-PowerPAD package and an 8 pin WSON package with an
exposed pad to aid in heat dissipation. An 8 pin VSSOP package without an exposed pad is also available.

7.2 Functional Block Diagram

4.5V to 42V
Negative Bias +
Input VIN
Regulator
LM25085 VCC CVCC
VIN
CIN CADJ
7.7V + Thermal
GND CBYP -
Shutdown VIN

RT - RADJ
0.73V + VCC RSEN
Gate
RT ON Time UVLO Driver
One-Shot PGATE
Q1
SHUTDOWN VCC
1.25V L1
VOUT
Gate Driver
Soft-Start Control Logic R3 C1
ADJ
COUT
40 PA
C2
+ D1
+ QS - RFB2
- R ISEN
REGULATION RFB1
OFF Time CURRENT
COMPARATOR
One-Shot LIMIT
GND 1.6V -
COMPARATOR
+
OVER-VOLTAGE
VIN
COMPARATOR FB

Sense resistor method shown for current limit detection.

Minimum output ripple configuration shown.

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7.3 Feature Description

7.3.1 Regulation Control Circuit
The LM25085 buck DC-DC controller employs a control scheme based on a comparator and a one-shot on-
timer, with the output voltage feedback compared to an internal reference voltage (1.25V). When the FB pin
voltage falls below the feedback reference, Q1 is switched on for a time period determined by the input voltage
and a programming resistor (RT). Following the on-time Q1 remains off until the FB voltage falls below the
reference. Q1 is then switched on for another on-time period. The output voltage is set by the feedback resistors
(RFB1, RFB2 in Functional Block Diagram. The regulated output voltage is calculated as follows:
VOUT = 1.25V x (RFB2+ RFB1)/ RFB1 (2)
The feedback voltage supplied to the FB pin is applied to a comparator rather than a linear amplifier. For proper
operation sufficient ripple amplitude is necessary at the FB pin to switch the comparator at regular intervals with
minimum delay and noise susceptibility. This ripple is normally obtained from the output voltage ripple attenuated
through the feedback resistors. The output voltage ripple is a result of the inductor’s ripple current passing
through the output capacitor’s ESR, or through a resistor in series with the output capacitor. Multiple methods are
available to ensure sufficient ripple is supplied to the FB pin, and three different configurations are discussed in
Alternate Output Ripple Configurations.
When in regulation, the LM25085 operates in continuous conduction mode at medium to heavy load currents and
discontinuous conduction mode at light load currents. In continuous conduction mode the inductor’s current is
always greater than zero, and the operating frequency remains relatively constant with load and line variations.
The minimum load current for continuous conduction mode is one-half the inductor’s ripple current amplitude. In
discontinuous conduction mode, where the inductor’s current reaches zero during the off-time, the operating
frequency is lower than in continuous conduction mode and varies with load current. Conversion efficiency is
maintained at light loads since the switching losses are reduced with the reduction in load and frequency.
If the voltage at the FB pin exceeds 1.6V due to a transient overshoot or excessive ripple at VOUT the internal
over-voltage comparator immediately switches off Q1. The next on-time period starts when the voltage at FB falls
below the feedback reference voltage.

7.3.2 On-Time Timer

The on-time of the PFET gate drive output (PGATE pin) is determined by the resistor (RT) and the input voltage
(VIN), and is calculated from:
-7
1.45 x 10 x (RT + 1.4)
tON = + 50 ns
(VIN - 1.56V + RT/3167)

where
• RT is in kΩ (3)
The minimum on-time, which occurs at maximum VIN, should not be set less than 150ns (see Current Limiting).
The buck regulator effective on-time, measured at the SW node (junction of Q1, L1, and D1) is typically longer
than that calculated in Equation 3 due to the asymmetric delay of the PFET. The on-time difference caused by
the PFET switching delay can be estimated as the difference of the turn-off and turn-on delays listed in the PFET
data sheet. Measuring the difference between the on-time at the PGATE pin versus the SW node in the actual
application circuit is also recommended.
In continuous conduction mode, the inverse relationship of tON with VIN results in a nearly constant switching
frequency as VIN is varied. The operating frequency can be calculated from:
VOUT x (VIN - 1.56V + RT/3167)
FS = -7
VIN x [(1.45 x 10 x (RT + 1.4)) + (tD x (VIN - 1.56V + RT/3167))]

where
• RT is in kΩ
• tD is equal to 50ns plus the PFET’s delay difference (4)

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Feature Description (continued)

To set a specific continuous conduction mode switching frequency (FS), the RT resistor is determined from the
following:

where
• RT is in kΩ (5)
A simplified version of Equation 5 at VIN = 12V, and tD = 100ns, is:
VOUT x 6 x 106
RT = - 8.6
FS
(6)
For VIN = 42V and tD = 100ns, the simplified equation is:

(7)

7.3.3 Shutdown
The LM25085 can be shutdown by grounding the RT pin (see Figure 22). In this mode the PFET is held off, and
the VCC regulator is disabled. The internal operating current is reduced to the value shown in Figure 3. The
shutdown threshold at the RT pin is ≊0.73V, with ≊50mV of hysteresis. Releasing the pin enables normal
operation. The RT pin must not be forced high during normal operation.

Input VIN
Voltage

RT LM25085

RT

STOP

RUN

Figure 22. Shutdown Implementation

7.3.4 Current Limiting

The LM25085 current limiting operates by sensing the voltage across either the RDS(ON) of Q1, or a sense
resistor, during the on-time and comparing it to the voltage across the resistor RADJ (see Figure 23). The current
limit function is much more accurate and stable over temperature when a sense resistor is used. The RDS(ON) of a
MOSFET has a wide process variation and a large temperature coefficient.
If the voltage across RDS(ON) of Q1, or the sense resistor, is greater than the voltage across RADJ, the current limit
comparator switches to turn off Q1. Current sensing is disabled for a blanking time of ≊100ns at the beginning of
the on-time to prevent false triggering of the current limit comparator due to leading edge current spikes.
Because of the blanking time and the turn-on and turn-off delays created by the PFET, the on-time at the PGATE
pin should not be set less than 150ns. An on-time shorter than that may prevent the current limit detection circuit
from properly detecting an over-current condition. The duration of the subsequent forced off-time is a function of
the input voltage and the voltage at the FB pin, as shown in Figure 7. The longer-than-normal forced off-time
allows the inductor current to decrease to a low level before the next on-time. This cycle-by-cycle monitoring,
followed by a forced off-time, provides effective protection from output load faults over a wide range of operating
conditions.
The voltage across the RADJ resistor is set by an internal 40µA current sink at the ADJ pin. When using Q1’s
RDS(ON) for sensing, the current at which the current limit comparator switches is calculated from:
ICL = 40µA x RADJ/RDS(ON) (8)
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Feature Description (continued)

When using a sense resistor (RSEN) the threshold of the current limit comparator is calculated from:
ICL = 40µA x RADJ/RSEN (9)
When using Equation 8 or Equation 9, the tolerances for the ADJ pin current sink and the offset of the current
limit comparator should be included to ensure the resulting minimum current limit is not less than the required
maximum switch current. Simultaneously increasing the values of RADJ and RSEN decreases the effects of the
current limit comparator offset, but at the expense of higher power dissipation. When using a sense resistor, the
RSEN resistor value should be chosen within the practical limitations of power dissipation and physical size. For
example, for a 10A current limit, setting RSEN = 0.005Ω results in a power dissipation as high as 0.5W. Current
sense connections to the RSEN resistor, or to Q1, must be Kelvin connections to ensure accuracy.
The CADJ capacitor filters noise from the ADJ pin, and helps prevent unintended switching of the current limit
comparator due to input voltage transients. The recommended value for CADJ is 1000pF.

7.3.5 Current Limit Off-Time

When the current through Q1 exceeds the current limit threshold, the LM25085 forces an off-time longer than the
normal off-time defined by Equation 1. See Figure 7 or calculate the current limit off-time from the following
equation:

where
• VIN is the input voltage
• VFB is the voltage at the FB pin at the time current limit was detected (10)
This feature is necessary to allow the inductor current to decrease sufficiently to offset the current increase which
occurred during the on-time. During the on-time, the inductor current increases an amount equal to:
(VIN - VOUT) x tON
'I =
L (11)
During the off-time the inductor current decreases due to the reverse voltage applied across the inductor by the
output voltage, the freewheeling diode’s forward voltage (VFD), and the voltage drop due to the inductor’s series
resistance (VESR). The current decrease is equal to:
(VOUT + VFD + VESR) x tOFF
'I =
L (12)
The on-time in Equation 11 is shorter than the normal on-time since the PFET is shut off when the current limit
threshold is crossed. If the off-time is not long enough, such that the current decrease (Equation 12) is less than
the current increase (Equation 11), the current levels are higher at the start of the next on-time. This results in a
further decrease in on-time, since the current limit threshold is crossed sooner. A balance is reached when the
current changes in Equation 11 and Equation 12 are equal. The worst case situation is that of a direct short
circuit at the output terminals, where VOUT = 0V, as that results in the largest current increase during the on-time,
and the smallest decrease during the off-time. The sum of the diode’s forward voltage and the inductor’s ESR
voltage must be sufficient to ensure current runaway does not occur. Using Equation 11 and Equation 12, this
requirement can be stated as:
VIN x tON
VFD + VESR t
tOFF
(13)

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Feature Description (continued)

For tON in Equation 13 use the minimum on-time at the SW node. To determine this time period add the
“Minimum on-time in current limit” specified in Electrical Characteristics (tON-4) to the difference of the turn-off
and turn-on delays of the PFET. For tOFF use the value in Figure 7 or use Equation 10, where VFB is equal to
zero volts. When using the minimum or maximum limits of those specifications to determine worst case
situations, the tolerance of the minimum on-time (tON-4) and the current limit off-times (tOFF(CL1) through tOFF(CL4))
track each other over the process and temperature variations. A device which has an on-time at the high end of
the range will have an off-time that is at the high end of its range.

LM25085 VIN LM25085 VIN

RADJ RADJ
ADJ ADJ
40 PA 40 PA
CURRENT LIMIT CURRENT LIMIT RSEN
CADJ COMPARATOR CADJ
COMPARATOR
+ +
ISEN ISEN
- -
VIN GATE VIN GATE
DRIVER DRIVER
Q1 L1 Q1 L1
PGATE PGATE

VCC VCC

D1 D1

USING Q1 RDS(ON) USING SENSE RESISTOR RSEN

Figure 23. Current Limit Sensing

7.3.6 VCC Regulator

The VCC regulator provides a regulated voltage between the VIN and the VCC pins to provide the bias and gate
current for the PFET gate driver. The 0.47µF capacitor at the VCC pin must be a low ESR capacitor, preferably
ceramic as it provides the high surge current for the PFET’s gate at each turn-on. The capacitor must be located
as close as possible to the VIN and VCC pins to minimize inductance in the PC board traces.
Referring to Figure 4, the voltage across the VCC regulator (VIN – VCC) is equal to VIN until VIN reaches
approximately 8.5V. At higher values of VIN, the voltage at the VCC pin is regulated at approximately 7.7V below
VIN. If VIN drops below about 8V due to voltage transients, the VCC pin can be pulled down below GND. To
prevent the negative VCC voltage from disturbing the internal circuit and causing abnormal operation, a Schottky
diode is recommended between VCC pin and GND pin. The VCC regulator has a maximum current capability of
at least 20mA. The regulator is disabled when the LM25085 is shutdown using the RT pin, or when the thermal
shutdown is activated.

7.3.7 PGATE Driver Output

The PGATE pin output swings between VIN (Q1 off) and the VCC pin voltage (Q1 on). The rise and fall times
depend on the PFET gate capacitance and the source and sink currents provided by the internal gate driver. See
Electrical Characteristics for the current capability of the driver.

7.3.8 P-Channel MOSFET Selection

The PFET must be rated for the maximum input voltage, with some margin above that to allow for transients and
ringing which can occur on the supply line and the switching node. The gate-to-source voltage (VGS) normally
provided to the PFET is 7.7V for VIN greater than 8.5V. However, if the circuit is to be operated at lower values
of VIN, the selected PFET must be able to fully turn-on with a VGS voltage equal to VIN. The minimum input
operating voltage for the LM25085 is 4.5V.

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Feature Description (continued)

Similar to NFETs, the case or exposed thermal pad for a PFET is electrically connected to the drain terminal.
When designing a PFET buck regulator the drain terminal is connected to the switching node. This situation
requires a trade-off between thermal and EMI performance since increasing the PC board area of the switching
node to aid the PFET power dissipation also increases radiated noise, possibly disrupting the circuit operation.
Typically the switching node area is kept to a reasonable minimum and the PFET peak current is derated to stay
within the recommended temperature rating of the PFET. The RDS(ON) of the PFET determines a portion of the
power dissipation in the PFET. However, PFETs with very low RDS(ON) usually have large values of gate charge.
A PFET with a higher gate charge has a corresponding slower switching speed, leading to higher switching
losses and affecting the PFET power dissipation.
If the PFET RDS(ON) is used for current limit detection, note that it typically has a positive temperature coefficient.
At 100°C the RDS(ON) may be as much as 50% higher than the value at 25°C which could result in incorrect
current limiting if not accounted for when determining the value of the RADJ resistor. The PFET Total Gate
Charge determines most of the power dissipation in the LM25085 due to the repetitive charge and discharge of
the PFET’s gate capacitance by the gate driver (powered from the VCC regulator). The LM25085’s internal
power dissipation can be calculated from the following:
PDISS = VIN x ((QG x FS) + IIN)
where
• QG is the PFET Total Gate Charge obtained from its datasheet
• FS is the switching frequency
• IIN is the LM25085's operating current obtained from Figure 2 (14)
Using the Thermal Resistance specifications in Electrical Characteristics, the approximate junction temperature
can be determined. If the calculated junction temperature is near the maximum operating temperature of 125°C,
either the switching frequency must be reduced, or a PFET with a smaller Total Gate Charge must be used.

7.3.9 Soft-Start
The internal soft-start feature of the LM25085 allows the regulator to gradually reach a steady state operating
point at power up, thereby reducing startup stresses and current surges. Upon turn-on, when VCC reaches its
under-voltage lockout threshold, the internal soft-start circuit ramps the feedback reference voltage from 0V to
1.25V, causing VOUT to ramp up in a proportional manner. The soft-start ramp time is typically 2.5ms.
In addition to controlling the initial power up cycle, the soft-start circuit also activates when the LM25085 is
enabled by releasing the RT pin, and when the circuit is shutdown and restarted by the internal Thermal
Shutdown circuit.
If the voltage at FB is below the regulation threshold value due to an over-current condition or a short circuit at
VOUT, the internal reference voltage provided by the soft-start circuit to the regulation comparator is reduced
along with FB. When the over-current or short circuit condition is removed, VOUT returns to the regulated value at
a rate determined by the soft-start ramp. This feature helps prevent the output voltage from overshooting
following an overload event.

7.3.10 Thermal Shutdown

The LM25085 should be operated such that the junction temperature does not exceed 125°C. If the junction
temperature increases above that, an internal Thermal Shutdown circuit activates at 170°C (typical) to disable
the VCC regulator and the gate driver, and discharge the soft-start capacitor. This feature helps prevent
catastrophic failures from accidental device overheating. When the junction temperature falls below 150°C
(typical hysteresis = 20°C), the gate driver is enabled, the soft-start circuit is released, and normal operation
resumes.

7.4 Device Functional Modes

7.4.1 Standby Mode with VIN <4.5 V
The LM25085 is intended to operate with input voltages above 4.5 V. The minimum operating input voltage is
determined by the VCC undervoltage lockout threshold of 3.8 V (typ). If VIN is too low to support a VCC voltage
greater than the VCC UVLO threshhold, the controller switches to the standby mode with the PFET buck switch
in the off state.
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Device Functional Modes (continued)

7.4.2 RT Shutdown Mode
The LM25085 is in shutdown mode when the RT pin is pulled below 0.73 V (typ). In this mode the PFET gate
driver is held off, and the VCC regulator is disabled.

8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM25085/LM25085-Q1 devices are step-down DC-DC converters. The devices are typically used to convert
a higher DC voltage to a lower DC voltage. Use the following design procedure to select component values.
Alternately, use the WEBENCH® software to generate a complete design. The WEBENCH software uses an
iterative design procedure and accesses a comprehensive database of components when generating a design.
This section presents a simplified discussion of the design process.

8.2 Typical Application

7V to 42V CVCC
Input LM25085 0.47 PF
VCC
VIN VIN CADJ 1000 pF
CBYP
CIN
1 PF
33 PF ADJ
GND RADJ RSEN
RT
2.1 k: 0.01:
90.9 k:
ISEN
RT L1 15 PH
PGATE
SHUTDOWN Q1 VOUT
5V
COUT
R3 C1 RFB2
66.5 k: 100 PF
D1 3300 pF 10 k:
C2
0.1 PF GND
GND FB RFB1
3.4 k:

Figure 24. LM25085 Typical Application

8.2.1 Design Requirements

The procedure for calculating the external components is illustrated with the following design example. Referring
to Figure 24, the circuit is to be configured for the following specifications:
• VOUT = 5V
• VIN = 7V to 42V, 12V Nominal
• Maximum load current (IOUT(max)) = 5A
• Minimum load current (IOUT(min)) = 600mA (for continuous conduction mode)
• Switching Frequency (FSW) = 300kHz
• Maximum allowable output ripple (VOS) = 5mVp-p
• Selected PFET: Vishay Si7465

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Typical Application (continued)

8.2.2 Detailed Design Procedure

8.2.2.1 RFB1 and RFB2

These resistors set the output voltage. The ratio of these resistors is calculated from:
RFB2/RFB1 = (VOUT/1.25V) - 1 (15)
For this example, RFB2 / RFB1 = 3. Typically, RFB1 and RFB2 should be chosen from standard value resistors in the
range of 1kΩ to 20kΩ which satisfy the above ratio. For this example, RFB2 = 10kΩ, and RFB1 = 3.4kΩ.

8.2.2.2 RT, PFET

Before selecting the RT resistor, the PFET must be selected as its turn-on and turn-off delays affect the
calculated value of RT. For the Vishay Si7465 PFET, the difference of its typical turn-off and turn-on delays is
57ns. Using Equation 5 at nominal input voltage, RT calculates to be:
5 x (12 - 1.56V) (50 ns + 57 ns) x (12 - 1.56V)
RT = -7 - -7
- 1.4= 90.9
1.45 x 10 x 12 x 300 kHz 1.45 x 10 (16)
A standard value 90.9kΩ resistor is selected. Using Equation 3 the minimum on-time at the PGATE pin, which
occurs at maximum input voltage (42V), is calculated to be 381ns. This minimum one-shot period is sufficiently
longer than the minimum recommended value of 150ns. The minimum on-time at the SW node (junction of Q1,
D1, L1) is longer due to the delay added by the PFET (57ns). Therefore the minimum SW node on-time is 438ns
at 42V. The maximum on-time at the SW node is calculated to be 2.55µs at 7V.

8.2.2.3 L1
The main parameter controlled by the inductor value is the current ripple amplitude (IOR). See Figure 25. The
minimum load current for continuous conduction mode is used to determine the maximum allowable ripple such
that the inductor current valley does not fall to zero. Continuous conduction mode operation at minimum load
current is not a requirement of the LM25085, but serves as a guideline for selecting L1. For this example, the
maximum ripple current is:
IOR(max) = 2 x IOUT(min) = 1.2 Amp (17)
If the minimum load current of the application is zero, a good initial estimate for the maximum ripple current
(IOR(max)) is 20% of the maximum load current. The ripple calculated in Equation 17 is then used in the following
equation to calculate L1:
tON(min) x (VIN(max) - VOUT)
L1 = = 13.5 PH
IOR(max)
(18)
A standard value 15µH inductor is selected. Using this inductance value, the maximum ripple current amplitude,
which occurs at maximum input voltage, is calculated to be 1.08 Ap-p. The peak current (IPK) at maximum load
current is 5.54A. However, the current rating of the selected inductor must be based on the maximum current
limit value calculated below.
Inductor Current

IPK

IOUT
IOR

1/FS
SW Node

Figure 25. Inductor Current Waveform

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Typical Application (continued)

8.2.2.4 RSEN, RADJ
To achieve good current limit accuracy and avoid over designing the power stage components, the sense
resistor method is used for current limiting in this example. A standard value 10mΩ resistor is selected for RSEN,
resulting in a 50mV drop at maximum load current, and a maximum 0.25W power dissipation in the resistor.
Since the LM25085 uses peak current detection, the minimum value for the current limit threshold must be equal
to the maximum load current (5A) plus half the maximum ripple amplitude calculated above:
ICL(min) = 5A + 1.08A/2 = 5.54A (19)
At this current level the voltage across RSEN is 55.4mV. Adding the current limit comparator offset of 9mV (max)
increases the required current limit threshold to 6.44A. Using Equation 9 with the minimum value for the ADJ pin
current (32µA), the required RADJ resistor is calculated to be:
6.44A x 0.01:
RADJ = = 2.01 k:
32 PA (20)
A standard value 2.1kΩ resistor is selected. The nominal current limit threshold is:
(2.1 k: x 40 PA)
ICL(nom) = = 8.4A
0.01: (21)
Using the tolerances for the ADJ pin current and the current limit comparator offset, the maximum current limit
threshold is calculated to be:
(2.1 k: x 48 PA) + 9 mV
ICL(max) = = 11A
0.01: (22)
The minimum current limit threshold is:
(2.1 k: x 32 PA) - 9 mV
ICL(min) = = 5.82A
0.01: (23)
The load current in each case is equal to the current limit threshold minus half the current ripple amplitude. The
recommended value of 1000pF for CADJ is used in this example.

8.2.2.5 COUT
Since the maximum allowed output ripple voltage is very low in this example (5mVp-p), the minimum ripple
configuration (R3, C1, and C2 in the Functional Block Diagram) must be used. The resulting ripple at VOUT is
then due to the inductor’s ripple current passing through COUT. This capacitor’s value can be selected based on
the maximum allowable ripple voltage at VOUT, or based on transient response requirements. The following
calculation, based on ripple voltage, provides a first order result for the value of COUT:
IOR(max)
COUT =
8 x FS x VRIPPLE (24)
where IOR(max) is the maximum ripple current calculated above, and VRIPPLE is the allowable ripple at VOUT.
1.08A
COUT = = 90 PF
8 x 300 kHz x 0.005V
(25)
A 100µF capacitor is selected. Typically the ripple amplitude will be higher than the calculations indicate due to
the capacitor’s ESR.

8.2.2.6 R3, C1, C2

The minimum ripple configuration uses these three components to generate the ripple voltage required at the FB
pin since there is insufficient ripple at VOUT. A minimum of 25mVp-p must be applied to the FB pin to obtain
stable constant frequency operation. R3 and C1 are selected to generate a sawtooth waveform at their junction,
and that waveform is AC coupled to the FB pin via C2. The values of the three components are determined using
the following procedure:

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Typical Application (continued)

First calculate VA = VOUT - (VSW x (1 – (VOUT/VIN(min))))
where VSW is the absolute value of the voltage at the SW node during the off-time, typically 0.5V to 1V
depending on the diode D1. Using a typical value of 0.65V, VA calculates to 4.81V. VA is the nominal DC voltage
at the R3/C1 junction, and is used in the next equation to calculate the R-C product:
(VIN(min) - VA) x tON
R3 x C1 =
'V (26)
where tON is the maximum on-time (at minimum input voltage), and ΔV is the desired ripple amplitude at the
R3/C1 junction. For ripple voltage of 25 mVp-p:
(7V - 4.81V) x 2.55 Ps -4
R3 x C1 = = 2.23 x 10
0.025V
(27)
R3 and C1 are then selected from standard value components to produce the product calculated above. Typical
values for C1 are 3000pF to 10,000pF, and R3 is typically from 10kΩ to 300kΩ. C2 is then chosen large
compared to C1, typically 0.1µF. For this example, 3300pF is chosen for C1, requiring R3 to be 67.7kΩ. A
standard value 66.5kΩ resistor is selected.

8.2.2.7 Alternate Output Ripple Configurations

The minimum ripple configuration with C1, C2 and R3 in the example circuit, Figure 24, results in a low ripple
amplitude at VOUT determined mainly by the characteristics of the output capacitor and the ripple current in L1.
This configuration allows multiple ceramic capacitors to be used for VOUT if the output voltage is provided to
several places on the PC board. However, if a slightly higher level of ripple at VOUT is acceptable in the
application, and distributed capacitance is not used, the ripple required for the FB comparator pin can be
generated with fewer external components using the circuits shown in Figure 26 and Figure 27.

8.2.2.7.1 Reduced Ripple Configuration

In Figure 26, R3, C1 and C2 are removed (compared to Layout Example). A low value resistor (R4) is added in
series with COUT, and a capacitor (Cff) is added across RFB2. Ripple is generated at VOUT by the inductor’s ripple
current flowing through R4, and that ripple voltage is passed to the FB pin via Cff. The ripple at VOUT can be set
as low as 25mVp-p since it is not attenuated by RFB2 and RFB1. The minimum value for R4 is calculated from:
25 mV
R4 =
IOR(min)
(28)
where IOR(min) is the minimum ripple current, which occurs at minimum input voltage. The minimum value for Cff
is determined from:
3 x tON(max)
Cff =
(RFB1//RFB2)
(29)
where tON(max) is the maximum on-time, which occurs at minimum VIN. The next larger standard value capacitor
should be used for Cff.

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Typical Application (continued)

LM25085
PGATE L1
Q1 VOUT

D1 Cff RFB2 R4

FB
COUT
GND
RFB1
GND

Figure 26. Reduced Ripple Configuration

8.2.2.7.2 Lowest Cost Configuration

This configuration, shown in Figure 27, is the same as Figure 26 except Cff is removed. Since the ripple voltage
at VOUT is attenuated by RFB2 and RFB1, the minimum ripple required at VOUT is equal to:
VRIP(min) = 25mV x (RFB2 + RFB1)/RFB1
The minimum value for R4 is calculated from:
VRIP(min)
R4 =
IOR(min)
(30)
where IOR(min) is the minimum ripple current, which occurs at minimum input voltage.

LM25085
PGATE L1
Q1 VOUT

D1 RFB2 R4

FB
COUT
GND
RFB1
GND

Figure 27. Lowest Cost Ripple Generating Configuration

8.2.2.8 CIN, CBYP

These capacitors limit the voltage ripple at VIN by supplying most of the switch current during the on-time. At
maximum load current, when Q1 is switched on, the current through Q1 suddenly increases to the lower peak of
the inductor’s ripple current, then ramps up to the upper peak, and then drops to zero at turn-off. The average
current during the on-time is the load current. For a worst case calculation, these capacitors must supply this
average load current during the maximum on-time, while limiting the voltage drop at VIN. For this example, 0.5V
is selected as the maximum allowable droop at VIN.

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Typical Application (continued)

The minimum input capacitance is calculated from:
IOUT(max) x tON(max) 5A x 2.55 Ps
CIN + CBYP = = = 25.5 PF
'V 0.5V
(31)
A 33µF electrolytic capacitor is selected for CIN, and a 1µF ceramic capacitor is selected for CBYP. Due to the
ESR of CIN, the ripple at VIN will likely be higher than the calculation indicates, and therefore it may be desirable
to increase CIN to 47µF or 68µF. CBYP must be located as close as possible to the VIN and GND pins of the
LM25085. The voltage rating for both capacitors must be at least 42V. The RMS ripple current rating for the input
capacitors must also be considered. A good approximation for the required ripple current rating is IRMS > IOUT/2.

8.2.2.9 D1
A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed
transitions at the SW node may affect the regulator’s operation due to diode reverse recovery transients. The
diode must be rated for the maximum input voltage, and the worst case current limit level. The average power
dissipation in the diode is calculated from:
PD1 = VF x IOUT x (1-D) (32)
where VF is the diode forward voltage drop, and D is the on-time duty cycle. Using Equation 1, the minimum duty
cycle occurs at maximum input voltage, and is calculated to be ≊11.9% in this example. The diode power
dissipation calculates to be:
PD1 = 0.65V x 5A x (1- 0.119) = 2.86W (33)

8.2.2.10 CVCC
The capacitor at the VCC pin (from VIN to VCC) provides not only noise filtering and stability for the VCC
regulator, but also provides the surge current for the PFET gate drive. The typical recommended value for CVCC
is 0.47µF. A good quality, low ESR, ceramic capacitor is recommended. CVCC must be located as close as
possible to the VIN and VCC pins. If the selected PFET has a Total Gate Charge specification of 100nC or
larger, or if the circuit is required to operate at input voltages below 7V, a larger capacitor may be required. The
maximum recommended value for CVCC is 1µF.

8.2.2.11 IC Power Dissipation

The maximum power dissipated in the LM25085 package is calculated using Equation 14 at the maximum input
voltage. The Total Gate Charge for the Si7465 PFET is specified to be 40nC (max) in the data sheet. Therefore
the total power dissipation within the LM25085 is calculated to be:
PDISS = 42V x ((40nC x 300kHz) + 1.3mA) = 559mW (34)
Using an HVSSOP-PowerPAD-8 package with a θJA of 46°C/W produces a temperature rise of 26°C from
junction to ambient.

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Typical Application (continued)

8.2.3 Application Curves

Figure 28. Efficiency vs. Load Current and VIN Figure 29. Frequency vs. VIN

Figure 30. Current Limit vs. VIN (Circuit Of Figure 32) Figure 31. LM25085 Power Dissipation (Circuit Of
Figure 32)

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9 Power Supply Recommendations

The devices are designed to operate from an input voltage supply range between 4.5 V and 42 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the device, additional
bulk capacitance may be required at the input terminals of the converter in addition to the calculated values to
limit the inductive spikes due to the input cables or wires.

10 Layout

10.1 Layout Guidelines

In most applications, the heat sink pad or tab of Q1 is connected to the switch node, i.e. the junction of Q1, L1
and D1. While it is common to extend the PC board pad from under these devices to aid in heat dissipation, the
pad size should be limited to minimize EMI radiation from this switching node. If the PC board layout allows, a
similarly sized copper pad can be placed on the underside of the PC board, and connected with as many vias as
possible to aid in heat dissipation.
The voltage regulation, over-voltage, and current limit comparators are very fast and can respond to short
duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be
as neat and compact as possible with all the components as close as possible to their associated pins. Two
major current loops conduct currents which switch very fast, requiring the loops to be as small as possible to
minimize conducted and radiated EMI. The first loop is that formed by CIN, Q1, L1, COUT, and back to CIN. The
second loop is that formed by D1, L1, COUT, and back to D1. The connection from the anode of D1 to the ground
end of CIN must be short and direct. CIN must be as close as possible to the VIN and GND pins, and CVCC must
be as close as possible to the VIN and VCC pins.
If the anticipated internal power dissipation of the LM25085 will produce excessive junction temperatures during
normal operation, a package option with an exposed pad must be used (HVSSOP-PowerPAD-8 or WSON-8).
Effective use of the PC board ground plane can help dissipate heat. Additionally, the use of wide PC board
traces, where possible, helps conduct heat away from the IC. Judicious positioning of the PC board within the
end product, along with the use of any available air flow (forced or natural convection) also helps reduce the
junction temperature.

10.2 Layout Example

RT and ADJ
Connections
(Tap to CIN)
VIN
Keep
CIN, D1, Q1
Exposed Pad on Bottom
Connect to Ground Loop Small

RSEN

ADJ 1 8 VIN Q1

RT 2 7 VCC CVCC CIN

FB 3 6 PGATE
L1
GND 4 5 ISEN VOUT

D1 COUT

GND

RFB1

Figure 32. LM25085 Buck Converter Layout Example

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 1. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
LM25085 Click here Click here Click here Click here Click here
LM25085-Q1 Click here Click here Click here Click here Click here

11.3 Trademarks
PowerPad is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: LM25085 LM25085-Q1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM25085MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SVZB

LM25085MME/NOPB ACTIVE VSSOP DGK 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SVZB

LM25085MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SVZB

LM25085MY/NOPB ACTIVE HVSSOP DGN 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SVYB

LM25085MYE/NOPB ACTIVE HVSSOP DGN 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SVYB

LM25085MYX/NOPB ACTIVE HVSSOP DGN 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SVYB

LM25085QMY/NOPB ACTIVE HVSSOP DGN 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SYLB

LM25085QMYE/NOPB ACTIVE HVSSOP DGN 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SYLB

LM25085QMYX/NOPB ACTIVE HVSSOP DGN 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SYLB

LM25085SD/NOPB ACTIVE WSON NGQ 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L246B

LM25085SDE/NOPB ACTIVE WSON NGQ 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L246B

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM25085, LM25085-Q1 :

• Catalog: LM25085
• Automotive: LM25085-Q1

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 6-Sep-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM25085MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085MME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085MY/NOPB HVSSOP DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085MYE/NOPB HVSSOP DGN 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085MYX/NOPB HVSSOP DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085QMY/NOPB HVSSOP DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085QMYE/NOPB HVSSOP DGN 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085QMYX/NOPB HVSSOP DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085SD/NOPB WSON NGQ 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LM25085SDE/NOPB WSON NGQ 8 250 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 6-Sep-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM25085MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM25085MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0
LM25085MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LM25085MY/NOPB HVSSOP DGN 8 1000 210.0 185.0 35.0
LM25085MYE/NOPB HVSSOP DGN 8 250 210.0 185.0 35.0
LM25085MYX/NOPB HVSSOP DGN 8 3500 367.0 367.0 35.0
LM25085QMY/NOPB HVSSOP DGN 8 1000 210.0 185.0 35.0
LM25085QMYE/NOPB HVSSOP DGN 8 250 210.0 185.0 35.0
LM25085QMYX/NOPB HVSSOP DGN 8 3500 367.0 367.0 35.0
LM25085SD/NOPB WSON NGQ 8 1000 210.0 185.0 35.0
LM25085SDE/NOPB WSON NGQ 8 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
NGQ0008A SCALE 4.000
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

3.1 A
B
2.9

PIN 1 INDEX AREA

3.1
2.9

0.8 C
0.7
SEATING PLANE

0.08 C

1.6 0.1 (0.1) TYP

SYMM 0.05
EXPOSED 0.00
THERMAL PAD

4
5

9 SYMM
2X
2 0.1
1.5

8
1
6X 0.5
0.3
8X
0.2
PIN 1 ID 0.5 0.1 C A B
8X
0.3 0.05 C

4214922/A 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
NGQ0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(1.6)
8X (0.6) SYMM

1
8

(0.75)
8X (0.25)
9 SYMM

(2)
6X (0.5)
5
4

(R0.05) TYP ( 0.2) VIA

TYP

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

EXPOSED METAL EXPOSED METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214922/A 03/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
NGQ0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

8X (0.6) SYMM METAL

TYP
9

1 8

8X (0.25)
SYMM
(1.79)

6X (0.5)
5
4

(R0.05) TYP
(1.47)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 9:
82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4214922/A 03/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
TM
DGN0008A SCALE 4.000
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
A TYP
4.75 0.1 C
PIN 1 INDEX AREA SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A

EXPOSED THERMAL PAD

4
5

0.25
GAGE PLANE
2.0
1.7 9 1.1 MAX

8
1 0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

1.88
TYPICAL
1.58

4218836/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
TM
DGN0008A PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(2)
NOTE 9
METAL COVERED
BY SOLDER MASK (1.88)
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(3)
9 SYMM NOTE 9

(2)

6X (0.65) (1.22)
5
4

( 0.2) TYP
VIA (0.55) SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4218836/A 11/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
TM
DGN0008A PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(1.88)
BASED ON
0.125 THICK
STENCIL
SYMM

8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(2)
SYMM BASED ON
0.125 THICK
STENCIL

6X (0.65)

4 5

METAL COVERED SEE TABLE FOR

BY SOLDER MASK DIFFERENT OPENINGS
(4.4) FOR OTHER STENCIL
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.10 X 2.24
0.125 1.88 X 2.00 (SHOWN)
0.15 1.72 X 1.83
0.175 1.59 X 1.69

4218836/A 11/2019
NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
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