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Lab-05 Layout: "Layout of Basic Gates Using 0.25 Micron Technology in Microwind" 1. Objective

The document describes the design and layout of CMOS NAND and NOR gates using the Microwind tool with 0.25 micron technology. It provides details on the theory of operation for each gate and their respective CMOS circuit diagrams. The lab instructions guide students to design the layout of each gate using MOS generators and metal layers for connections. Students are asked to simulate their designs and analyze the effects of transistor sizing on delay, area, power and current.

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Sheikh Abdullah Al Salman
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306 views3 pages

Lab-05 Layout: "Layout of Basic Gates Using 0.25 Micron Technology in Microwind" 1. Objective

The document describes the design and layout of CMOS NAND and NOR gates using the Microwind tool with 0.25 micron technology. It provides details on the theory of operation for each gate and their respective CMOS circuit diagrams. The lab instructions guide students to design the layout of each gate using MOS generators and metal layers for connections. Students are asked to simulate their designs and analyze the effects of transistor sizing on delay, area, power and current.

Uploaded by

Sheikh Abdullah Al Salman
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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VLSI Design 34

Lab-05 Layout

“Layout of Basic Gates using 0.25 micron Technology in Microwind”

1. Objective

In this lab students will design and implement the layouts of different CMOS gates,
which includes NAND, NOR. The tool used in this lab is Microwind. The goals for this
Lab are:

 Design of CMOS NAND and NOR Gate. 


Layout Design using the tool.
 Gate delay, area, power and current analysis and the effects of transistor sizing
on these parameters.

2. Theory

2.1 NAND Gate

As per discussion and design on white board in the Lab, a NAND gate can be
implemented using four FETS i.e. two pFETs and two nFETs as the inputs of the gate is
two. pFETs are connected in parallel while nFETs are connected in series, Vdd is
supplied to the parallel combination of pFETs while the series combination of nFETs is
grounded. Inputs a & b are applied to the gate terminals of all FETs, and the output f is
obtained from the common junction of these series and parallel combinations as
illustrated in NAND circuit under the heading of Design Diagram / Circuit.

2.2 NOR Gate

As per discussion and design on white board in the Lab, A NOR Gate can be
implemented using fours FETS i.e two pFETs and two nFETs as the inputs of the gate is
two. pFETs are connected in series while nFETs are connected in parallel, Vdd is
supplied to the series combination of pFETs while the parallel combination of nFETs is
grounded. Inputs a & b are applied to the gate terminals of all FETs, and the output f is
obtained from the common junction of these parallel and series combinations as
illustrated inNOR circuit under the heading of Design Diagram/Circuit.
VLSI Design 35

3. Design Diagram / Circuit


a) Symbol, Truth Table and CMOS circuit of NAND Gate
Vdd

a a b f
f a b
b 0 0 1
0 1 1 f
1 0 1
1 1 0 a

b) Symbol, Truth Table and CMOS circuit of NOR Gate

Vdd
a a b f
f
b 0 0 1 a
0 1 0
1 0 0 b
1 1 0
f

a b

Gnd

Figure 5.1 NOR Gate, Symbols and Truth Table

4. Lab Instructions

1. Open Microwind and select the foundry cmos025


2. Save the design as “Save as” as “Lab05”, and save the design frequently
during the lab session.
3. Draw the layout of nMOS using MOS Generator
4. Draw the layout of pMOS using MOS Generator by setting the appropriate
width of pMOS
5. Connect the transistors using Metal 1 as per design.
6. Draw the rails of VDD and ground rails above and below.
7. Connect the nWell to V DD
8. Check the design using DRC for any design rule violation and correct the
VLSI Design 36

design in case of error, again run the DRC and


check for errors. Or run the DRC after each change
in the layout.
9. Check for Electrical connections to be valid.
10. Add inputs and outputs to the design; also add
virtual capacitance at the output
in your design.
11. Simulate the Design. Observe the values of
configuration delay, gate delay,
power, current, VTC, and area.
12. Repeat the design using for different values of
transistor’s dimensions, supply
voltages. And observe the changes in configuration
delay, gate delay, power,
current, VTC, and area carefully. Make a conclusion
of your observations.

NAND Gate using Metal 3 for inputs, Metal 2 for Vdd and Gnd, and Metal 1 for diffusion
interconnection and CMOS 0.12 micron

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