a Monolithic 16-Bit

DACPORT
AD669
FEATURES FUNCTIONAL BLOCK DIAGRAM
Complete 16-Bit D/A Function
On-Chip Output Amplifier (MSB) (LSB)
High Stability Buried Zener Reference DB15 DB0
Monolithic BiMOS II Construction 7 22

61 LSB Integral Linearity Error

CS 6 16-BIT LATCH 10k
15-Bit Monotonic over Temperature 26 SPAN/
Microprocessor Compatible L1 5 BIP OFF
16-Bit Parallel Input 10.05k
LDAC 23 16-BIT LATCH
Double-Buffered Latches
10k
Fast 40 ns Write Pulse REF IN 27 16-BIT DAC
AMP 25 VOUT
Unipolar or Bipolar Output
Low Glitch: 15 nV-s 28 10V REF 24 AGND
REF OUT AD669
Low THD+N: 0.009%
MIL-STD-883 Compliant Versions Available
1 2 3 4
–V EE +VCC +VLL DGND

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS

The AD669 DACPORT® is a complete 16-bit monolithic D/A 1. The AD669 is a complete voltage output 16-bit DAC with
converter with an on-board reference and output amplifier. It is voltage reference and digital latches on a single IC chip.
manufactured on Analog Devices’ BiMOS II process. This pro- 2. The internal buried Zener reference is laser trimmed to
cess allows the fabrication of low power CMOS logic functions 10.000 volts with a ± 0.2% maximum error. The reference
on the same chip as high precision bipolar linear circuitry. The voltage is also available for external applications.
AD669 chip includes current switches, decoding logic, an output
amplifier, a buried Zener reference and double-buffered latches. 3. The AD669 is both dc and ac specified. DC specs include
± 1 LSB INL error and ± 1 LSB DNL error. AC specs include
The AD669’s architecture insures 15-bit monotonicity over 0.009% THD+ N and 83 dB SNR. The ac specifications
temperature. Integral nonlinearity is maintained at ± 0.003%, make the AD669 suitable for signal generation applications.
while differential nonlinearity is ± 0.003% max. The on-chip
output amplifier provides a voltage output settling time of 10 µs 4. The double-buffered latches on the AD669 eliminate data
to within 1/2 LSB for a full-scale step. skew errors while allowing simultaneous updating of DACs in
multi-DAC systems.
Data is loaded into the AD669 in a parallel 16-bit format. The
double-buffered latch structure eliminates data skew errors and 5. The output range is a pin-programmable unipolar 0 V to
provides for simultaneous updating of DACs in a multi-DAC +10 V or bipolar –10 V to +10 V output. No external compo-
system. Three TTL/LSTTL/5 V CMOS compatible signals con- nents are necessary to set the desired output range.
trol the latches: CS, L1 and LDAC. 6. The AD669 is available in versions compliant with MIL-
The output range of the AD669 is pin programmable and can STD-883. Refer to the Analog Devices Military Products
be set to provide a unipolar output range of 0 V to +10 V or a Databook or current AD669/883B data sheet for detailed
bipolar output range of –10 V to +10 V. specifications.
The AD669 is available in seven grades: AN and BN versions
are specified from –40°C to +85°C and are packaged in a 28-pin
plastic DIP. The AR and BR versions are specified for –40°C to
+85°C operation and are packaged in a 28-pin SOIC. The SQ
version is specified from –55°C to +125°C and is packaged in a
hermetic 28-pin cerdip package. The AD669 is also available
compliant to MIL-STD-883. Refer to the AD669/883B data
sheet for specifications and test conditions.
DACPORT is a registered trademark of Analog Devices, Inc.

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
AD669* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017

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• AD669: Monolithic 16-Bit DACPORT Data Sheet
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AD669–SPECIFICATIONS (@ T = +258C, V A CC = +15 V, VEE = –15 V, VLL = +5 V, unless otherwise noted)

Model AD669AN/AR AD669AQ/SQ AD669BN/BQ/BR

Min Typ Max Min Typ Max Min Typ Max Units
RESOLUTION 16 16 16 Bits
DIGITAL INPUTS (TMIN to TMAX)
VIH (Logic “1” ) 2.0 5.5 * * * * Volts
VIL (Logic “0” ) 0 0.8 * * * * Volts
IIH (VIH = 5.5 V) 610 * * µA
IIL (VIL = 0 V) 610 * * µA
TRANSFER FUNCTION CHARACTERISTICS1
Integral Nonlinearity 62 * 61 LSB
TMIN to TMAX 64 * 62 LSB
Differential Nonlinearity 62 * 61 LSB
TMIN to TMAX 64 * 62 LSB
Monotonicity Over Temperature 14 14 15 Bits
Gain Error2, 5 60.15 60.10 60.10 % of FSR
Gain Drift2 (TMIN to TMAX) 25 15 15 ppm/°C
Unipolar Offset 65 65 62.5 mV
Unipolar Offset Drift (TMIN to TMAX) 5 3 3 ppm/°C
Bipolar Zero Error 615 615 610 mV
Bipolar Zero Error Drift (TMIN to TMAX) 12 10 5 ppm/°C
REFERENCE INPUT
Input Resistance 7 10 13 * * * * * * kΩ
Bipolar Offset Input Resistance 7 10 13 * * * * * * kΩ
REFERENCE OUTPUT
Voltage 9.98 10.00 10.02 * * * * * * Volts
Drift 25 15 15 ppm/°C
External Current3 2 4 * * * * mA
Capacitive Load 1000 * * pF
Short Circuit Current 25 * * mA
OUTPUT CHARACTERISTICS
Output Voltage Range
Unipolar Configuration 0 +10 * * * * Volts
Bipolar Configuration –10 +10 * * * * Volts
Output Current 5 * * mA
Capacitive Load 1000 * * pF
Short Circuit Current 25 * * mA
POWER SUPPLIES
Voltage
VCC4 +13.5 +16.5 * * * * Volts
VEE4 –13.5 –16.5 * * * * Volts
VLL +4.5 +5.5 * * * * Volts
Current (No Load)
ICC +12 +18 * * * * mA
IEE –12 –18 * * * * mA
ILL
@ VIH, VIL = 5, 0 V 0.3 2 * * * * mA
@ VIH, VIL = 2.4, 0.4 V 3 7.5 * * * * mA
Power Supply Sensitivity 1 3 * * * * ppm/%
Power Dissipation (Static, No Load) 365 625 * * mW
TEMPERATURE RANGE
Specified Performance (A, B) –40 +85 –40 +85 –40 +85 °C
Specified Performance (S) –55 +125 °C
NOTES
1
For 16-bit resolution, 1 LSB = 0.0015% of FSR = 15 ppm of FSR. For 15-bit resolution, 1 LSB = 0.003% of FSR = 30 ppm of FSR. For 14-bit resolution
1 LSB = 0.006% of FSR = 60 ppm of FSR. FSR stands for Full-Scale Range and is 10 V for a 0 V to + 10 V span and 20 V for a –10 V to +10 V span.
2
Gain error and gain drift measured using the internal reference. Gain drift is primarily reference related. See the Using the AD669 with the AD688 Reference section
for further information.
3
External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD669.
4
Operation on ± 12 V supplies is possible using an external reference like the AD586 and reducing the output range. Refer to the Internal/External Reference Use section.
5
Measured with fixed 50 Ω resistors. Eliminating these resistors increases the gain error by 0.25% of FSR (Unipolar mode) or 0.50% of FSR (Bipolar mode). Refer to
the Analog Circuit Connections section.
*Same as AD669AN/AR specification.
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifica-
tions are guaranteed. Those shown in boldface are tested on all production units.

–2– REV. A
 AD669
AC PERFORMANCE CHARACTERISTICS (With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise
Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested.
TMIN ≤ TA ≤ TMAX, VCC = +15 V, VEE = –15 V, VLL = +5 V except where noted.)
Parameter Limit Units Test Conditions/Comments
Output Settling Time 13 µs max 20 V Step, TA = +25°C
(Time to ± 0.0008% FS 8 µs typ 20 V Step, TA = +25°C
with 2 kΩ, 1000 pF Load) 10 µs typ 20 V Step, TMIN ≤ TA ≤ TMAX
6 µs typ 10 V Step, TA = +25°C
8 µs typ 10 V Step, TMIN ≤ TA ≤ TMAX
2.5 µs typ 1 LSB Step, TMIN ≤ TA ≤ TMAX
Total Harmonic Distortion + Noise
A, B, S Grade 0.009 % max 0 dB, 1001 Hz; Sample Rate = 100 kHz; TA = +25°C
A, B, S Grade 0.07 % max –20 dB, 1001 Hz; Sample Rate = 100 kHz; TA = +25°C
A, B, S Grade 7.0 % max –60 dB, 1001 Hz; Sample Rate = 100 kHz; TA = +25°C
Signal-to-Noise Ratio 83 dB min TA = +25°C
Digital-to-Analog Glitch Impulse 15 nV-s typ DAC Alternately Loaded with 8000H and 7FFFH
Digital Feedthrough 2 nV-s typ DAC Alternately Loaded with 0000H and FFFFH; CS High
Output Noise Voltage 120 nV/√Hz typ Measured at VOUT, 20 V Span; Excludes Reference
Density (1 kHz – 1 MHz)
Reference Noise 125 nV/√Hz typ Measured at REF OUT
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed. Those shown in boldface are tested on all production units.

TIMING CHARACTERISTICS tCS

VCC = +15 V, VEE = –15 V, VLL = +5 V, VHI = 2.4 V, VLO = 0.4 V CS
Limit Limit tL1
Limit –408C to –558C to L1
Parameter +258C +858C +1258C Units
(Figure la) DATA
tCS 40 50 55 ns min
tLI 40 50 55 ns min t DS t DH
LDAC
tDS 30 35 40 ns min t LW
tDH 10 10 15 ns min t LH
tLH 90 110 120 ns min
tLW 40 45 45 ns min Figure 1a. AD669 Level Triggered Timing Diagram
(Figure lb) t LOW t HIGH
tLOW 130 150 165 ns min
tHIGH 40 45 45 ns min CS AND/OR
tDS 120 140 150 ns min L1, LDAC
tDH 10 10 15 ns min
DATA
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical t DS
test. Results from those tests are used to calculate outgoing quality levels. All t DH
min and max specifications are guaranteed. Those shown in boldface are tested
on all production units. TIE CS AND/OR L1 TO GROUND OR TOGETHER WITH LDAC

Figure 1b. AD669 Edge Triggered Timing Diagram

REV. A –3–
AD669
ESD SENSITIVITY
The AD669 features input protection circuitry consisting of large transistors and polysilicon series
resistors to dissipate both high-energy discharges (Human Body Model) and fast, low-energy pulses
(Charged Device Model). Per Method 3015.2 of MIL-STD-883: C, the AD669 has been classified
as a Class 2 device. WARNING!
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test ESD SENSITIVE DEVICE
equipment and discharge without detection. Unused devices must be stored in conductive foam or
shunts, and the foam should be discharged to the destination socket before devices are removed.
For further information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.

ABSOLUTE MAXIMUM RATINGS * PIN CONFIGURATION

VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17.0 V
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17.0 V VEE 1 28 REF OUT
VLL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VCC 2 27 REF IN
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 1 V SPAN/BIP
VLL 3 26
Digital Inputs (Pins 5 through 23) to DGND . . . . . . –1.0 V to OFFSET
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0 V DGND 4 25 VOUT
REF IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10.5 V L1 5 24 AGND
Span/Bipolar Offset to AGND . . . . . . . . . . . . . . . . . . . ± 10.5 V
CS 6 23 LDAC
REF OUT, VOUT . . . . . . Indefinite Short To AGND, DGND,
AD669
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC, VEE, and VLL DB15 7 22 DB0
TOP VIEW
Power Dissipation (Any Package) DB14 8 (Not to Scale) 21 DB1
To +60°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
DB13 9 20 DB2
Derates above +60°C . . . . . . . . . . . . . . . . . . . . . .8.7 mW/°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C DB12 10 19 DB3
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C DB11 11 18 DB4
*Stresses above those listed under “Absolute Maximum Ratings” may cause
DB10 12 17 DB5
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indi cated in DB9 13 16 DB6
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. DB8 14 15 DB7

ORDERING GUIDE
Linearity Gain
Temperature Error Max TC max Package Package
Model Range TMIN–TMAX ppm/8C Description Option*
AD669AN –40°C to +85°C ± 4 LSB 25 Plastic DIP N-28
AD669AR –40°C to +85°C ± 4 LSB 25 SOIC R-28
AD669BN –40°C to +85°C ± 2 LSB 15 Plastic DIP N-28
AD669BR –40°C to +85°C ± 2 LSB 15 SOIC R-28
AD669AQ –40°C to +85°C ± 4 LSB 15 Cerdip Q-28
AD669BQ –40°C to +85°C ± 2 LSB 15 Cerdip Q-28
AD669SQ –55°C to +125°C ± 4 LSB 15 Cerdip Q-28
AD669/883B** –55°C to +125°C ** ** ** **
** N = Plastic DIP; Q = Cerdip; R = SOIC.
** Refer to AD669/883B military data sheet.

10
10

–60dB –60dB
1 1
THD + N – %
THD + N – %

0.1 0.1 –20dB

–20dB
0.01 0.01
0dB

0dB

0.001 0.001
–50 –25 0 25 50 75 100 125 100 1000 10000
TEMPERATURE – °C FREQUENCY – Hz

THD+N vs. Temperature THD+N vs. Frequency

–4– REV. A
 AD669
DEFINITIONS OF SPECIFICATIONS THEORY OF OPERATION
INTEGRAL NONLINEARITY: Analog Devices defines inte- The AD669 uses an array of bipolar current sources with MOS
gral nonlinearity as the maximum deviation of the actual, ad- current steering switches to develop a current proportional to
justed DAC output from the ideal analog output (a straight line the applied digital word, ranging from 0 mA to 2 mA. A seg-
drawn from 0 to FS–1 LSB) for any bit combination. This is mented architecture is used, where the most significant four
also referred to as relative accuracy. data bits are thermometer decoded to drive 15 equal current
DIFFERENTIAL NONLINEARITY: Differential nonlinearity sources. The lesser bits are scaled using a R-2R ladder, then ap-
is the measure of the change in the analog output, normalized to plied together with the segmented sources to the summing node
full scale, associated with a 1 LSB change in the digital input of the output amplifier. The internal span/bipolar offset resistor
code. Monotonic behavior requires that the differential linearity can be connected to the DAC output to provide a 0 V to +10 V
error be within ± 1 LSB over the temperature range of interest. span, or it can be connected to the reference input to provide a
–10 V to +10 V span.
MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs with (MSB) (LSB)
DB15 DB0
the result that the output will always be a single-valued function
7 22
of the input.
GAIN ERROR: Gain error is a measure of the output error be- CS 6 10k
16-BIT LATCH
26 SPAN/
tween an ideal DAC and the actual device output with all 1s L1 5
BIP OFF
loaded after offset error has been adjusted out. 10.05k
LDAC 23 16-BIT LATCH

OFFSET ERROR: Offset error is a combination of the offset 10k

REF IN 27 16-BIT DAC
errors of the voltage-mode DAC and the output amplifier and is AMP 25 VOUT
measured with all 0s loaded in the DAC. 28
REF OUT 10V REF 24 AGND
AD669
BIPOLAR ZERO ERROR: When the AD669 is connected for
bipolar output and 10 . . . 000 is loaded in the DAC, the devia- 1 2 3 4
tion of the analog output from the ideal midscale value of 0 V is –VEE +VCC +VLL DGND
called the bipolar zero error.
DRIFT: Drift is the change in a parameter (such as gain, offset
Figure 2. AD669 Functional Block Diagram
and bipolar zero) over a specified temperature range. The drift
temperature coefficient, specified in ppm/°C, is calculated by
ANALOG CIRCUIT CONNECTIONS
measuring the parameter at TMIN, 25°C and TMAX and dividing
Internal scaling resistors provided in the AD669 may be con-
the change in the parameter by the corresponding temperature
nected to produce a unipolar output range of 0 V to +10 V or a
change.
bipolar output range of –10 V to +10 V. Gain and offset drift
TOTAL HARMONIC DISTORTION + NOISE: Total har- are minimized in the AD669 because of the thermal tracking of
monic distortion + noise (THD+N) is defined as the ratio of the the scaling resistors with other device components.
square root of the sum of the squares of the values of the har-
monics and noise to the value of the fundamental input fre- UNIPOLAR CONFIGURATION
quency. It is usually expressed in percent (%). The configuration shown in Figure 3a will provide a unipolar
THD+N is a measure of the magnitude and distribution of lin- 0 V to +10 V output range. In this mode, 50 Ω resistors are tied
earity error, differential linearity error, quantization error and between the span/bipolar offset terminal (Pin 26) and VOUT (Pin
noise. The distribution of these errors may be different, depend- 25), and between REF OUT (Pin 28) and REF IN (Pin 27). It
ing upon the amplitude of the output signal. Therefore, to be is possible to use the AD669 without any external components
the most useful, THD+N should be specified for both large and by tying Pin 28 directly to Pin 27 and Pin 26 directly to Pin 25.
small signal amplitudes. Eliminating these resistors will increase the gain error by 0.25%
of FSR.
SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is de-
fined as the ratio of the amplitude of the output when a full- (MSB) (LSB)
scale signal is present to the output with no signal present. This DB15 DB0

is measured in dB. 7 22

DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the CS 6 16-BIT LATCH 10k

amount of charge injected from the digital inputs to the analog 26
L1 5
output when the inputs change state. This is measured at half 10.05k
LDAC 23 16-BIT LATCH R2
scale when the DAC switches around the MSB and as many 10k
50Ω

as possible switches change state, i.e., from 011 . . . 111 to 27 16-BIT DAC
AMP 25 OUTPUT
100 . . . 000. R1
50Ω
28 10V REF
DIGITAL FEEDTHROUGH: When the DAC is not selected AD669 24 GND
(i.e., CS is held high), high frequency logic activity on the digi-
1 2 3 4
tal inputs is capacitively coupled through the device to show up
–V EE +VCC +VLL
as noise on the VOUT pin. This noise is digital feedthrough.

Figure 3a. 0 V to +10 V Unipolar Voltage Output

REV. A –5–
AD669
If it is desired to adjust the gain and offset errors to zero, this STEP III . . . BIPOLAR ZERO ADJUST
can be accomplished using the circuit shown in Figure 3b. The (Optional) In applications where an accurate zero output is re-
adjustment procedure is as follows: quired, set the MSB ON, all other bits OFF, and readjust R2
STEP1 . . . ZERO ADJUST for zero volts output.
Turn all bits OFF and adjust zero trimmer, R4, until the output
reads 0.000000 volts (1 LSB = 153 µV).
100V
STEP 2 . . . GAIN ADJUST (MSB) R2 (LSB)
Turn all bits ON and adjust gain trimmer, R1, until the output DB15 DB0
7 22
is 9.999847 volts. (Full scale is adjusted to 1 LSB less than the
nominal full scale of 10.000000 volts). CS 6 16-BIT LATCH 10kV
L1 5 26
(MSB) (LSB)
DB15 10.05kV
DB0 16-BIT LATCH
+15V LDAC 23
R3
7 22
16kV 10kV
R4
27 16-BIT DAC
CS 6 16-BIT LATCH 10kV 10kV AMP 25 OUTPUT
100V
26 R1
L1 5
–15V
28 10V REF
LDAC 23 16-BIT LATCH
10.05kV
R2 AD669 24 GND
50V
10kV 1 2 3 4
27 16-BIT DAC
R1 AMP 25 OUTPUT –VEE +VCC +VLL
100V
28 10V REF
AD669 24 GND Figure 4b. ± 10 V Bipolar Voltage Output with Gain and
1 2 3 4 Offset Adjustment
–VEE +VCC +VLL It should be noted that using external resistors will introduce a
Figure 3b. 0 V to +10 V Unipolar Voltage Output with small temperature drift component beyond that inherent in the
Gain and Offset Adjustment AD669. The internal resistors are trimmed to ratio-match and
temperature-track other resistors on chip, even though their ab-
BIPOLAR CONFIGURATION solute tolerances are ± 20% and absolute temperature coeffi-
The circuit shown in Figure 4a will provide a bipolar output cients are approximately –50 ppm/°C. In the case that external
voltage from –10.000000 V to +9.999694 V with positive full resistors are used, the temperature coefficient mismatch be-
scale occurring with all bits ON. As in the unipolar mode, resis- tween internal and external resistors, multiplied by the sensitiv-
tors R1 and R2 may be eliminated altogether to provide AD669 ity of the circuit to variations in the external resistor value, will
bipolar operation without any external components. Eliminating be the resultant additional temperature drift.
these resistors will increase the gain error by 0.50% of FSR in INTERNAL/EXTERNAL REFERENCE USE
the bipolar mode. The AD669 has an internal low noise buried Zener diode refer-
R2
ence which is trimmed for absolute accuracy and temperature
(MSB) 50V (LSB) coefficient. This reference is buffered and optimized for use in a
DB15 DB0
7 22
high speed DAC and will give long-term stability equal or supe-
rior to the best discrete Zener diode references. The perfor-
CS 6 10kV mance of the AD669 is specified with the internal reference
16-BIT LATCH
26
L1 5 driving the DAC since all trimming and testing (especially for
10.05kV
LDAC 23 16-BIT LATCH gain and bipolar offset) is done in this configuration.
R1 10kV The internal reference has sufficient buffering to drive external
27 16-BIT DAC OUTPUT
50V
AMP 25 circuitry in addition to the reference currents required for the
28 10V REF
DAC (typically 1 mA to REF IN and 1 mA to BIPOLAR OFF-
AD669 24 GND
SET). A minimum of 2 mA is available for driving external
1 2 3 4 loads. The AD669 reference output should be buffered with an
–VEE +VCC +VLL external op amp if it is required to supply more than 4 mA total
current. The reference is tested and guaranteed to ± 0.2% max
Figure 4a. ± 10 V Bipolar Voltage Output error. The temperature coefficient is comparable to that of the
gain TC for a particular grade.
Gain offset and bipolar zero errors can be adjusted to zero using
the circuit shown in Figure 4b as follows: If an external reference is used (10.000 V, for example), addi-
tional trim range should be provided, since the internal refer-
STEP I . . . OFFSET ADJUST ence has a tolerance of ± 20 mV, and the AD669 gain and
Turn OFF all bits. Adjust trimmer R2 to give –10.000000 volts bipolar offset are both trimmed with the internal reference. The
output. optional gain and offset trim resistors in Figures 5 and 6 provide
STEP II . . . GAIN ADJUST enough adjustment range to null these errors.
Turn all bits ON and adjust R1 to give a reading of +9.999694 It is also possible to use external references other than 10 volts
volts. with slightly degraded linearity specifications. The recom-
mended range of reference voltages is +5 V to +10.24 V, which

–6– REV. A
 AD669
allows 5 V, 8.192 V and 10.24 V ranges to be used. For ex- USING THE AD669 WITH THE AD688 HIGH PRECISION
ample, by using the AD586 5 V reference, outputs of 0 V to VOLTAGE REFERENCE
+5 V unipolar or ± 5 V bipolar can be realized. Using the The AD669 is specified for gain drift from 15 ppm/°C to
AD586 voltage reference makes it possible to operate the 25 ppm/°C (depending upon grade) using its internal 10 volt
AD669 off of ± 12 V supplies with 10% tolerances. reference. Since the internal reference contributes the vast ma-
Figure 5 shows the AD669 using the AD586 5 V reference in jority of this drift, an external high precision voltage reference
the bipolar configuration. This circuit includes two optional po- will greatly improve performance over temperature. As shown in
tentiometers and one optional resistor that can be used to adjust Figure 6, the +10 volt output from the AD688 is used as the
the gain, offset and bipolar zero errors in a manner similar to AD669 reference. With a 3 ppm/°C drift over the industrial
that described in the BIPOLAR CONFIGURATION section. temperature range, the AD688 will improve the gain drift by a
Use –5.000000 V and +4.999847 as the output values. factor of 5 to a factor of 8 (depending upon the grade of the
AD669 being used). Using this combination may result in ap-
50Ω parent increases in initial gain error due to the differences
(MSB) (LSB) between the internal reference by which the device is laser
DB15 DB0 trimmed and the external reference with which the device is ac-
2 22
+VCC
7
tually applied. The AD669 internal reference is specified to be
6 CS
SPAN/BIP 26
10 volts ± 20 mV whereas the AD688 is specified as 10 volts
AD586
5 L1 OFFSET
± 5 mV. This may result in an additional 5 mV (33 LSBs) of ap-
23 LDAC
parent initial gain error beyond the specified AD669 gain error.
25 OUTPUT
VOUT 6 27 REF IN AD669 The circuit shown in Figure 6 also makes use of the –10 V
R1
100Ω 28 REF OUT
24 GND
AD688 output to allow the unipolar offset and gain to be ad-
R2 –V EE +VCC +V LL justed to zero in the manner described in the UNIPOLAR
TRIM 5
GND 10kΩ
1 2 3 4 CONFIGURATION section.
4

Figure 5. Using the AD669 with the AD586 5 V Reference

(MSB) (LSB)
DB15 DB0

7 22
7 6 4 3

A3 1 CS 6 R3
16-BIT LATCH 20k
10k
A1 R1 R4
RS L1 5 26 10kΩ
AD688 100Ω
R4
LDAC 23 16-BIT LATCH 10.05k
14
R1 R2
R2 R5 100Ω
A4 15 10k
27 16-BIT DAC OUTPUT
AMP 25
R6 2 +VCC 0 TO +10V
R3 A2

16 –VEE 28 24 GND
10V REF AD669
5 9 10 8 12 11 13

1 2 3 4

-VEE +VCC +VLL

Figure 6. Using the AD669 with the AD688 High Precision ± 10 V Reference

REV. A –7–
AD669
OUTPUT SETTLING AND GLITCH DIGITAL CIRCUIT DETAILS
The AD669’s output buffer amplifier typically settles to within The bus interface logic of the AD669 consists of two indepen-
0.0008% FS (l/2 LSB) of its final value in 8 µs for a full-scale dently addressable registers in two ranks. The first rank consists
step. Figures 7a and 7b show settling for a full-scale and an LSB of a 16-bit register which is loaded directly from a 16-bit micro-
step, respectively, with a 2 kΩ, 1000 pF load applied. The guar- processor bus. Once the 16-bit data word has been loaded in the
anteed maximum settling time at +25°C for a full-scale step is first rank, it can be loaded into the 16-bit register of the second
13 µs with this load. The typical settling time for a 1 LSB step is rank. This double-buffered organization avoids the generation of
2.5 µs. spurious analog output values.
The digital-to-analog glitch impulse is specified as 15 nV-s typi- The first rank latch is controlled by CS and L1. Both of these
cal. Figure 7c shows the typical glitch impulse characteristic at inputs are active low and are level-triggered. This means that
the code 011 . . . 111 to 100 . . . 000 transition when loading data present during the time when both CS and L1 are low will
the second rank register from the first rank register. enter the latch. When either one of these signals returns high,
the data is latched.
600 The second rank latch is controlled by LDAC. This input is ac-
tive high and is also level-triggered. Data that is present when
+10 400
LDAC is high will enter the latch, and hence the DAC will
200 change state. When this pin returns low, the data is latched in
VOLTS

the DAC.
µV
0 0

–200 Note that LDAC is not gated with CS or any other control sig-
–400
nal. This makes it possible to simultaneously update all of the
–10
AD669’s present in a multi-DAC system by tying the LDAC
–600 pins together. After the first rank register of each DAC has been
individually loaded and latched, the second rank registers are
0 10 20 then brought high together, updating all of the DACs at the
µs
same time. To reduce bit skew, it is suggested to leave 100 ns
a. –10 V to +10 V Full-Scale Step Settling between the first rank load and the second rank load.
The first rank latch and second rank latch can be used together
in a master-slave or edge-triggered configuration. This mode of
600 operation occurs when LDAC and CS are tied together with L1
400
tied to ground. Rising edges on the LDAC-CS pair will update
the DAC with the data presented preceding the edge. The tim-
200
ing diagram for operation in this mode can be seen in Figure lb.
µV

0 Note, however, that the sum of tLOW and tHIGH must be long
–200 enough to allow the DAC output to settle to its new value.
–400
Table I. AD669 Truth Table
–600
CS L1 LDAC Operation
0 1 2 3 4 5
µs 0 0 X First Rank Enable
X 1 X First Rank Latched
b. LSB Step Settling 1 X X First Rank Latched
X X 1 Second Rank Enabled
X X 0 Second Rank Latched
0 0 1 All Latches Transparent
+10 “X” = Don’t Care
It is possible to make the second rank register transparent by ty-
mV

0 ing Pin 23 high. Any data appearing in the first rank register will
then appear at the output of the DAC. It should be noted, how-
ever, that the deskewing provided by the second rank latch is
–10
then defeated, and glitch impulse may increase. If it is desired to
make both registers transparent, this can be done by tying Pins
5 and 6 low and Pin 23 high. Table I shows the truth table for
0 1 2 3 4 5 the AD669, while the timing diagram is found in Figure 1.
µs

c. D-to-A Glitch Impulse INPUT CODING

Figure 7. Output Characteristics The AD669 uses positive-true binary input coding. Logic “1” is
represented by an input voltage greater than 2.0 V, and Logic
“0” is defined as an input voltage less than 0.8 V.

–8– REV. A
 AD669
Unipolar coding is straight binary, where all zeros (0000H) on +5V
the data inputs yields a zero analog output and all ones
(FFFFH) yields an analog output 1 LSB below full scale.
VLL
Bipolar coding is offset binary, where an input code of 0000H A0
yields a minus full-scale output, an input of FFFFH yields an ADDRESS BUS
output 1 LSB below positive full scale, and zero occurs for an A13

input code with only the MSB on (8000H). ADSP-2101

DECODER VLL
The AD669 can be used with twos complement input coding if DMS CS1 LDAC
an inverter is used on the MSB (DB15). CS AD669 VOUT
WR L1
DIGITAL INPUT CONSIDERATIONS DB0 DB15 DGND

The threshold of the digital input circuitry is set at 1.4 volts. D8

The input lines can thus interface with any type of 5 volt logic. DATA BUS
D23
The AD669 data and control inputs will float to indeterminate DGND
logic states if left open. It is important that CS and L1 be con-
nected to DGND and Chat LDAC be tied to VLL if these pins
are not used.
a. ADSP-2101 to AD669 Interface
Fanout for the AD669 is 40 when used with a standard low
power Schottky gate output device.
A13

16-BIT MICROPROCESSOR INTERFACE A12

The 16-bit parallel registers of the AD669 allow direct interfac- CS1
ing to 16-bit general purpose and DSP microprocessor buses.
A11
The following examples illustrate typical AD669 interface
configurations. DMS

AD669 TO ADSP-2101 INTERFACE

The flexible interface of the AD669 minimizes the required
“glue” logic when it is connected in configurations such as the b. Typical Address Decoder
one shown in Figure 8. The AD669 is mapped into the ADSP-
2101’s memory space and requires two wait states using a 12.5 Figure 8. ADSP-2101 to AD669 Interface
MHz processor clock. Figure 8b shows the circuitry a typical decoder might include.
In this configuration, the ADSP-2101 is set up to use the inter- In this case, a data memory write to any address in the range
nal timer to interrupt the processor at the desired sample rate. 3000H to 3400H will result in the AD669 being updated. These
The WR pin and data lines D8–D23 from the ADSP-2101 are decoders will vary greatly depending on the number of devices
tied directly to the L1 and DB0 through DB15 pins of the memory-mapped by the processor.
AD669, respectively. The decoded signal CS1 is connected to AD669 TO DSP56001 INTERFACE
both CS and LDAC. When a timer interrupt is detected, the Figure 9 shows the interface between the AD669 and the
ADSP-2101 automatically vectors to the appropriate service DSP56001. Like the ADSP-2101, the AD669 is mapped into
routine with minimal overhead. The interrupt routine then in- the DSP56001’s memory space. This application was tested
structs the processor to execute a data memory write to the ad- with a processor clock of 20.48 MHz (tCYC = 97.66 ns) although
dress of the AD669. faster rates are possible.
The WR pin and CS1 both go low causing the first 16-bit latch An external clock connected to the IRQA pin of the DSP56001
inside the AD669 to be transparent. The data present in the first interrupts the processor at the desired sample rate. If ac perfor-
rank is then latched by the rising edge of WR. The rising edge mance is important, this clock should be synchronous with the
of CS1 will cause the second rank 16-bit latch to become DSP56001 processor clock. Asynchronous clocks will cause jit-
transparent updating the output of the DAC. The length of ter on the latch signal due to the uncertainty associated with the
WR is extended by two wait states to comply with the timing acknowledgment of the interrupt. A synchronous clock is easily
requirements of tLOW shown in Figure 1b. It is important to generated by dividing down the clock from the DSP crystal. If
latch the data with the rising edge of WR rather than the decoded ac performance is not important, it is not necessary for IRQA to
CS1. This is necessary to comply with the tDH specification of be synchronous.
the AD669.
After the interrupt is acknowledged, the interrupt routine ini-
tiates a memory write cycle. All of the AD669 control inputs are

REV. A –9–
AD669
tied together which configures the input stage as an edge trig- The same procedure is repeated until all three AD669s have had
gered 16-bit register. The rising edge of the decoded signal their first rank latches loaded with the desired data. A final write
latches the data and updates the output of the DAC. It is neces- command to the LDAC address results in a high-going pulse
sary to insert wait states after the processor initiates the write that causes the second rank latches of all the AD669s to become
cycle to comply with the timing requirements tLOW shown in transparent. The falling edge of LDAC latches the data from the
Figure 1b. The number of wait states that are required will vary first rank until the next update. This scheme is easily expanded
depending on the processor cycle time. The equation given in to include as many AD669s as required.
Figure 9 can be used to determine the number of wait states
+5V
given the frequency of the processor crystal.

+5V VLL
AD0 – AD15

VLL DB0 – DB15 VLL

WR ADDRESS
A0–A15 CS VOUT
M/I0 DECODE AD669
LDAC
VLL ALE LDAC CS1 CS2 CS3 DGND L1
DS ADDRESS
X/Y DECODE AD669
XTAL 8086
CS DB0 – DB15 VLL
DSP56001 CS1
L1 DGND CS
WR AD669 VOUT
LDAC LDAC
74F32
DGND L1
DGND
EXTERNAL
IRQA
CLOCK
DB0–DB15 DB0 – DB15 VLL
D0–D23 CS
AD669 VOUT
DGND LDAC
DGND L1

# OF t LOW – T + 9ns
WAIT STATES =
2T
T=
1 Figure 10. 8086-to-AD669 Interface
2 (XTAL)

8-BIT MICROPROCESSOR INTERFACE

Figure 9. DSP56001 to AD669 Interface The AD669 can easily be operated with an 8-bit bus by the ad-
As an example, the 20.48 MHz crystal used in this application dition of an octal latch. The 16-bit first rank register is loaded
results in T = 24.4 ns which means that the required number of from the 8-bit bus as two bytes. Figure 11 shows the configura-
wait states is about 2.76. This must be rounded to the next tion when using a 74HC573 octal latch.
highest integer to assure that the minimum pulse widths comply The eight most significant bits are latched into the 74HC573 by
with those required by the AD669. As the speed of the proces- setting the “latch enable” control line low. The eight least sig-
sor is increased, the data hold time relative to CS1 decreases. As nificant bits are then placed onto the bus. Now all sixteen bits
processor clocks increase beyond 20.48 MHz, a configuration can be simultaneously loaded into the first rank register of the
such as the one shown for the ADSP-2101 is the better choice. AD669 by setting CS and L1 low.
AD669 TO 8086 INTERFACE
Figure 10 shows the 8086 16-bit microprocessor connected to
11
multiple AD669s. The double-buffered capability of the AD669 CS1 L1 LDAC
allows the microprocessor to write to each AD669 individually D7 D7 Q7 MSB
and then update all the outputs simultaneously. Processor
D0 Q0 DB8
speeds of 6, 8, and 10 MHz require no wait states to interface 8-BIT µP
with the AD669. AND 74HC573 AD669
CONTROL
DB7
The 8086 software routine begins by writing a data word to the
CS1 address. The decoder must latch the address using the D0 LSB
ALE signal. The decoded CS1 pulse goes low causing the first
rank latch of the associated AD669 to become transparent.
Figure 11. Connections for 8-Bit Bus Interface
Simultaneously, the 8086 places data on the multiplexed bus
which is then latched into the first rank of the AD669 with the
rising edge of the WR pulse. Care should be taken to prevent
excessive delays through the decoder potentially resulting in a
violation of the AD669 data hold time (tDH).

–10– REV. A
 AD669
NOISE Analog and digital signals should not share a common path.
In high resolution systems, noise is often the limiting factor. A Each signal should have an appropriate analog or digital return
16-bit DAC with a 10 volt span has an LSB size of 153 µV routed close to it. Using this approach, signal loops enclose a
(–96 dB). Therefore, the noise floor must remain below this small area, minimizing the inductive coupling of noise. Wide PC
level in the frequency range of interest. The AD669’s noise tracks, large gauge wire, and ground planes are highly recom-
spectral density is shown in Figures 12 and 13. Figure 12 shows mended to provide low impedance signal paths. Separate analog
the DAC output noise voltage spectral density for a 20 V span and digital ground planes should also be utilized, with a single
excluding the reference. This figure shows the l/f corner frequency interconnection point to minimize ground loops. Analog signals
at 100 Hz and the wideband noise to be below 120 nV/√Hz. should be routed as far as possible from digital signals and
Figure 13 shows the reference noise voltage spectral density. should cross them at right angles.
This figure shows the reference wideband noise to be below One feature that the AD669 incorporates to help the user layout
125 nV/√Hz. is the analog pins (VCC, VEE, REF OUT, REF IN, SPAN/BIP
OFFSET, VOUT and AGND) are adjacent to help isolate analog
1000
signals from digital signals.
Hz

SUPPLY DECOUPLING
NOISE VOLTAGE – nV/

100 The AD669 power supplies should be well filtered, well regu-
lated, and free from high frequency noise. Switching power sup-
plies are not recommended due to their tendency to generate
10
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout prox-
imity between all power supply pins and ground. A 10 µF tanta-
lum capacitor in parallel with a 0.1 µF ceramic capacitor
1
1 10 100 1k 10k 100k 1M 10M provides adequate decoupling. VCC and VEE should be bypassed
FREQUENCY – Hz to analog ground, while VLL should be decoupled to digital
ground.
Figure 12. DAC Output Noise Voltage Spectral Density
An effort should be made to minimize the trace length between
1000
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD669, associated analog circuitry and interconnections as
Hz

far as possible from logic circuitry. A solid analog ground plane

NOISE VOLTAGE – nV/

100 around the AD669 will isolate large switching ground currents.
For these reasons, the use of wire wrap circuit construction
is not recommended; careful printed circuit construction is
preferred.
10

GROUNDING
The AD669 has two pins, designated analog ground (AGND)
1 and digital ground (DGND.) The analog ground pin is the
1 10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz
“high quality” ground reference point for the device. Any exter-
nal loads on the output of the AD669 should be returned to
Figure 13. Reference Noise Voltage Spectral Density analog ground. If an external reference is used, this should also
be returned to the analog ground.
BOARD LAYOUT If a single AD669 is used with separate analog and digital
Designing with high resolution data converters requires careful ground planes, connect the analog ground plane to AGND and
attention to board layout. Trace impedance is the first issue. A the digital ground plane to DGND keeping lead lengths as short
306 µA current through a 0.5 Ω trace will develop a voltage as possible. Then connect AGND and DGND together at the
drop of 153 µV, which is 1 LSB at the 16-bit level for a 10 V AD669. If multiple AD669s are used or the AD669 shares ana-
full-scale span. In addition to ground drops, inductive and ca- log supplies with other components, connect the analog and
pacitive coupling need to be considered, especially when high digital returns together once at the power supplies rather than at
accuracy analog signals share the same board with digital sig- each chip. This single interconnection of grounds prevents large
nals. Finally, power supplies need to be decoupled in order to ground loops and consequently prevents digital currents from
filter out ac noise. flowing through the analog ground.

REV. A –11–
 AD669

–12–
REV. A
PRINTED IN U.S.A. C1555–10–11/91