cd00211314 How To Get The Best Adc Accuracy in stm32 Microcontrollers Stmicroelectronics
cd00211314 How To Get The Best Adc Accuracy in stm32 Microcontrollers Stmicroelectronics
Application note
How to get the best ADC accuracy
in STM32 microcontrollers
Introduction
STM32 microcontrollers embed advanced 12-bit or 16-bit ADCs (depending on the device).
A self-calibration feature is provided to enhance ADC accuracy versus environmental
condition changes.
In applications involving analog-to-digital conversion, ADC accuracy has an impact on the
overall system quality and efficiency. To improve this accuracy, the errors associated with
the ADC and the parameters affecting them must be understood.
ADC accuracy does not only depend on ADC performance and features, but also on the
overall application design around the ADC.
This application note aim is to help understand ADC errors and explain how to enhance
ADC accuracy. It is divided into three main parts:
• a simplified description of ADC internal structure to help understand ADC operation and
related ADC parameters
• explanations of the different types and sources of ADC errors related to the ADC design
and to external ADC parameters such as the external hardware design
• recommendations on how to minimize these errors, focusing on hardware and software
methods
Contents
1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 ADC errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Errors due to the ADC itself . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1 Offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.2 Gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.3 Differential linearity error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.4 Integral linearity error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.5 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Errors due to the ADC environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.1 Reference voltage noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.2 Reference voltage / power supply regulation . . . . . . . . . . . . . . . . . . . . . 17
3.2.3 Reference voltage decoupling and impedance . . . . . . . . . . . . . . . . . . . 18
3.2.4 External reference voltage parameters . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.5 Analog input signal noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.6 ADC dynamic range bad match for maximum input signal amplitude . . 18
3.2.7 Effect of the analog signal source resistance . . . . . . . . . . . . . . . . . . . . 19
3.2.8 Effect of source capacitance and parasitic capacitance of the PCB . . . 20
3.2.9 Injection current effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.10 Temperature influence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.11 I/O pin crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.12 EMI-induced noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
List of tables
Table 1. Minimum sampling time for STM32H7 Series devices (in ns) . . . . . . . . . . . . . . . . . . . . . . 33
Table 2. ADC SMP selection vs STM32 Series (in ADC clock cycles) . . . . . . . . . . . . . . . . . . . . . . . 34
Table 3. Rounded minimum sampling time vs resolution
and maximum error (in ADC clock cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 4. Minimum SMP values vs resolution and maximum error
(in ADC clock cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 5. Additional ADC clock cycles due to SMP
vs resolution and maximum error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 6. Minimum ADC conversion time (TSMPL + TSAR) vs resolution
and maximum error (in ADC clock cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7. Maximum ADC output sampling rate (MSPS)
vs resolution and maximum error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
List of figures
1 General information
VREF
VIN
Sa
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11
C C/2 C/4 C/8 C/16 C/32 C/64 C/128 C/256 C/512 C/512
Sb A D PR Q ADC Data
CLK
CLR
ADC Clk
ai17097b
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
VREF
VIN
Sa
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11
C C/2 C/4 C/8 C/16 C/32 C/64 C/128 C/256 C/512 C/512
Sb A D PR Q ADC Data
CLK
CLR
ADC Clk
VCOMP= 0
2C
VIN
Equivalent circuit: A
ai17098b
1. Sample state: capacitors are charging to VIN voltage. Sa switched to VIN, Sb switch closed during sampling
time.
VREF
VIN
Sa
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11
C C/2 C/4 C/8 C/16 C/32 C/64 C/128 C/256 C/512 C/512
Sb A D PR Q ADC Data
CLK
CLR
ADC Clk
VCOMP= –VIN
2C
Equivalent circuit: A
ai17099b
1. Hold state: the input is disconnected, capacitors hold input voltage. Sb switch is open, then S1-S11
switched to ground and Sa switched to VREF.
VREF
VIN
Sa
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11
C C/2 C/4 C/8 C/16 C/32 C/64 C/128 C/256 C/512 C/512
Sb A D PR Q ADC Data
CLK
CLR
ADC Clk
VCOMP= –VIN+ VREF/2
C
VREF
Equivalent circuit: C A
ai17800b
VREF
VIN
Sa
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11
C C/2 C/4 C/8 C/16 C/32 C/64 C/128 C/256 C/512 C/512
Sb A D PR Q ADC Data
CLK
CLR
ADC Clk
VCOMP= –VIN+ 1/4 VREF
C/2
VREF
Equivalent circuit: 3C/2 A
ai17801b
1. Compare with ¼VREF; if MSB =1. S1 switched back to ground. S2 switched to VREF.
VREF
VIN
Sa
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11
C C/2 C/4 C/8 C/16 C/32 C/64 C/128 C/256 C/512 C/512
Sb A D PR Q ADC Data
CLK
CLR
ADC Clk
VCOMP= –VIN+ 3/4VREF
3C/2
VREF
Equivalent circuit: C/2 A
ai17802b
1. Compare with ¾VREF; if MSB =0. S1 remained switched to ground. S2 switched to VREF.
3 ADC errors
This section lists the main errors that have an effect on A/D conversion accuracy. These
types of errors occur in all A/D converters and conversion quality depends on their
elimination. These error values are specified in the ADC characteristics section of STM32
microcontroller datasheets.
Different accuracy error types are specified for the STM32 ADC. For easy reference,
accuracy errors are expressed as multiples of 1 LSB. The resolution in terms of voltage
depends on the reference voltage. The error in terms of voltage is calculated by multiplying
the number of LSBs by the voltage corresponding to 1 LSB (1 LSB = VREF+/212 or
VDDA/212).
Example
For the STM32 ADC, the smallest detectable incremental change in voltage is expressed in
terms of LSBs:
1 LSB = VREF+/4096 (on some packages, VREF+ = VDDA).
If VREF+ = 3.3 V, the input of 402.8 µV (0.5 LSB = 0.5 × 805.6 µV) should ideally lead to the
generation of a digital output of 1. In practice, however, the ADC may still provide a reading
of 0. If a digital output of 1 is obtained from an analog input of 550 µV, then:
Offset error = Actual transition – Ideal transition
EO = 550 µV – 402.8 µV = 141.2 µV
EO = 141.2 µV / 805.6 µV = 0.17 LSB
When an analog input voltage greater than 0.5 LSB generates the first transition, the offset
error is positive (refer to Figure 7 for an example of positive offset error).
Digital output
EO > 0
2
Actual transfer curve
1
0 VAIN
0.5LSB
ai15475b
When an analog input voltage of less than 0.5 LSB generates the first transition, the offset
error is negative (refer to Figure 8 for an example of negative offset error).
If the analog input voltage (VAIN) is equal to VSSA and the ADC generates a non-zero digital
output, the offset error is negative. This means that a negative voltage generates the first
transition.
Digital output
EO > 0
Actual transfer curve
2
1
0 VAIN
0.5LSB
ai15476b
Example
The gain error is obtained by the formula below:
EG = Last actual transition – ideal transition
If VREF+ = 3.3 V and VAIN = 3.298435 V generate a transition from 0xFFE to 0xFFF then:
EG = 3.298435 V – 3.299597 V
EG = –1162 µV
EG = (–1162 µV / 805.6 V) LSB = –1.44 LSB
If a full scale reading (0xFFF) is not obtained for VAIN equal to VREF+, the gain error is
positive. This means that a voltage greater than VREF+ will cause the last transition. Figure 9
shows a positive gain error while Figure 10 shows a a negative gain error.
Digital output
4095
EG > 0
VAIN
4094.5
LSB
ai5477b
Digital output
4095
EG < 0
Ideal transfer curve
VAIN
4094.5
LSB
ai15478b
Example
A given digital output should correspond to an analog input range. Ideally, the step width
should be 1 LSB. Let us assume that the digital output is the same over an analog input
voltage range of 1.9998 V to 2.0014 V, the step width will be:
2.0014 V – 1.9998 V = 1.6 mV.
ED is thus the voltage difference between the higher (2.0014 V) and the lower (1.9998 V)
analog voltages minus the voltage corresponding to 1 LSB.
Actual
Digital output Step
width 1LSB
ED > 0
ED < 0
Ideal transfer curve
Actual transfer curve
VAIN
ai15479b
If VREF+ = 3.3 V, an analog input of 1.9998 V (0x9B1) can provide results varying between
0x9B0 and 0x9B2. Similarly, for an input of 2.0014 V (0x9B3), the results may vary between
0x9B2 and 0x9B4.
As a result, the total voltage variation corresponding to the 0x9B2 step is:
0x9B3 – 0x9B1, that is, 2.0014 V – 1.9998 V = 1.6 mV (1660 µV)
ED = 1660 µV – 805.6 µV
ED = 854.4 µV
ED = (854.4 µV/805.6 µV) LSB
ED = 1.06 LSB
Digital output
4095
EL
2
Actual transfer curve
1
0 VAIN
550 • •V 3.298435 V
ai15480b
Example
If the first transition from 0 to 1 occurs at 550 µV and the last transition (0xFFE to 0xFFF)
occurs at 3.298435 V (gain error), then the line on the transfer curve that connects the
actual digital codes 0x1 and 0xFFF is the endpoint correlation line.
Example
If VREF+ = 3.3 V and VAIN = 2 V, the ideal result is 0x9B2.
TUE = absolute (actual value – ideal case value) = 0x9B4 – 0x9B2 = 0x2 = 2 LSB
Digital output
ET
VAIN
ai15481b
12
1 × (2 – 1)
Digital output = ---------------------------------- = 0x4D9
3.3
If the voltage supply provides a voltage equal to 3.292 V (after its output connection to
VREF+), then:
12
1 × (2 – 1)
Digital output = ---------------------------------- = 0x4DC
3.292
The error introduced by the voltage drop is: 0x4DC – 0x4D9 = 3 LSB.
3.2.6 ADC dynamic range bad match for maximum input signal amplitude
To obtain the maximum ADC conversion precision, it is very important that the ADC dynamic
range matches the maximum amplitude of the signal to be converted. Let us assume that
the signal to be converted varies between 0 V and 2.5 V and that VREF+ is equal to 3.3 V.
The maximum signal value converted by the ADC is 3102 (2.5 V) as shown in Figure 14. In
this case, there are 993 unused transitions (4095 – 3102 = 993). This implies a loss in the
converted signal accuracy.
See Section 4.2.5: Matching the ADC dynamic range to the maximum signal amplitude on
page 27 for details on how to make the ADC dynamic range match the maximum input
signal amplitude.
V
VREF+ = 3.3 V(0x4095)
2.5 V(0x3102)
ai15499b
The effective charging of CADC is governed by RADC + RAIN, so the charging time constant
becomes tc = (RADC+RAIN) × CADC. If the sampling time is less than the time required to fully
charge the CADC through RADC + RAIN (ts < tc), the digital value converted by the ADC is
less than the actual value.
STM32
VAIN RADC
RAIN AINX
CADC
VC
VAIN
VC
tC t
ai15482b
1. tc is the time taken by the CADC capacitor to fully charge: Vc = VAIN (with max.1/2 LSB error)
Vc: capacitor (CADC) voltage
tc = (RADC + RAIN) × CADC
STM32
Source
VAIN
RAIN AINX
CAIN CP
ai15483b
leakage
current
AIN1
VSSA
ai15484
Analog Analog
in STM32 in STM32
Digital Digital
I/O I/O
Case 1 Case 2
ai15485
1. Case 1: Digital and analog signal tracks that pass close to each other.
2. Case 2: Digital and analog signal tracks that cross each other on a different PCB side.
Electro- I/O
magnetic coupled
noise noise STM32
ADC
ai15486
To filter high-frequency noise, a ferrite inductance in series with the power supply can be
used. This solution leads to very low (negligible) DC loss unless the current is high because
the series resistance of the wire is very low. At high frequencies, however, the impedance is
high.
The inductance must be small enough not to limit high current peak requirements from the
supply pins. The inductance together with the decoupling capacitor is a LC circuit which can
start to oscillate if there is a fast voltage drop on the decoupling capacitor, caused by a
change of consumption (on VDDA, VDD, VREF+). The oscillations can take more time and
influence the ADC measurement (oscillations on VREF+ during conversion). To suppress
these oscillations, it is recommended to use small inductances and with ferrite cores which
have losses at high frequencies (resistive character of the impedance).
Figure 20. Power supply and reference decoupling for 100- and 144-pin packages
VDDA VDDA
VREF+ VREF+
1 μF // 10 nF 1 μF // 10 nF
1 μF // 10 nF VREF– VREF–
VSSA VSSA
ai15487b
Figure 21. Power supply decoupling for 36-, 48- and 64-pin packages
VDDA
1 μF // 10 nF
VSSA
ai15488
operations (accumulation and right-bit shifting) are performed by hardware. The ADC
hardware oversampling feature can be configured to process up to 1024 input samples
(depending on devices).
UOUT
VDD
t
R1
OUT
C
R2
AIN
VIN
MCU
UIN
VIN
ai17803b
4.2.5 Matching the ADC dynamic range to the maximum signal amplitude
This method improves accuracy by a proper selection of the reference voltage or by using a
preamplifier stage to obtain the maximum possible resolution using the full ADC output
range.
V V
VREF+= 3.3 V VREF+= 2.5 V
(0x4095) unused ADC (0x4095)
transition range Change VREF+
2.5 V value from
(0x3102) 3.3 V to 2.5 V
t t
4095 4095 - x VIN
Digital Output= ------------
- x VIN Digital Output= ------------
3.3 2.5
ai15600b
Using a preamplifier
If the measured signal is too small (in comparison with the ADC range), then an external
preamplifier can be useful. This method can be implemented whatever the STM32 package,
and more specifically in packages that do not have a VREF+ input.
For example, if the measured signal varies between 0 V to 1 V and VDDA is set to 3 V, the
signal can be amplified so that its peak-to-peak amplitude is similar to the VDDA value. The
gain is then equal to 3 (see Figure 24 for an example).
This amplifier can adapt the input signal range to the ADC range. It can also insert offsets
between the input signal and the ADC input. When designing the preamplifier, care must be
taken not to generate additional errors (such as additional offset, amplifier gain stability or
linearity, frequency response).
V V
VDDA= 3 V Input signal max
(0x4095) unused ADC value is 3 V
transition range (0x4095)
1V G=3
(0x1365)
t t
Before amplification After amplification
4095 - x VIN 4095 x G x V
DigitalOutput = ------------ Digital Output= IN
3 3
ai15601b
MSv66807V1
The following paragraph describes the two successive operations required for sample
conversion:
1. Sampling
This operation samples the analog input signal by charging the internal ADC sampling
capacitor (CADC).
The duration of this operation is TSMPL. It depends on the SMP parameter that is
configured in the ADC configuration register to select the sampling time duration.
2. Bit conversion
This operation converts the analog value stored in the CADC sampling capacitor to a
digital value.
The duration of this operation is TSAR. It depends on the RES parameter that is
configured in ADC configuration register to select the ADC bit resolution.
ADC sample conversion time ( T CONV ) = Sampling time ( T SMPL ) + Bit conversion time (T SAR )
Both TSMPL and TSAR durations are relative to multiple of ADC clock cycles:
• TSMPL duration:
This duration depends on the SMP parameter (ADC sampling duration). As an
example, SMP values for STM32L5 Series can be 2.5, 6.5, 12.5, 24.5, 47.5, 92.5,
247.5 or 640.5 ADC clock cycles.
• TSAR duration:
This duration depends on the RES parameter (ADC bit resolution). As an example,
RES values for STM32L5 Series can be 6.5, 8.5, 10.5 and 12.5 ADC clock cycles for 6,
8, 10 and 12-bit resolution.
The ADC sampling rate or sample conversion time (TCONV) can be calculated using the
following formula:
T CONV = T SMPL + T SAR = 2.5 × T ADC_CLK + 12.5 × T ADC_CLK = 15 × T ADC_CLK
= 15 × 1 ⁄ F ADC_CLK = 15 × 20 ns = 300 ns
6
ADC sample rate = 1 ⁄ T CONV = 3.33 samples per second or 3.33 MSPS
where
FADC_CLK = 50 MHz
TSMPL = 2.5 clock cycles
TSAR = 12.5 (ADC 12-bit resolution):
Mux input
GND
MSv66808V2
Based on the above constraints, the minimum TSMPL required to achieve the maximum
output sampling rate can then be estimated.
The device datasheet provides a few TSMPL values to obtain a maximum accuracy of ± 1/2
LSB for each channel type, different RAIN values, a given CAIN/CPCB capacitor, and in the
worst conditions of package dimensions, temperature, manufacturing process and supply
voltages.
Figure 27 and Figure 28 show the impact of the desired accuracy (from ± 0.5 to ± 3 LSB)
and ADC resolution (expressed in LSB) on the input signal to reach the voltage accuracy.
When the resolution is low and the error accuracy is high, the required signal sampling time
is short, whereas when the resolution is high and the error accuracy is low, the required
signal sampling time is long.
Figure 27 shows that the sampling duration increases with the ADC resolution. It also shows
the voltage variation on the STM32 ADC analog input pin. The first ADC conversion starts at
0 ns. For negative timings, the curve shows the input voltage state before the first ADC
conversion.
Figure 27. Example of SAR ADC input sampling time vs ADC resolution
Figure 28 shows that the sampling duration has to be increased to achieve a higher
accuracy: a 23.8 ns sampling duration is required to obtain a 12-bit resolution and ± 3 LSB,
whereas a 40.4 ns duration is needed for 12 bits and ± 0.5 LSB.
Table 1 gives examples of sampling time for STM32H7 Series with RAIN = 1 kΩ,
CAIN/CPCB = 2 nF, VREF+ = 2 V and FADC = 20 MHz.
Table 1. Minimum sampling time for STM32H7 Series devices (in ns)
Acquisition
8 bits 10 bits 12 bits 14 bits 16 bits
accuracy
When the ADC resolution is 8 bits and the acquisition accuracy is greater than ± 1 LSB,
TSMPL can be minimized to a few picoseconds due to LSB amplitude, whereas with an ADC
resolution is 16 bits and an acquisition accuracy equal to ± 0.5 LSB, T SMPL maximum value
is 67.1 ns.
SAR ADC conversion duration and sampling rate dependency versus SMP
The ADC SMP parameter enables programming the duration of the ADC sampling
operation to a given number of ADC clock cycles. SMP can be selected among a list of
values that depends on each STM32 Series (see Figure 29 and Table 2). To match the
requirements of wide frequency-range applications, SMP values approximately follow a
logarithm law.
Table 2. ADC SMP selection vs STM32 Series (in ADC clock cycles)
STM32L4/
ADC SMP STM32L0/ STM32L5/
STM32F1 STM32L1 STM32F7 STM32H7
code STM32G0 STM32G4/
STM32WB
The distribution of ADC SMP values is a constraint to optimize the ADC sampling time. In
the following example, which is based on STM32H7 Series, some application conditions are
optimized.
Table 3 to Table 7 show examples of results for STM32H7 Series obtained with RAIN = 1 kΩ,
CAIN/CPCB = 2 nF, VREF+ = 2 V and FADC = 20 MHz.
Table 3 shows the real minimum sampling time expressed in ADC clock cycles (sampling
duration / ADC clock period) corresponding to Table 1.
± 0.5 LSB 4 6 9 11 14
± 1 LSB 2 5 7 10 13
± 2 LSB 1 4 6 9 11
± 3 LSB 1 3 5 8 11
For STM32H7 Series, TSMPL can be programmed to the following values, through the SMP
parameter: 1.5, 2.5, 8.5, 16.5, 32.5, 64.5, 387.5 or 810.5 ADC clock cycles. Table 4 shows
the minimum SMP value required to reach various input sampling accuracies:
Table 5 gives additional clock cycles between the real minimum sampling time and the
corresponding minimum SMP value.
In normal application conditions, an optimized sampling time is achieved for an 8-bit ADC
resolution and an accuracy greater than ± 1 LSB, while non- optimized sampling times are
obtained for a 12-bit ADC resolution and an accuracy lower than ± 1 LSB, and 14-bit and
16-bit resolution with an accuracy lower than ± 3 LSB.
Table 6 shows the total conversion times including TSAR duration and the computed ADC
output sampling rate (TSMPL). For STM32H7 Series, TSAR can be programmed to the
following values: 4.5, 5.5, 6.5, 7.5 or 8.5 ADC clock cycles for ADC resolutions of 8-, 10-,
12-, 14- and 16 bit resolutions.
± 0.5 LSB 13 14 23 24 25
± 1 LSB 7 14 15 24 25
± 2 LSB 6 14 15 24 25
± 3 LSB 6 14 15 16 25
The maximum ADC output sampling rate for this application conditions can then be
computed.
When the ADC resolution is 8 bits and the acquisition accuracy is above ± 2 LSB, the
maximum ADC sampling rate output 3.3 MSPS, is achieved with RAIN = 1 kΩ,
CAIN/CPCB = 2 nF, FADC = 20 MHz, and typical conditions of voltage, temperature, process,
package and number of ADCs running.
When the ADC resolution is 16 bits, the ADC sampling rate is reduced to 0.8 MSPS with an
acquisition accuracy lower than ± 3 LSB.
Figure 30. TSMPL estimation versus ADC frequency and comparison of minimum
TSMPL duration
for slow and fast channels with same RAIN/CAIN
1. The above results are obtained in the worst conditions of temperature, supply voltages and process.
Figure 31. TSMPL estimation versus ADC frequency and comparison of minimum
TSMPL duration
for fast channels with RAIN/CAIN = 51 Ω/10 pf and 100 Ω/33 pF
1. The above results are obtained in the worst conditions of temperature, supply voltage and process.
If the analog input signal changes, then the analog signal frequency (FAIN) should be such
that the time period of this analog signal is at least: 10 × RAIN × (CAIN + Cp).
TAIN = analog signal time period = 1/FAIN.
We have: T AIN ≥ 10 × R AIN × ( C AIN + C P )
1
Therefore: F AIN ≤ ---------------------------------------------------------------------
10 × R AIN × ( C AIN + C P )
For example:
For RAIN = 25 kΩ, CAIN = 7 pF, Cp = 3 pF, this gives:
1
F AINmax = ----------------------------------------------------------------------------------
3 – 12
10 × 25 × 10 × ( 7 + 3 ) × 10
Thus, the maximum frequency of the source will be: F AINmax = 400 kHz .
So for the above defined source characteristics (capacitance and resistance), the frequency
of the source must not exceed 400 kHz, otherwise the ADC conversion result will be not
accurate.
Figure 32. Recommended values for RAIN and CAIN vs. source frequency FAIN
1000
CAIN 10 nF
100
CAIN 22 nF
CAIN 47 nF
Max. RAIN (k¾ )
10
0.1
0.01 0.1 1 10
FAIN(kHz) ai15489
Analog
in STM32
Digital
I/O
ai15490
Shielding technique
Placing ground tracks alongside sensitive analog signals provides shielding on the PCB.
The other side of the two-layer PCB should also have a ground plane. This prevents
interference and I/O crosstalk affecting the signal (see Figure 34).
Signals coming from distant locations (such as sensors) should be connected to the PCB
using shielded cable. Care should be taken to minimize the length of the paths of these
types of signal on the PCB.
The shield should not be used to carry the ground reference from the sensor or analog
source to the microcontroller. A separate wire should be used as ground. The shield should
be grounded at only one place near the receiver such as the analog ground of the
microcontroller. Grounding the shield at both ends (source and receiver) might lead to the
creation of ground loops, with the result of current flowing through the shield. In this case,
the shield acts like an antenna and the purpose of the shielding is lost.
The shielding concept also applies to grounding the chassis of the application if it is metallic.
And it also helps remove EMI and EMC interference. In this case the mains earth ground is
used to shield the chassis. Similarly DC ground can be used for shielding in case of the
earth ground not being available.
Sensor Sensor
ADC ADC
Ground
loop
Do not ground the shield at both ends Ground the shield at the receiver end only ai15491
Power
supply
Digital Analog
circuitry STM32
circuitry
Digital Analog
ground ground
plane plane
ai15492b
Linear Vout1
regulator GND SMPS
Vout2
Star
Network V SS V DD
V DDA
V REF+
STM32
Analog
V REF-
Circuit
V SSA
ai15493b
It is also recommended to connect the analog and digital grounds in a star network. This
means that you must connect the analog and digital grounds at only one point. This
prevents the introduction of noise in the analog power supply circuit due to digital signal
switching. This also prevents current surges from affecting the analog circuit.
2 2 2
U ef = U1 + U2 + … + Un
So if the 15th harmonics amplitude is only 1% (0.01) from the 1st harmonics (50 Hz), then
its contribution to the total effective value will be only 0.01% (because the square addition in
the above equation gives: 0.012 = 0.0001).
The principle of this method is therefore to sample the AC signal with a known frequency
and then perform post-processing on the FFT for each measured period. Because the
number of sampling points per measured signal period is small (32 points for example) then
the performance needed for FFT processing is not so high (only 32-point FFT for example).
This method is well adapted for AC measurement of signals with lower distortion. The
drawback is that it requires precise signal sampling:
• The frequency of the measured signal must be known and the ADC sampling
frequency must be set exactly as a 2n multiplier of the measured frequency.
• The input signal frequency is measured by another method.
• The ADC sampling frequency is tuned by programming the prescaler and MCU master
clock selection (if sampling is performed with an inaccurate clock an interpolation can
be used to obtain samples at the required points).
ADC input
R in
U in STM32
C ext
ai17903b
Figure 38. Noise observed on ADC input pin during ADC conversions
ai17904b
Figure 39. ADC simplified schematic of input stage - sample and hold circuit
S1
ADC input
Csh
ai17905b
The spikes (noise) present on ADC input pin during conversions are related to the sampling
switch (S1). If the switch is closed, some charge (coming from the sample and hold
capacitor Csh or caused by another effect) is transferred to the input pin. Then this charge
starts discharging through the source impedance (Rin). The discharge process ends at the
end of the sampling time (tS) when the switch S1 is opened. The remaining undischarged
voltage remains on the capacitor Csh and ADC measures this voltage. If the sampling time
(tS) is too short, the remaining voltage does not drop under 0.5 LSB and ADC measurement
shows an additional error. Figure 40 illustrates this process.
Figure 40. ADC input pin noise spikes from internal charge during sampling process
Uinput
Added error
t
Sampling time
(tS) = Discharging
time
Conversion
time (tC)
ai17906b
Note that a non-zero external capacitance Cext (parasitic pin capacitance) also exists, so
during conversion time the pin capacitance is discharged through source impedance Rin.
N+1
T S ≥ f ADC ⋅ ( R in ⋅ C sh ) ⋅ ln ( 2 ) [ cycles ]
The ADC clock (fADC) is another important factor, since slowing down the ADC clock
increases the sampling time.
Original
sampling time
(tS)
Conversion
time (tC)
Extended
sampling time
(tS)
ai17907b
If the maximum register value of the sampling time (TS) setting is reached and the problem
is still present, you need a more complex solution which is applicable also for
measurements of source with extra high internal impedance (see Section : Workaround for
extra high impedance sources).
Note that for this application you must take into account not only the internal sampling
capacitance, but also any external parasitic capacitance (in parallel to Cext), such as pin
capacitance or PCB path capacitance.
Do not add any external capacitor (Cext) to the input pin when applying this above
workaround. Its capacity will increase the timing constant (Rin x Csh || Cext) and the problem
will remain.
U max 4096
C ext ≥ C sh ⋅ -------------- = 16pF ⋅ ------------- ≈ 131nF
U lsb 0.5
The closest larger standard value chosen here is: Cext = 150 nF.
If the internal sampling capacitor Csh is not charged to full voltage range (4096 level) before
sampling, the Cext value can be computed by replacing “4096” in the formula above.
Calculating with 4096 level gives precise measurement results also in the case of ADC input
channels switching (Csh was charged from different ADC input in the previous
measurement).
A side effect of this hardware workaround is the cyclical charging of Cext which must be
taken into account. Each ADC conversion transfers charge from Csh to Cext. One transfer
charges the Cext below 0.5 LSB, as described above, but more transfers can charge Cext to
larger values if it is not discharged between two conversions. Figure 42 shows an example
of this scenario where the ADC measurement is performed faster.
Figure 42. Charging the external capacitor with too short time between conversions
Added error > 0.5 lsb
Uinput
Too
short tC
Recommended
tC
ai17908b
Software change
The side effect mentioned above can be solved by software. The objective is to create a
delay in order to let Cext discharge through Rin (not measure so often) giving enough
“discharge time” between ADC conversions. The “discharge time” (tC) is equal to the
transferred charge from Csh to Cext (charging) and from Cext to Rin (discharging). The
assumption is that Cext >> Csh.
tC t
– -------------------
U lsb R in C ext
Q disch arg ing = ----------- ⋅ e dt
R in
0
where:
Ulsb ....... 0.5 LSB voltage level
Umax ..... 4096 LSB voltage level (worst case)
Qcharging = Qdischarging
tC t
-------------------
U lsb R in C ext
C sh ⋅ U max = ----------- ⋅ e dt
R in
0
Simplification of the above formula gives the final formula for the required waiting time
between conversions:
C sh U max
t C = – ( R in ⋅ C ext ) ⋅ In 1 – ----------- --------------
C ext U lsb
This final formula shows dependency between the external capacitor Cext and the required
waiting time between two conversions if the precision Ulsb is needed.
From the same formula you can see that the argument in logarithm must be positive and
therefore there is a condition for the minimal value of Cext:
C sh U max
1 – ----------- -------------- > 0
C ext U lsb
C sh U max
1 > ----------- --------------
C ext U lsb
U max
C ext > C sh ⋅ --------------
U lsb
Choosing a larger Cext decreases more the time between conversions (tC).
max U
An extra large Cext (Cext>> Csh ⋅ -------------
- ) enables sampling more often.
U lsb
However, increasing Cext limits the frequency bandwidth of measurement signal (increasing
the “external” timing constant Rin . Cext).
The formulas below show how to choose the optimal Cext value: signal bandwidth in
correlation with sample time. Signal bandwidth is characterized by an “external” timing
constant, so optimal solution is to charge Cext during tC:
( R in ⋅ C ext ) = t C
C sh U max
( R in ⋅ C ext ) = – ( R in ⋅ C ext ) ⋅ In 1 – ----------- --------------
C ext U lsb
C sh U max
– 1 = In 1 – ----------- --------------
C ext U lsb
–1 C sh U max
e = 1 – ----------- --------------
C ext U lsb
U max
C sh --------------
U lsb U max
C ext = -----------------------
- ≈ 1, 58 ⋅ C sh -------------
-
1–e
–1 U lsb
1 - ≈ (R ⋅ C )
t C ≈ – ( R in ⋅ C ext ) ⋅ In 1 – ------------ in ext
1, 58
Practically the firmware must not program the ADC in continuous mode but only in single
mode and must ensure that there will be a time gap between conversions with duration
equal to tC. This adding of waiting time is the software change which must be applied
together with the hardware change (adding an external capacitor Cext).
Without implementation of tC waiting time in software (for instance, running a conversion just
after the first one) the external capacitor Cext will be cyclically charged from the Csh
capacitor. After a lot of cycles the voltage on Cext will reach a quite high error value (as
previously shown in Figure 42).
A practical example of implementation for STM32L1 ADC is shown below:
U max 4096
C ext = 1, 58 ⋅ C sh -------------- = 1, 58 ⋅ 16pF ⋅ ------------- ≈ 207nF 220nF
U lsb 0.5
S1
Uin
Csh
H = switch on
L = switch off
ai17909b
The switch is controlled by the gate voltages of transistors (inverted signal on PMOS
transistor). This design is a standard bidirectional switch (for rail to rail range of input Uin
voltages). Both transistors have parasitic capacitances between gate and source.
If those capacitances are charged (close to the switch), then their charge can be transferred
to the sampling capacitor (see Figure 44).
Uin S1
Csh
Cext
L → H switching on
ai17910b
This charging and discharging currents (PMOS and NMOS asymmetric capacitances) can
cause charge transfer to sampling capacitor Csh.
Rparasitic
ADC input S1
Csh
ai17911b
5 Conclusion
This application notes describes the main ADC errors and then methods and application
design rules to minimize STM32 microcontroller ADC errors and obtain the best ADC
accuracy.
The choice of method depends on the application requirements and is always a
compromise between speed, precision, enough computation power and design topology.
The published methods lead to a precision improvement and are optimized for the design of
an ADC converter using the SAR (successive approximation register) principle.
6 Revision history
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