EE 411 -VLSI DESIGN

WEEK 1

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 An Overview of VLSI

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 VLSI: Very Large Scale Integration
 Integration: Integrated Circuits
multiple devices on one substrate
 How large is Very Large?
SSI (small scale integration)
7400 series, 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1,000-10,000 transistors
VLSI > 10,000 transistors …HOW MUCH MORE?
IN MODERN CHIPS UPTO 1 BILLION OR MORE!

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 Complexity & Design
sand marketing
CAD
idea engineers &
scientists

VLSI funnel
Design

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 TOP DESIGN LEVEL System Specifications Initial concept
IOs, Goals and Objectives,
Function, Costs
Abstract high-level System design
model VHDL, Verilog and verification
HDL

General Overview of Logic Design

Logic Synthesis
The Design and Verification
Gates plus Registers
Hierarchy
CMOS Design
Circuit Design and Verification
Discrete Logic,
Technology Mapping

Silicon logic Design

BOTTOM DESIGN LEVEL Physical Design and Verification
Transistors sized for power and
speed

Manufacturing Mass Production,

testing and
packaging
5 Finished VLSI chip Marketing
 Abstract Art…..
Abstract art uses a visual language of shape, form,
color and line to create a composition which may exist
with a degree of independence from visual references
in the world.

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 Instruction sets Basic component

Architectural Block Diagram

model RTL &
Behavioral HDL Test instructions

Logical Functionality
A simple design flow description
for a microprocessor
Ports and
Component level connection

Electronic logic Electrical

circuits behavior

Silicon Logic Silicon Behavior

7 Design Complete
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 MOORE’s LAW
Fig 1.6: Devices count by year
Main concept:
 Density of transistors double
every two years. 110M
 Complexity of transistors for
42M
minimum cost double every
Number of transistors

year. 21M
108
9M
5.5M
107 3.1M
1.2M

106 0.25M

105

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1985 1990 1995 2000
11 Year
 Fabrication of CMOS integrated
Circuits

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 An IC consists of several patterned layers of material that
are used to form transistors and provide interconnections
for the circuit

Minimum Feature size currently is lesser than 0.12µm

which allows a packing density of more than 100 million
FETs in a single IC package

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 Silicon Wafer
Silicon ICs are created on large circular sheets called
‘Wafers’

These are 100 to 300mm in diameter and about 0.4 to

0.7mm thick

Wafer Flats: used as a reference for forming the wafer

grids

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 Silicon Wafer Showing Die Sites
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 Additional Flats on a wafer would contain codes that will
keep the information regarding the wafer and its processing

Processing/Manufacturing Capacity is expressed in terms of

Wafer Starts per day/week/Month etc.

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 Fabrication Yield:

*Y= 85% means that 85% of the chips operate as they should and can be sold to
customer

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  Die Area (Adie)= One critically important variable in controlling
yield

 The total number of die sites (NT) on a wafer are given by:

 de=Wasted edge distance

 d=wafer dia
 Adie=Die area

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  Larger the die area, Lesser the yield! Represented by the
following equation:

 Here A= Die Area and D is the Defect Density in cm-2

 D represents the limit on perfection (the average number of
defects per cm2 on wafers)
 For modern processing technologies a D of 1cm-2 is quite a
reasonable value

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 Economics of Silicon wafer processing is a very important aspect.
Profit = Csell – C chip

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 Material Growth and Deposition
ICs are created by stacking layers of materials in a pre-
specified sequence

Both the electrical and material properties of these layers

are important in establishing the characteristics of these
devices formed within an IC

Most layers are created first then patterned using the

lithographic techniques

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 Silicon Dioxide (SiO2)
A critically important material in IC processing

Properties:
 Excellent Electrical Insulator
 Exceptionally good Adhesive properties
 Can easily be grown on the silicon wafer or deposited on
top of it
 Also called ‘Quartz Glass’ or simply ‘Glass’

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 Types of (SiO2):

There are two types of SiO2 layers

Thermal Oxide: Formed by the reaction:

Si + O2 = SiO2

Using Heat as a catalyst

silicon required for the process is obtained from the silicon wafer
itself. thus wafer thickness reduces as a result of this coating
XSi = 0.46XOX

This process is also called Dry Oxidation

The process is also slow, thou high grade oxide is obtained

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 Faster oxide growth rate is obtained by Wet Oxidation process

Here steam and oxygen gas is passed over the Silicon wafer
layer to get the following chemical reaction:

Si + 2 H2O = SiO2 + 2 H2

This chemical reaction would require presence of certain

chemicals like Nitrogen and Chlorine also as catalysts

Thermal oxide is a form of ‘native oxide’ i.e. oxides that are

created when the surface is exposed to oxygenated
atmosphere
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 CVD Oxide Process:

 Increased temperatures raise the rate of thermal oxide growth,

typical temperatures 800 to 1100 OC

 Most oxide layers in VLSI are grown over the surfaces where
no Silicon is available for thermal oxides

 In such cases we create SiO2 molecules using gaseous

reactions and then deposit them onto such surfaces

 This techniques is called CVD (CHEMICAL VAPOR

DEPOSITION) and the resulting oxides are called CVD
Oxides
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 Silicon Nitride (Si3N4)

Properties
Also called Nitride
Excellent Barrier to most atoms
Ideal for Overglass protective layers
Excellent Electrical Isolator
Very high Dielectric constant 7.8
This makes this the most suitable material for Oxide- Nitride ON

30 sandwich exclusively used in DRAM cells