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Hef4093b PDF

This document provides data and specifications for the HEF4093B quadruple 2-input NAND Schmitt trigger gates integrated circuit from Philips Semiconductors. It includes details on device description, pinning, logic diagram, DC and AC characteristics, typical waveforms, and application examples. The HEF4093B consists of four independent Schmitt trigger NAND gates in a single package with hysteresis on both inputs to reduce noise sensitivity.
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0% found this document useful (0 votes)
178 views6 pages

Hef4093b PDF

This document provides data and specifications for the HEF4093B quadruple 2-input NAND Schmitt trigger gates integrated circuit from Philips Semiconductors. It includes details on device description, pinning, logic diagram, DC and AC characteristics, typical waveforms, and application examples. The HEF4093B consists of four independent Schmitt trigger NAND gates in a single package with hysteresis on both inputs to reduce noise sensitivity.
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic


Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

HEF4093B
gates
Quadruple 2-input NAND Schmitt
trigger
Product specification January 1995
File under Integrated Circuits, IC04
Philips Semiconductors Product specification

HEF4093B
Quadruple 2-input NAND Schmitt trigger
gates

DESCRIPTION
The HEF4093B consists of four Schmitt-trigger circuits.
Each circuit functions as a two-input NAND gate with
Schmitt-trigger action on both inputs. The gate switches at
different points for positive and negative-going signals.
The difference between the positive voltage (VP) and the
negative voltage (VN) is defined as hysteresis voltage
(VH).

Fig.2 Pinning diagram.

HEF4093BP(N): 14-lead DIL; plastic


(SOT27-1)
HEF4093BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4093BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America

Fig.3 Logic diagram (one gate).

FAMILY DATA, IDD LIMITS category GATES


See Family Specifications

Fig.1 Functional diagram.

January 1995 2
Philips Semiconductors Product specification

HEF4093B
Quadruple 2-input NAND Schmitt trigger
gates

DC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C

VDD
SYMBOL MIN. TYP. MAX.
V
Hysteresis 5 0,4 0,7 − V
voltage 10 VH 0,6 1,0 − V
15 0,7 1,3 − V
Switching levels 5 1,9 2,9 3,5 V
positive-going 10 VP 3,6 5,2 7 V
input voltage 15 4,7 7,3 11 V
negative-going 5 1,5 2,2 3,1 V
input voltage 10 VN 3 4,2 6,4 V
15 4 6,0 10,3 V

Fig.5 Waveforms showing definition of


VP, VN and VH; where VN and VP are
Fig.4 Transfer characteristic. between limits of 30% and 70%.

January 1995 3
Philips Semiconductors Product specification

HEF4093B
Quadruple 2-input NAND Schmitt trigger
gates

AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns

VDD TYPICAL EXTRAPOLATION


SYMBOL TYP. MAX.
V FORMULA
Propagation delays 5 90 185 ns 63 ns + (0,55 ns/pF) CL
In → On 10 tPHL 40 80 ns 29 ns + (0,23 ns/pF) CL
HIGH to LOW 15 30 60 ns 22 ns + (0,16 ns/pF) CL
5 85 170 ns 58 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 40 80 ns 29 ns + (0,23 ns/pF) CL
15 30 60 ns 22 ns + (0,16 ns/pF) CL
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL
5 60 120 ns 10 ns + (1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL

VDD
TYPICAL FORMULA FOR P (µW)
V
Dynamic power 5 1300 fi + ∑(foCL) × VDD2 where
dissipation per 10 6400 fi + ∑(foCL) × VDD 2 fi = input freq. (MHz)
package (P) 15 18 700 fi + ∑(foCL) × VDD 2 fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)

January 1995 4
Philips Semiconductors Product specification

HEF4093B
Quadruple 2-input NAND Schmitt trigger
gates

Fig.6 Typical drain current as a function of input Fig.7 Typical drain current as a function of input
voltage; VDD = 5 V; Tamb = 25 °C. voltage; VDD =10 V; Tamb = 25 °C.

Fig.8 Typical drain current as a function of input


voltage; VDD = 15 V; Tamb = 25 °C.

January 1995 5
Philips Semiconductors Product specification

HEF4093B
Quadruple 2-input NAND Schmitt trigger
gates

Fig.9 Typical switching levels as a function of supply voltage VDD; Tamb = 25 °C.

APPLICATION INFORMATION
Some examples of applications for the HEF4093B are:
• Wave and pulse shapers
• Astable multivibrators
• Monostable multivibrators.

Fig.11 Schmitt trigger driven via a high impedance


Fig.10 The HEF4093B used as a astable multivibrator. (R > 1 kΩ).

If a Schmitt trigger is driven via a high impedance (R > 1 kΩ) then it is necessary to incorporate a capacitor C of such
value that:
C V DD – V SS
------- > --------------------------
- , otherwise oscillation can occur on the edges of a pulse.
Cp VH

Cp is the external parasitic capacitance between inputs and output; the value depends on the circuit board layout.

Note
The two inputs may be connected together, but this will result in a larger through-current at the moment of switching.

January 1995 6

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