Data Sheet: HEF40098B Buffers
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DATA SHEET
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• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40098B
buffers
3-state hex inverting buffer
Product specification January 1995
File under Integrated Circuits, IC04
Philips Semiconductors Product specification
HEF40098B
3-state hex inverting buffer
buffers
DESCRIPTION
The HEF40098B is a hex inverting buffer with 3-state
outputs. The 3-state outputs are controlled by two enable
inputs (EO4 and EO2). A HIGH on EO4 causes four of the
six buffer elements to assume a high impedance or
OFF-state regardless of the other input conditions and a
HIGH on EO2 causes the outputs of the remaining two
buffer elements to assume a high impedance or OFF-state
regardless of the other input conditions.
Fig.2 Pinning diagram.
HEF40098BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF40098BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40098BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
I1 to I6 buffer inputs
EO4, EO2 enable inputs (active LOW)
O1 to O6 buffer outputs (active LOW)
Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category BUFFERS
See Family Specifications
January 1995 2
Philips Semiconductors Product specification
HEF40098B
3-state hex inverting buffer
buffers
Fig.3 Logic diagram.
DC CHARACTERISTICS
VSS = 0 V
Tamb (°C)
VDD VOH VOL
HEF SYMBOL −40 +25 +85
V V V
MIN. MAX. MIN. MAX. MIN. MAX.
Output current 5 4,6 1,2 1,0 0,8 mA
HIGH 10 9,5 −IOH 3,8 3,2 2,5 mA
15 13,5 12,0 10,0 8,0 mA
HIGH 5 2,5 −IOH 3,8 3,2 2,5 mA
Output current 4,75 0,4 3,5 2,9 2,3 mA
LOW 10 0,5 IOL 12,0 10,0 8,0 mA
15 1,5 24,0 20,0 16,0 mA
Tamb (°C)
VDD VOH VOL
HEC SYMBOL −55 +25 +125
V V V
MIN. MAX. MIN. MAX. MIN. MAX.
Output current 5 4,6 1,25 1,0 0,6 mA
HIGH 10 9,5 −IOH 4,0 3,2 2,1 mA
15 12,5 12,5 10,0 6,7 mA
HIGH 5 2,5 −IOH 4,0 3,2 2,1 mA
Output current 4,75 0,4 3,6 2,9 1,9 mA
LOW 10 0,5 IOL 12,5 10,0 6,7 mA
15 1,5 25,0 20,0 13,0 mA
January 1995 3
Philips Semiconductors Product specification
HEF40098B
3-state hex inverting buffer
buffers
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD TYPICAL EXTRAPOLATION
SYMBOL TYP. MAX.
V FORMULA
Propagation delays
In → On 5 80 160 ns 70 ns + (0,20 ns/pF) CL
HIGH to LOW 10 tPHL 35 70 ns 31 ns + (0,08 ns/pF) CL
15 25 50 ns 22 ns + (0,06 ns/pF) CL
5 65 130 ns 50 ns + (0,30 ns/pF) CL
LOW to HIGH 10 tPLH 30 60 ns 24 ns + (0,13 ns/pF) CL
15 25 50 ns 23 ns + (0,05 ns/pF) CL
Output transition times 5 30 60 ns 15 ns + (0,30 ns/pF) CL
HIGH to LOW 10 tTHL 15 30 ns 10 ns + (0,11 ns/pF) CL
15 10 20 ns 7 ns + (0,07 ns/pF) CL
5 35 70 ns 10 ns + (0,50 ns/pF) CL
LOW to HIGH 10 tTLH 20 40 ns 8 ns + (0,24 ns/pF) CL
15 15 30 ns 6 ns + (0,18 ns/pF) CL
3-state propagation delays
Output disable times
EO2, EO4 → On 5 45 85 ns
HIGH 10 tPHZ 35 65 ns
15 30 60 ns
5 65 135 ns
LOW 10 tPLZ 40 80 ns
15 35 70 ns
Output enable times
EO2, EO4 → On 5 70 140 ns
HIGH 10 tPZH 35 75 ns
15 30 65 ns
5 90 185 ns
LOW 10 tPZL 40 85 ns
15 35 70 ns
VDD
TYPICAL FORMULA FOR P (µW)
V
Dynamic power 5 5 000 fi + ∑ (foCL) × VDD2 where
dissipation per 10 22 800 fi + ∑ (foCL) × VDD2 fi = input freq. (MHz)
package (P) 15 81 000 fi + ∑ (foCL) × VDD2 fo = output freq. (MHz)
CL = load cap. (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995 4
