Hef4081b PDF
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DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4081B
gates
Quadruple 2-input AND gate
Product specification January 1995
File under Integrated Circuits, IC04
Philips Semiconductors Product specification
HEF4081B
Quadruple 2-input AND gate
gates
DESCRIPTION
The HEF4081B provides the positive quadruple 2-input
AND function. The outputs are fully buffered for highest
noise immunity and pattern insensitivity of output
impedance.
Fig.2 Pinning diagram.
HEF4081BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4081BD(F): 14-lead DIL; ceramic (cerdip)
Fig.1 Functional diagram. (SOT73)
HEF4081BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995 2
Philips Semiconductors Product specification
HEF4081B
Quadruple 2-input AND gate
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD TYPICAL EXTRAPOLATION
SYMBOL TYP. MAX.
V FORMULA
Propagation delays
In → On 5 55 110 ns 28 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 25 50 ns 14 ns + (0,23 ns/pF) CL
15 20 40 ns 12 ns + (0,16 ns/pF) CL
5 45 90 ns 18 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 20 40 ns 9 ns + (0,23 ns/pF) CL
15 15 30 ns 7 ns + (0,16 ns/pF) CL
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL
5 60 120 ns 10 ns + (1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL
VDD
TYPICAL FORMULA FOR P (µW)
V
Dynamic power 5 450 fi + ∑ (foCL) × VDD 2 where
dissipation per 10 2 900 fi + ∑ (foCL) × VDD 2 fi = input freq. (MHz)
package (P) 15 11 700 fi + ∑ (foCL) × VDD 2 fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995 3
