RDA5807M

SINGLE-CHIP BROADCAST FM RADIO TUNER Rev.1.8–Aug.2014

1 General Description

The RDA5807M series is the newest generation single-chip

broadcast FM stereo radio tuner with fully integrated
1 GND LOUT 10
synthesizer, IF selectivity, RDS/RBDS and MPX decoder.
The tuner uses the CMOS process, support multi-interface 2 FMIN ROUT 9
and require the least external component. All these make it
3 GND RDA5807M GND 8
very suitable for portable devices.
4 SCLK VDD 7
The RDA5807M series has a powerful low-IF digital audio
processor, this make it have optimum sound quality with 5 SDIO RCLK 6
varying reception conditions.

The RDA5807M series support frequency range is from

50MHz to 115MHz. Figure1-1. RDA5807M Top View

1.1 Features

 CMOS single-chip fully-integrated FM tuner  High cut

 Low power consumption  Programmable de-emphasis (50/75 s)
 Total current consumption lower than 20mA at 3.0V  Receive signal strength indicator (RSSI) and SNR
power supply when under normal situation  Bass boost
 Support worldwide frequency band  Volume control and mute
 50 -115 MHz  Line-level analog output voltage
 Support flexible channel spacing mode  32.768 KHz 12M,24M,13M,26M,19.2M,38.4MHz
 100KHz, 200KHz, 50KHz and 25KHz Reference clock
 Support RDS/RBDS  Only support 2-wire bus interface
 Digital low-IF tuner  Directly support 32Ω resistance loading
 Image-reject down-converter  Integrated LDO regulator
 High performance A/D converter  2.7 to 3.3 V operation voltage
 IF selectivity performed internally  MSOP－10pins
 Fully integrated digital frequency synthesizer
 Fully integrated on-chip RF and IF VCO 1.2 Applications
 Fully integrated on-chip loop filter
 Cellular handsets
 Autonomous search tuning
 MP3, MP4 players
 Support 32.768KHz crystal oscillator
 Portable radios
 Digital auto gain control (AGC)
 PDAs, Notebook
 Digital adaptive noise cancellation
 Mono/stereo switch
 Soft mute
Copyright © RDA Microelectronics Inc. 2006. All rights are reserved.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

Table of Contents

1 General Description .................................................................................................................................... 1

1.1 Features ......................................................................................................................................... 1
1.2 Applications .................................................................................................................................... 1
Table of Contents................................................................................................................................................. 2
2 Functional Description................................................................................................................................ 3
2.1 FM Receiver .................................................................................................................................. 3
2.2 Synthesizer .................................................................................................................................... 3
2.3 Power Supply ................................................................................................................................ 3
2.4 RESET and Control Interface select ............................................................................................. 4
2.5 Control Interface ........................................................................................................................... 4
3 Electrical Characteristics ........................................................................................................................... 5
4 Receiver Characteristics ............................................................................................................................. 6
5 Serial Interface ............................................................................................................................................ 7
5.1 I2C Interface Timing ...................................................................................................................... 7
6 Register Definition ...................................................................................................................................... 8
7 Pins Description......................................................................................................................................... 14
8 Application Diagram................................................................................................................................. 16
8.1 Audio Loading Resistance Larger than 32Ω & Reference Clock Application: ........................... 16
8.1.1 Bill of Materials: ......................................................................................................................... 16
8.2 Audio Loading Resistance Larger than 32Ω & DCXO Application: .......................................... 17
8.2.1 Bill of Materials: ......................................................................................................................... 17
9 Physical Dimension ................................................................................................................................... 18
10 PCB Land Pattern ..................................................................................................................................... 19
Change List ........................................................................................................................................................ 22
11 Notes： ....................................................................................................................................................... 22
12 Contact Information ................................................................................................................................. 23

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

2 Functional Description

LOUT
I I L
PGA ADC DAC
Audio
FMIN DSP
+
Core
LNA
- digital filter
MPX decoder
stereo/mono
audio ROUT
Limiter
Q Q R
PGA ADC DAC

32.768 KHz RDS

VCO
/RBDS
Synthesizer
RCLK
RSSI
SCLK MCU
2.7-3.3 V Interface
VDD Bus
LDO SDIO

Figure 2-1. RDA5807M FM Tuner Block Diagram

2.1 FM Receiver noise.

The DACs convert digital audio signal to analog
The receiver uses a digital low-IF architecture that and change the volume at same time. The DACs
avoids the difficulties associated with direct has low-pass feature and -3dB frequency is about
conversion while delivering lower solution cost 30 KHz.
and reduces complexity, and integrates a low
noise amplifier (LNA) supporting the FM
2.2 Synthesizer
broadcast band (50 to 115MHz), a multi-phase
image-reject mixer array, a programmable gain
control (PGA), a high resolution analog-to-digital The frequency synthesizer generates the local
converters (ADCs), an audio DSP and a high- oscillator signal which divide to multi-phase, then
fidelity digital-to-analog converters (DACs). be used to downconvert the RF input to a
constant low intermediate frequency (IF). The
The limiter prevents overloading and limits the synthesizer reference clock is 32.768 KHz.
amount of intermodulation products created by
strong adjacent channels. The synthesizer frequency is defined by bits
CHAN[9:0] with the range from 50MHz to
The multi-phase mixer array down converts the 115MHz.
LNA output differential RF signal to low-IF, it also
has image-reject function and harmonic tones
rejection.
The PGA amplifies the mixer output IF signal and
then digitized with ADCs.
2.3 Power Supply
The DSP core finishes the channel selection, FM
demodulation, stereo MPX decoder and output The RDA5807M integrated one LDO which
audio signal. The MPX decoder can autonomous supplies power to the chip. The external supply
switch from stereo to mono to limit the output voltage range is 2.7-3.3 V.

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

2.4 RESET and Control Interface select from MCU, and when in read transfer, data bytes
is read out from RDA5807M. There is no visible
register address in I2C interface transfers. The I2C
The RDA5807M is RESET itself When VDD is
interface has a fixed start register address (0x02h
Power up. And also support soft reset by trigger
for write transfer and 0x0Ah for read transfer), and
02H BIT1 from 0 to 1. T he RDA5807M only
an internal incremental address counter. If register
support I2C control interface bus mode.
address meets the end of register file, 0x3Ah,
register address will wrap back to 0x00h. For write
transfer, MCU programs registers from register
0x02h high byte, then register 0x02h low byte,
2.5 Control Interface
then register 0x03h high byte, till the last register.
RDA5807M always gives out ACK after every byte,
The RDA5807M only supports I2C control and MCU gives out STOP condition when register
interface. programming is finished. For read transfer, after
The I2C interface is compliant to I2C Bus command byte from MCU, RDA5807M sends out
Specification 2.1. It includes two pins: SCLK and register 0x0Ah high byte, then register 0x0Ah low
SDIO. A I2C interface transfer begins with START byte, then register 0x0Bh high byte, till receives
condition, a command byte and data bytes, each NACK from MCU. MCU gives out ACK for data
byte has a followed ACK (or NACK) bit, and ends bytes besides last data byte. MCU gives out
with STOP condition. The command byte includes NACK for last data byte, and then RDA5807M will
a 7-bit chip address (0010000b) and a R/W bit. return the bus to MCU, and MCU will give out
The ACK (or NACK) is always sent out by receiver. STOP condition.
When in write transfer, data bytes is written out

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

3 Electrical Characteristics

Table 3-1 DC Electrical Specification (Recommended Operation Conditions):

SYMBOL DESCRIPTION MIN TYP MAX UNIT
VDD Supply Voltage 2.7 3.0 3.3 V
Tamb Ambient Temperature -20 27 +75 ℃
VIL CMOS Low Level Input Voltage 0 0.3*VDD V
VIH CMOS High Level Input Voltage 0.7*VDD VDD V
VTH CMOS Threshold Voltage 0.5*VDD V

Table 3-2 DC Electrical Specification (Absolute Maximum Ratings):

SYMBOL DESCRIPTION MIN TYP MAX UNIT
Tamb Ambient Temperature -40 +90 °C
(1)
IIN Input Current -10 +10 mA
(1)
VIN Input Voltage -0.3 VDD+0.3 V
Vlna FM Input Level +10 dBm
Notes:
1. For Pin: SCLK, SDIO

Table 3-3 Power Consumption Specification

(VDD = 3 V, TA = 25℃, unless otherwise specified)

SYMBOL DESCRIPTION CONDITION TYP UNIT

(1)
IVDD Supply Current ENABLE=1 20 mA
(2)
IVDD Supply Current ENABLE=1 21 mA
IPD Powerdown Current ENABLE=0 15 A
Notes:
1. For strong input signal condition
2. For weak input signal condition

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

4 Receiver Characteristics

Table 4-1 Receiver Characteristics

(VDD = 3 V, TA = 25 °C, unless otherwise specified)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

General specifications
Fin FM Input Frequency Range Adjust BAND Register 50 115 MHz
50MHz - 1.4 1.8
65MHz - 1.2 1.5

1,2,3
88MHz - 1.2 1.5
Vrf Sensitivity S/N=26dB V EMF
98MHz - 1.3 1.5
108MHz - 1.3 1.5
115MHz - 1.3 1.8
4
IP3in Input IP3 80 - - dBV
1,2
αam AM Suppression m=0.3 60 - - dB
S200 Adjacent Channel Selectivity ±200KHz 50 70 - dB
S400 400KHz Selectivity ±400KHz 60 85 - dB
1,2
Audio L/R Output Voltage
VAFL; VAFR Volume [3:0] =1111 - 360 - mV
(Pins LOUT and ROUT)
2
Maximum Signal to Noise Mono 55 57 -
S/N 1,2,3,5 6
dB
Ratio Stereo 53 55 -
αSCS Stereo Channel Separation 35 - - dB
Audio Output Loading
RL Single-ended 32 - - Ω
Resistance
Audio Total Harmonic Volume[3:0] Rload=1KΩ - 0.15 0.2
THD 1,3,6 %
Distortion =1111 Rload=32Ω - 0.2 -
Audio Output L/R
αAOI - - 0.05 dB
Imbalance1,6
Rmute Mute Attenuation Ratio1 Volume[3:0]=0000 60 - - dB
9
1KHz=0dB Low Freq - 100 -
BWaudio Audio Response1 Hz
±3dB point High Freq - 14 -
Pins FMIN, LOUT, ROUT
Pins FMIN Input Common
Vcom_rfin 0 V
Mode Voltage
Audio Output Common Mode
Vcom 1.0 1.05 1.1 V
Voltage8
Notes:1. Fin=65 to 115MHz; Fmod=1KHz; de-emphasis=75s; MONO=1; L=R unless noted otherwise;
2. f=22.5KHz; 3. BAF = 300Hz to 15KHz, RBW <=10Hz; 4. |f2-f1|>1MHz, f0=2xf1-f2, AGC disable, Fin=76 to 108MHz;
5. PRF=60dBUV; 6. f=75KHz,fpilot=10% 7. Measured at VEMF = 1 m V, f RF = 65 to 108MHz
8. At LOUT and ROUT pins 9. Adjustable

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

5 Serial Interface

5.1 I2C Interface Timing

Table 5-1 I2C Interface Timing Characteristics

(VDD = 3 V, TA = 25 °C, unless otherwise specified)

PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT

SCLK Frequency fscl 0 - 400 KHz
SCLK High Time thigh 0.6 - - s
SCLK Low Time tlow 1.3 - - s
Setup Time for START Condition tsu:sta 0.6 - - s
Hold Time for START Condition thd:sta 0.6 - - s
Setup Time for STOP Condition tsu:sto 0.6 - - s
SDIO Input to SCLK↑ Setup tsu:dat 100 - - ns
SDIO Input to SCLK↓ Hold thd:dat 0 - 900 ns
STOP to START Time tbuf 1.3 - - s
SDIO Output Fall Time tf:out 20+0.1Cb - 250 ns
SDIO Input, SCLK Rise/Fall Time tr:in / tf:in 20+0.1Cb - 300 ns
Input Spike Suppression tsp - - 50 ns
SCLK, SDIO Capacitive Loading Cb - - 50 pF
Digital Input Pin Capacitance 5 pF

tsu:sta thd:sta tsu:dat thd:dat tsp tsu:sto tbuf

SDIO

SCLK 1-7 8 9 1-7 8

9
1-7 8 9

START address r/w ACK data high byte ACK data low byte ACK STOP START

Figure 5-1. I2C Interface Write Timing Diagram

tsu:sta thd:sta tsu:dat thd:dat tsp tsu:sto tbuf

SDIO

SCLK 1-7 8 9 1-7 8

9
1-7 8 9

START address r/w ACK data high byte ACK data low byte NACK STOP START

Figure 5-2. I2C Interface Read Timing Diagram

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

6 Register Definition

REG BITS NAME FUNCTION DEFAULT

00H 15:0 CHIPID[7:0] Chip ID. 0x5804
02H 15 DHIZ Audio Output High-Z Disable. 0
0 = High impedance; 1 = Normal operation
14 DMUTE Mute Disable. 0
0 = Mute; 1 = Normal operation
13 MONO Mono Select. 0
0 = Stereo; 1 = Force mono
12 BASS Bass Boost. 0
0 = Disabled; 1 = Bass boost enabled
11 RCLK NON-CALIBRATE 0=RCLK clock is always supply 0
MODE 1=RCLK clock is not always supply when FM
work ( when 1, RDA5807M can’t directly
support -20 ℃ ~70 ℃ temperature. Only
suppory ±20℃ temperature swing from tune
point)

10 RCLK DIRECT INPUT MODE 1=RCLK clock use the directly input mode 0
9 SEEKUP Seek Up. 0
0 = Seek down; 1 = Seek up
8 SEEK Seek. 0
0 = Disable stop seek; 1 = Enable
Seek begins in the direction specified by
SEEKUP and ends when a channel is found,
or the entire band has been searched.
The SEEK bit is set low and the STC bit is set
high when the seek operation completes.
7 SKMODE Seek Mode 0
0 = wrap at the upper or lower band limit and
continue seeking
1 = stop seeking at the upper or lower band
limit
6:4 CLK_MODE[2:0] 000=32.768kHz 000
001=12Mhz
101=24Mhz
010=13Mhz
110=26Mhz
011=19.2Mhz
111=38.4Mhz

3 RDS_EN RDS/RBDS enable 0

If 1, rds/rbds enable

2 NEW_METHOD New Demodulate Method Enable, can improve 0

the receive sensitivity about 1dB.

1 SOFT_RESET Soft reset. 0

If 0, not reset;

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

REG BITS NAME FUNCTION DEFAULT

If 1, reset.

0 ENABLE Power Up Enable. 0

0 = Disabled; 1 = Enabled
03H 15:6 CHAN[9:0] Channel Select. 0x13f
BAND = 0
Frequency =
Channel Spacing (kHz) x CHAN+ 87.0 MHz
BAND = 1or 2
Frequency =
Channel Spacing (kHz) x CHAN + 76.0 MHz
BAND = 3
Frequency =
Channel Spacing (kHz) x CHAN + 65.0 MHz
CHAN is updated after a seek operation.
5 DIRECT MODE Directly Control Mode, Only used when test. 0
4 TUNE Tune 0
0 = Disable
1 = Enable
The tune operation begins when the TUNE bit
is set high. The STC bit is set high when the
tune operation completes.
The tune bit is reset to low automatically when
the tune operation completes..
3:2 BAND[1:0] Band Select. 00
00 = 87–108 MHz (US/Europe)
01 = 76–91 MHz (Japan)
10 = 76–108 MHz (world wide)
1
11 = 65 –76 MHz （East Europe） or 50-65MHz
1:0 SPACE[1:0] Channel Spacing. 00
00 = 100 kHz
01 = 200 kHz
10 = 50kHz
11 = 25KHz
04H 15 RSVD Reserved 0
14 STCIEN Seek/Tune Complete Interrupt Enable. 0
0 = Disable Interrupt
1 = Enable Interrupt
Setting STCIEN = 1 will generate a low
pulse on GPIO2 when the interrupt
occurs.
13 RBDS 1 = RBDS mode enable 0
0 = RDS mode only
12 RDS_FIFO_EN 1 = RDS fifo mode enable. 0
11 DE De-emphasis. 0
0 = 75 µs; 1 = 50 µs

1
If 0x07h_bit<9> ( band )=1, 65-76MHz; =0, 50-76MHz
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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

REG BITS NAME FUNCTION DEFAULT

10 RDS_FIFO_CLR 1 = clear RDS fifo 1
9 SOFTMUTE_EN If 1, softmute enable 0
8 AFCD AFC disable. 0
If 0, afc work;
If 1, afc disabled.

7 rsvd Read as 0. 0
6 I2S_ENABLE I2S enable. 0
0 = disabled;
1 = enabled.
5:4 GPIO3[1:0] General Purpose I/O 3.when 00
gpio_sel=00or11
00 = High impedance
01 = Mono/Stereo indicator (ST)
10 = Low
11 = High
3:2 GPIO2[1:0] General Purpose I/O 2. when gpio_sel=10 00
00 = High impedance
01 = Interrupt (INT)
10 = Low
11 = High
1:0 GPIO1[1:0] General Purpose I/O 1. when gpio_sel=01 00
00 = High impedance
01 = Reserved
10 = Low
11 = High
05H 15 INT _MODE If 0, generate 5ms interrupt; 1
If 1, interrupt last until read reg0CH action
occurs.

14:13 Seek_mode Default value is 00; When = 10, will add the 00
RSSI seek mode.

12 RSVD
2
11:8 SEEKTH[3:0] Seek SNR threshold value 1000

7:6 LNA_PORT_SEL[1:0] LNA input port selection bit: 10

00: no input
01: LNAN
10: LNAP
11: dual port input

5:4 LNA_ICSEL_BIT[1:0] Lna working current bit: 00

00=1.8mA
01=2.1mA
10=2.5mA
11=3.0mA

3:0 VOLUME[3:0] DAC Gain Control Bits (Volume). 1011

0000=min; 1111=max

2
The default noise threshold is 71dB
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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

REG BITS NAME FUNCTION DEFAULT

Volume scale is logarithmic
When 0000, output mute and output
impedance is very large
06H 15 RSVD reserved 0

14:13 OPEN_MODE[1:0] Open reserved register mode. 00

11=open behind registers writing function
others: only open behind registers reading
function
12 slave_master I2S slave or master. 0
1 = slave;
0 = master.
11 ws_lr Ws relation to l/r channel. 0
If 0, ws=0 ->r, ws=1 ->l;
If 1, ws=0 ->l, ws=1 ->r.
10 sclk_i_edge If 0, use normal sclk internally; 0
If 1, inverte sclk internally.
9 data_signed If 0, I2S output unsigned 16-bit audio 0
data.
If 1, I2S output signed 16-bit audio data.
8 WS_I_EDGE If 0, use normal ws internally; 0
If 1, inverte ws internally.
4'b1000: WS_STEP_48;
7:4 I2S_SW_CNT[4:0]
4'b0111: WS_STEP=44.1kbps;
0
Only valid 4'b0110: WS_STEP=32kbps;
4'b0101: WS_STEP=24kbps;
in master mode 4'b0100: WS_STEP=22.05kbps;
4'b0011: WS_STEP=16kbps;
4'b0010: WS_STEP=12kbps;
4'b0001: WS_STEP=11.025kbps;
4'b0000: WS_STEP=8kbps;
3 SW_O_EDGE If 1, invert ws output when as master. 0
2 SCLK_O_EDGE If 1, invert sclk output when as master. 0
1 L_DELY If 1, L channel data delay 1T. 0
0 R_DELY If 1, R channel data delay 1T. 0
07H 15 RSVD Reserved 0

14:10 TH_SOFRBLEND[5:0] Threshold for noise soft blend setting, unit 10000
2dB

9 65M_50M MODE Valid when band[1:0] = 2’b11 (0x03H_bit<3:2>) 1

1 = 65~76 MHz;
0 = 50~76 MHz.

8 RSVD Reserved 0

7:2 SEEK_TH_OLD Seek threshold for old seek mode, Valid when 000000
Seek_Mode=10

1 SOFTBLEND_EN If 1, Softblend enable 1

0 FREQ_MODE If 1, then freq setting changed. 0

Freq = 76000(or 87000) kHz + freq_direct (08H)
kHz.

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

REG BITS NAME FUNCTION DEFAULT

08H 15:0 freq_direct[15:0] Valid when freq_mode = 1. 0x0

0AH 15 RDSR RDS ready 0

0 = No RDS/RBDS group ready(default)
1 = New RDS/RBDS group ready

14 STC Seek/Tune Complete. 0

0 = Not complete
1 = Complete
The seek/tune complete flag is set when the
seek or tune operation completes.
13 SF Seek Fail. 0
0 = Seek successful; 1 = Seek failure
The seek fail flag is set when the seek
operation fails to find a channel with an RSSI
level greater than SEEKTH[3:0].
12 RDSS RDS Synchronization 0
0 = RDS decoder not synchronized(default)
1 = RDS decoder synchronized
Available only in RDS Verbose mode

11 BLK_E When RDS enable: 0

1 = Block E has been found
0 = no Block E has been found
10 ST Stereo Indicator. 1
0 = Mono; 1 = Stereo
9:0 READCHAN[9:0] Read Channel. 8’h00
BAND = 0
Frequency = Channel Spacing (kHz) x
READCHAN[9:0]+ 87.0 MHz
BAND = 1 or 2
Frequency = Channel Spacing (kHz) x
READCHAN[9:0]+ 76.0 MHz
BAND = 3
Frequency = Channel Spacing (kHz) x
READCHAN[9:0]+ 65.0 MHz
READCHAN[9:0] is updated after a tune or
seek operation.
0BH 15:9 RSSI[6:0] RSSI. 0
0000000 = min
1111111 = max
RSSI scale is logarithmic.

8 FM TRUE 1 = the current channel is a station 0

0 = the current channel is not a station

7 FM_READY 1=ready 0
0=not ready

<6:5> reserved 0
<4> ABCD_E 1= the block id of register 0cH,0dH,0eH,0fH is E
0= the block id of register 0cH, 0dH, 0eH,0fH is
A, B, C, D

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

REG BITS NAME FUNCTION DEFAULT

<3:2> BLERA[1:0] Block Errors Level of RDS_DATA_0, and is
always read as Errors Level of RDS BLOCK A
(in RDS mode) or BLOCK E (in RBDS mode
when ABCD_E flag is 1)
00= 0 errors requiring correction
01= 1~2 errors requiring correction
10= 3~5 errors requiring correction
11= 6+ errors or error in checkword, correction
not possible.
Available only in RDS Verbose mode

<1:0> BLERB[1:0] Block Errors Level of RDS_DATA_1, and is

always read as Errors Level of RDS BLOCK B
(in RDS mode ) or E (in RBDS mode when
ABCD_E flag is 1).
00= 0 errors requiring correction
01= 1~2 errors requiring correction
10= 3~5 errors requiring correction
11= 6+ errors or error in checkword, correction
not possible.
Available only in RDS Verbose mode

0CH <15:0> RDSA[15:0] BLOCK A ( in RDS mode) or BLOCK E (in 16’h5803

RBDS mode when ABCD_E flag is 1)

0DH <15:0> RDSB[15:0] BLOCK B ( in RDS mode) or BLOCK E (in 16’h5804

RBDS mode when ABCD_E flag is 1)

0EH <15:0> RDSC[15:0] BLOCK C ( in RDS mode) or BLOCK E (in 16’h5808

RBDS mode when ABCD_E flag is 1)

0FH <15:0> RDSD[15:0] BLOCK D ( in RDS mode) or BLOCK E (in 16’h5804

RBDS mode when ABCD_E flag is 1)

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

7 Pins Description

Figure 7-1. RDA5807M Top View

Table 7-1 RDA5807M Pins Description

SYMBOL PIN DESCRIPTION
Ground. Connect to ground plane
GND 1,3,8
on PCB
FMIN 2 FM single input
32.768KHz crystal oscillator and
RCLK 6
reference clock input
Data input/output for serial control
SDIO 5
bus
SCLK 4 Clock input for serial control bus
VDD 7 Power supply
ROUT,LOUT 9,10 Right/Left audio output

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

Table 7-2 Internal Pin Configuration

SYMBOL PIN DESCRIPTION

FMs

FMIN 2 FMIN
MN1

50pF

RCLK 6

47K

SDIO\SCLK Sin

SDIO /SCLK 5/4

Sout
MN1

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

8 Application Diagram

8.1 Audio Loading Resistance Larger than 32Ω & Reference Clock Application:

Notes:
1. J1: Common 32Ω Resistance
Headphone;
2. U1: RDA5807M Chip;
3. V1: Power Supply (2.7~3.3V);
4. FM Choke (L1 and C1) for Audio
Common and LNA Input
Common;
5. Place C2 Close to 5807M pin7.

Figure 8-1. RDA5807M FM Tuner Application Diagram (Reference Clock Application)

8.1.1 Bill of Materials:

COMPONENT VALUE DESCRIPTION SUPPLIER

U1 RDA5807M Broadcast FM Radio Tuner RDA

J1 Common 32Ω Resistance Headphone
L1,L2,L3 100nH LC Chock for FMIN Input Murata
C1,C3,C4 24pF Capacitor Murata
C6,C7 4.7µF Audio AC Couple Capacitors Murata
C5 22nF Power Supply Bypass Capacitor Murata
C2 100pF AC Couple Capacitors Murata
F1/F2 1.8K@100MHz FM Band Ferrite Murata
2
R1,R2 10KΩ I C Bus Pull-up Resister Murata

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

8.2 Audio Loading Resistance Larger than 32Ω & DCXO Application:

Notes:
1. J1: Common 32Ω Resistance
Headphone;
2. U1: RDA5807M Chip;
3. V1: Power Supply (2.7~3.3V);
4. FM Choke (L1 and C1) for
Audio Common and LNA Input
Common;
5. Place C2 Close to 5807M pin7.

Figure 8-2. RDA5807M FM Tuner Application Diagram (32.768K crystal)

8.2.1 Bill of Materials:

COMPONENT VALUE DESCRIPTION SUPPLIER

U1 RDA5807M Broadcast FM Radio Tuner RDA

J1 Common 32Ω Resistance Headphone
L1,L2,L3 100nH LC Chock for FMIN Input Murata
C1,C3,C4 24pF Capacitor Murata
C6,C7 4.7µF Audio AC Couple Capacitors Murata
C5 22nF Power Supply Bypass Capacitor Murata
C2 100pF AC Couple Capacitors Murata
F1/F2 1.8K@100MHz FM Band Ferrite Murata
2
R1,R2 10KΩ I C Bus Pull-up Resister Murata

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

9 Physical Dimension

Figure 9-1 illustrates the package details for the RDA5807M. The package is lead-free and
RoHS-compliant.

Figure 9-1. 10-Pin MSOP

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

10 PCB Land Pattern

Figure 10-1.Classification Reflow Profile

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly

Average Ramp-Up Rate 3 oC/second max. 3 oC/second max.

(TSmax to Tp)

Preheat
-Temperature Min (Tsmin) 100 oC 150 oC
-Temperature Max (Tsmax) 100 oC 200 oC
-Time (tsmin to tsmax) 60-120 seconds 60-180 seconds

Time maintained above:

-Temperature (TL) 183 oC 217oC
-Time (tL) 60-150seconds 60-150 seconds

Peak /Classification See Table-II See Table-III

Temperature(Tp)

Time within 5 oC of actual 10-30 seconds 20-40 seconds

Peak Temperature (tp)

Ramp-Down Rate 6 oC/second max. 6 oC/seconds max.

Time 25 oC to Peak 6 minutes max. 8 minutes max.

Temperature

Table-I Classification Reflow Profiles

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

Package Thickness Volume mm3 Volume mm3

<350 ≥350

＜2.5mm 240 + 0/-5 o C 225 + 0/-5 o C

≥2.5mm 225 + 0/-5 o C 225 + 0/-5 o C

Table – II SnPb Eutectic Process – Package Peak Reflow Temperatures

Package Volume mm3 Volume mm3 Volume mm3

Thickness ＜350 350-2000 ＞2000

＜1.6mm 260 + 0 o C * 260 + 0 o C * 260 + 0 o C *

1.6mm – 2.5mm 260 + 0 o C * 250 + 0 o C * 245 + 0 o C *

≥2.5mm 250 + 0 o C * 245 + 0 o C * 245 + 0 o C *

*Tolerance : The device manufacturer/supplier shall assure process compatibility up to and

including the stated classification temperature(this mean Peak reflow temperature + 0 o C. For
example 260+ 0 o C ) at the rated MSL Level.

Table – III Pb-free Process – Package Classification Reflow Temperatures

Note 1: All temperature refer topside of the package. Measured on the package body surface.
o o
Note 2: The profiling tolerance is + 0 C, - X C (based on machine variation
capability)whatever
is required to control the profile process but at no time will it exceed - 5 o C. The
producer assures process compatibility at the peak reflow profile temperatures defined
in Table –III.
Note 3: Package volume excludes external terminals(balls, bumps, lands, leads) and/or non
integral heat sinks.
Note 4: The maximum component temperature reached during reflow depends on package the
thickness and volume. The use of convection reflow processes reduces the thermal
gradients between packages. However, thermal gradients due to differences in
thermal mass of SMD package may sill exist.
Note 5: Components intended for use in a “lead-free” assembly process shall be evaluated
using the “lead free” classification temperatures and profiles defined in Table-I II III
whether or not lead free.

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

RoHS Compliant
The product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated
biphenyls (PBB) or polybrominated diphenyl ethers (PBDE), and are therefore considered RoHS
compliant.

ESD Sensitivity
Integrated circuits are ESD sensitive and can be damaged by static electricity. Proper
ESD techniques should be used when handling these devices.

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part without prior written permission of RDA. Page 21 of 23
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

Change List

REV DATE AUTHER CHANGE DESCRIPTION

V1.0 2011-05-23 Chun Zhao Original Draft.

11 Notes：

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RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE

12 Contact Information

RDA Microelectronics (Shanghai), Inc.

Suite 1108 Block A, e-Wing Center, 113 Zhichun Road Haidian District, Beijing
Tel: 86-10-62635360
Fax: 86-10-82612663
Postal Code: 100086

Suite 302 Building 2, 690 Bibo Road Pudong District, Shanghai

Tel: 86-21-50271108
Fax: 86-21-50271099
Postal Code: 201203

Copyright © RDA Microelectronics Inc. 2006. All rights are reserved.

Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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