Power Management Ics For Handheld Device: General Description Features
Power Management Ics For Handheld Device: General Description Features
Power Management Ics For Handheld Device: General Description Features
integrated linear charger for a single cell Lithium Ion battery, Dynamic Path.
five LDO linear regulators and two high efficiency buck ` PWR_IN LDO Support Continuous 1.5A, Peak 2A
well as power on timing control for complete flexibility. 18V Input Voltage
` Switch Well for LDO and Charger Power MOSFET
The linear charger integrates LDO, MOSFET pass element,
` Set Charge Current by ISETA Pin
and thermal-regulation circuitry. The proprietary thermal-
` Charge Status Indicator
regulation circuitry limits the die temperature when fast
` Interrupt for PWR_IN Plug In/Out, Time Out and
charging or while exposed to high ambient temperatures,
Charger Done.
allowing maximum charging current without damaging the
` Battery Temperature Monitoring
IC.
z Hysteretic Buck
The two step-down converters are optimized for small size ` Buck 1 for Memory, Adjustable Voltage and 600mA
inductor and high efficiency applications. They utilize a Output Current
proprietary hysteretic PWM control scheme that switches ` Buck 2 for Core voltage with 25mV/step I C
2
with nearly fixed frequency and is adjustable, allowing the Adjustable, 600mA Output Current
customer to trade some efficiency for smaller external ` Max. Efficiency Up to 90%
component, as desired. The output current is guaranteed z LDO
up to 600mA, while quiescent current is a low 40μA (typ). ` LDO1 : 3.3V/500mA for I/O, Default ON
The LDO linear regulators provide high power supply ` LDO2 : 1.2V/80mA for PLL, Default ON
rejection rate and have only 45uVRMS of output noises for ` LDO3 : 1.2V/80mA for VDD Alive.
100Hz to 10kHz frequency range to power noise sensitive ` LDO4 : 2.5V/50mA, Default OFF
PWR_HOLD
PWR_ON
HP_PWR
PWR_IN
PWR_IN
PWR_ID
ISETU
VSYS
VSYS
CLK
40 39 38 37 36 35 34 33 32 31
nCHG_S 1 30 DATA
ISETA 2 29 BATT
TS 3 28 BATT
TIMER 4 27 FB1
VOUT2 5 26 PGND1
GND
VIN3 6 25 LX1
VOUT3 7 24 VIN1
VOUT1 8 23 LX2
41
VIN2 9 22 PGND2
VOUT4 10 21 FB2
11 12 13 14 15 16 17 18 19 20
nPBSTAS
VOUT5
nRESET
nINT
nLBO
LBI
GND
S2
S1
PWR_EN
WQFN-40L 5x5
VIN1
Control SW
Circuit
LX1
ISETU Buck1
PGND1
ISETA
TS Li-lon Linear Charger UVLO FB1
TIMER Control nRESET
nCHG_S Thermal Reset
Shutdown
nPBSTAS
LX2
320ms Buck2
PWR_ON
2µA Debounce PGND2
FB2
PWR_EN
320ms ON/OFF VIN3
HP_PWR Debounce 2
2µA Control & I C LDO1 VOUT1
BUCK1 OK Interface
LDO2 VOUT2
To be continued
DS9945-01 April 2011 www.richtek.com
11
RT9945
Parameter Symbol Conditions Min Typ Max Unit
Protection
Thermal Regulation -- 125 -- °C
TS Pin Source Current V TS = 1.5V 94 100 106 μA
TS Pin Low Threshold
2.45 2.5 2.55 V
Voltage
TS Pin High Threshold
0.485 0.5 0.515 V
Voltage
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of
JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Efficiency (%)
60 VBATT = 4.2V 60 VBATT = 3.7V
VBATT = 4.2V
50 50
40 40
30 30
20 20
10 10
VBuck1 = 1.8V VBuck2 = 1.35V
0 0
0.001 0.01 0.1 1 0.001 0.01 0.1 1
Output Current (A) Output Current (A)
Buck1 Output Voltage vs. Output Current Buck2 Output Voltage vs. Output Current
1.82 1.38
VBuck1 = 1.8V VBuck2 = 1.35V
1.81 1.37
Output Voltage (V)
1.8 1.36
1.79 1.35
VBATT = 4V VBATT = 4V
VBATT = 3.6V VBATT = 3.6V
1.78 1.34
1.77 1.33
1.76 1.32
1.75 1.31
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Output Current (A) Output Current (A)
VBuck1 PWR_EN
(2V/Div) (1V/Div)
VLDO1 VBuck2
(2V/Div) (1V/Div)
VLDO3 VLDO2
(2V/Div) (1V/Div)
CLK
PWR_EN (5V/Div)
(2V/Div)
DATA
(5V/Div)
nRESET LDO4
(5V/Div) (2V/Div)
LDO5
(2V/Div)
CLK PWR_EN
(5V/Div) (1V/Div)
DATA VBuck2
(5V/Div)
(1V/Div)
LDO4
(5V/Div) VLDO2
(1V/Div)
LDO5
(5V/Div)
VLX1 VLX2
(2V/Div) (2V/Div)
VBuck1 VBuck2
(20mV/Div) (20mV/Div)
ILX1 ILX2
(500mA/Div) (500mA/Div)
VBuck1 VBuck2
(50mV/Div) (50mV/Div)
I Buck1 I Buck2
(200mA/Div) (200mA/Div)
2.0 VLDO1
(50mV/Div)
Frequency (MHz)
1.5 Buck2
1.0
0.5
I LDO1
(200mA/Div)
IOUT = 200mA
0.0
3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 Time (100μs/Div)
Input Voltage (V)
LDO1 Output Voltage vs. Output Current LDO1 Dropout Voltage vs. Temperature
3.36 140
VBATT = 3.8V
3.34 120
Dropout Voltage (mV)
3.32
Output Voltage (V)
100
3.30
80
3.28
60
3.26
40
3.24
3.22 20
IOUT1 = 200mA
3.20 0
0 0.1 0.2 0.3 0.4 0.5 -40 -15 10 35 60 85
Output Current (A) Temperature (°C)
-40
PWRIN = 4.5V
-50 600
LDO5
-60
400
-70
LDO1
-80
200
-90
-100 0
100 1k
1,000 10k
10,000 100k
100,000 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Frequency (Hz) VBATT (V)
800
I PWRIN IPWRIN
(2A/Div) VSYS
VBATT
600 (2V/Div) VPWRIN
V SYS
400 (2V/Div)
I SYS
(2A/Div) ISYS
200
V PWRIN
(2V/Div) VPWRIN = 5V, VBATT = 4V, PWRID = L, ISYS = 0 to 2.4A
0
0 2.5 5 7.5 10 12.5 15 Time (1ms/Div)
RISETA (kΩ)
(k⎠ )
IBATT IBATT
(2A/Div)
IPWRIN
I PWRIN
(2A/Div) VBATT
VSYS
VBATT
(2V/Div)
V SYS VPWRIN
(2V/Div)
V PWRIN
(2V/Div) VPWRIN = 5V, VBATT = 3.8V, PWRID = L
Time (250ms/Div)
The device that Acknowledges must pull down the DATA TYPE I : Send the address and one command by I2C (Figure
line during the acknowledge clock pulse, so that the DATA 3).
SCL
VSYS
Processor RT9945
SCL
SDA
SDO
Master
Slave
0 0 0 1 1 0.5375
0 0 1 0 0 0.55 Z51 Z50 LDO5 Output Voltage (V)
0 0 1.2
0 0 1 0 1 0.5625
0 1 1.5
0 0 1 1 0 0.575
1 0 3.0
0 0 1 1 1 0.5875 1 1 3.3 (Default)
0 1 0 0 0 0.6
2
0 1 0 0 1 0.6125 TYPE II : Send address and two commands by I C
0 1 0 1 0 0.625 (Figure 4).
0 1 0 1 1 0.6375
0 1 1 0 0 0.65
0 1 1 0 1 0.6625
0 1 1 1 0 0.675 (Default)
0 1 1 1 1 0.6875
1 X[1] X X X 0.7
Note 1 : “X” means don’t care
Table 2. The Default Status of Interrupt Registers for I2C Reading (No PWR_IN)
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Name PWR_IN PWR_OUT PWR_ID Reserved Time Out CHG_DONE Reserved
Default 0 1 0 1 0 0 0 0
Power Sequence
If the PWR_IN and VSYS pin voltages are below the internal UVLO threshold, all IC blocks are disabled and the RT9945
is not operational. When an external power source or battery with voltage greater than the VULO voltage threshold is
applied to VSYS pins, the internal RT9945 references are powered up and biasing internal circuits. When all the main
internal supply rails are active, the RT9945 I2C registers are set to the power-up default values.
CLK 2
I C 2
I C
DATA Decoder Registers
and Non-
nINT Interrupt Volatile
VMEM VSYS Controller Memory
Host
Processor
nPBSTAS
nRESET VSYS
PWR_HOLD Sequencing System and
& Operating Battery PWR_IN
PWR_EN
Mode Charger
HP_PWR Control Logic BATT
Setting
PWR_ON
VSYS
If a power good fault is not present at the end of the power good check mode and then NORMAL mode starts. In this mode
of operation, the I2C registers define the RT9945 operation, and must be able to handle all issues regarding power on/off
the handheld device. The following pins and battery voltages determine the power on/off status of the handset :
PWR_ON
PWR_HOLD
Logic high on PWR_ON pin is the normal way of powering up a handset. The PWR_ON signal is held high for at least 320
ms; Buck1, 2 and LDO1, 3 are turned on; when Buck2 reaches 87% of its final value, a 200ms reset timer is started at
after which nRESET is asserted high, and then the handheld device processor is initialized and will assert PWR_HOLD
high to maintain power on. This wrap around constitutes the PWR_ON button can be released (return to low state) and the
power remains on. If, however, PWR_ON is released before the PWR_HOLD signal is asserted, then Buck1, 2 and LDO1,
3 will be turned off. All output could be turned off by the processor asserting PWR_HOLD low, if PWR_ON = Low.
The RT9945's default power output voltages for Samsung platform are listed in Table 4 as following :
Sleep Mode
The external host can set the RT9945 in sleep mode using the GPIO configuration. In the sleep mode, change the
PWR_EN signal to set different output on/off status :
1. Buck2 and LDO2 will be disabled when the PWR_EN is turned off to enter the sleep mode.
2. When the PWR_EN is turned on, the Buck2 and LDO2 are enabled and the reset signal from the RT9945 remains high.
PWR_ON
320ms
VDD_MEM
BUCK1
VDD_IO
LDO1 100µs
VDD_alive
LDO3 100µs
PWR_EN BUCK2 PG
VDD_CORE
BUCK2
VDD_PLL
LDO2
LDO4
LDO5
PWR_HOLD
2
I C : LDO4/5_EN
nRESET 200ms
If this internal interrupt event is set without mask, the interrupt controller will set nINT to low if any interrupt behavior
happened. Then processor will be acknowledged by nINT and then read register status by I2C interface. PMU will accept
this READ OK status and let the nINT return to high (Figure 8).
Interrupt Mask = 0
CLK
DATA
nINT READ OK
If this internal interrupt register is set with mask, the interrupt controller will not set nINT to low even external real interrupt
event happened (Figure 9).
Interrupt Event
Interrupt Mask = 1
SET MASK = 0
CLK
DATA
READ OK
nINT
PWR_ON
nPBSTAS
Buck1
LDO1
LDO3 Buck2 power good
320ms
nRESET
200ms
PWR_HOLD
VSYS
CIN
Zero-Current ZC
Logic L
Detection LX
+ VOUT
Buffer
Current Limit OC R1 CFF
R2 COUT
-
+
PGND
VREF FB
Reference
( )
VOUT = R1 + 1 × VFB1
R2
Where VFB1 is the feedback reference voltage (0.6V typ.)
Below table is the default value of resistor and CFF for different output voltages.
VBuck (V) R1 (k) R2 (k) CFF (pF)
1.2 100 100 220
1.8 200 100 120
2.5 316 100 120
Inductor Selection
The RT9945 step-down converters operate with inductors of 1μH to 4.7μH. Low inductance values are physically smaller
but require faster switching, which results in some efficiency loss. The inductor's DC current rating only needs to match
the maximum load current of the application because the RT9945 step-down converters feature zero current overshoot
during startup and load transients. The recommended inductor is 2.2μH. For optimum voltage positioning load transients,
choose an inductor with DC series resistance in the 50mΩ to 150mΩ range. For higher efficiency at heavy loads (above
200mA) or minimal load regulation (but some transient overshoot), the resistance should be kept below 100mΩ. For light
load applications up to 200mA, much higher resistance is acceptable with very little impact on performance.
CFF = L × 10
R1
Select the closest standard value to CFF as possible.
Charger
The RT9945 has an integrated charger with power path integrated MOSFETs. This topology, shown in the simplified block
diagram (Figure 12), enables the goal of using an external input power to run the system and charge the battery. The
power path has single inputs that can be used to select either an external AC_DC adapter or USB port by PWR_ID pin and
different charging current by limitation. The RT9945 connect the end equipment main power rail and charge the battery
pack by the BATT pin.
USB/AC
Adapter System
Power Bus
Q1
PWR_IN VSYS
CC/CV
Dynamic
Q2
LDO Battery
Supplement Battery
BATT
+ Li
Power Path
Current
Control, TS NTC
Scaling and
nCHG_S System power
Charger ISETA
and Current
PWR_ID limit selection Suspend
RSET
The RT9945 charger uses current, voltage, and thermal control loops to charge and protect a single Li+ battery cell. One
enable input PWR_ID pin is supplied to set charging current limits. During pre-charge and fast-charge phases, the charger
output status is pulled low. As the battery voltage approaches 4.2V, the charging current is reduced. When the charging
current drops below 10% of charging current setting and the battery voltage equals 4.2V, the nCHG_S output pin goes
high impedance, signaling a full battery and set the internal I2C register bit CHG DONE. If the charger done is not masked,
the interrupt flag will be trigged. At any time during charging, if the RT9945 internal I2C register bit, Charger ON/OFF, is
clear. Then the charger enters suspend mode, charging stops, and nCHG_S goes high impedance.
Constant
Precharge Fast Charge Voltage Phase Recharge
Phase Phase & Phase
Standby Phase
Programmed 4.2V
Charge
Current
4.1V
Recharge
Threshold
1/10 Programmed
Charge Current 2.8V
Precharge
Threshold Charge
Complete
UVLO > VIN < OVP YES BATT < 4.1V YES YES Fast-CHG State
2 BATT>2.8V ICHG_fast = 1000mA
& I C = ON &VIN > 0.5V < TS < 2.5V
BATT @RISET = 1.5kΩ
NO
NO
Power Off State
PFET = OFF Decrease
Pre-CHG State
Check Thermal NO ICHG_fast
ICHG_pre = 0.1 x
NO Temp.<125°C
ICHG_fast Temp.<125°C
Any State
if VIN < UVLO or
YES
VIN > OVP or
2
I C = OFF or
VIN < BATT
Charge Done State YES NO
ICHG<0.1*ICHG_fast
ICHG = 0A
PWR_IN 5V
SYS 4.65V
4.2V
BATT 4.0V
0V
3A
2A
IBATT 1A
ISYS 0
IPWR_IN -1A
-2A
-3A
T1 T2 T3 T4 T5 T6 T7 T8
NO
ACOK?
YES
NO
AC Current Limit
YES
NO NO
AC supply SYS &
AC & BATT
BATT
YES YES SYS Load > YES supply SYS
Reduce charge ACOK? AC Current Limit AC Current SYS < BATT
current
Limit (T4)
SYS = 4.2V > BATT
(T3,T5) NO NO
Q1
Adapter PWR_IN
VSYS
Power Path
Control,
System power
PWR_ID and Current
ID
limit selection
GND GND
Q1
USB PWR_IN
USB port
from PC or
Notebook LDO
VBUS VBUS
D+ VSYS
D- Power Path
Control,
System power
PWR_ID and Current
ID
limit selection
GND GND
Charge-Current Selection
When powered from a USB port, the input current is available to 0.5A. For AC-Adapter input applications (PWR_ID = Low)
requiring a different current requirement, set the charging current with an external resistor (RSET) from ISETA to GND.
Calculate charge current as follows :
Charge Current = 2.5/ RSET(kΩ) x 600 (mA)
The RT9945 offers ISETA pin to determine the AC charge rate from 100mA to 1A.
Charge-Status Output
nCHG_S is an open-drain output that indicates charger status and can be used with an external LED. nCHG_S goes low
during charging. When VBAT equals 4.2V and the charging current drops below 10% of the setting charge current,
nCHG_S goes high impedance and the RT9945 internal I2C register bit CHG DONE will be set. Connect a pull-up resistor
between nCHG_S and VSYS to indicate charge status.
Soft-Start
To prevent input transients, the change rate of the charge current is limited when the charger is turned on or changes its
current compliance. It takes approximately 1ms for the charger to go from 0mA to the maximum fast-charge current.
VBATT
A
+
ITS
NTC
Temperature TS
Sense
Battery
0.1µF to 10µF
VTS = RTS × 100μA
VBATT
A
+
ITS
NTC
Temperature RT1
TS
Sense
Battery
RT2
0.1µF to 10µF
R × (RT1 + RNTC )
VTS = ITS × T2
RT1 + RT2 + RNTC
Timer
As a safety mechanism, the charger has a user programmable timer that monitors the pre-charge and fast charge time.
This timer (charge safety timer) is started at the beginning of the pre-charge and fast charge period. The safety charge
timeout value is set by the value of an
external capacitor connected to the TIMR pin (CTIMR), if pin TIMR is short to GND, the charge safety timer is disabled.
As CTIMR = 0.1μF, TFAULT is CTIMR (F) x 1.97 x 1011 secs = 19700 secs and TPRECH = TFAULT /8
As timer fault, re-plug-in power or I2C ON/OFF charger again can release the fault condition.
SYS Output
The RT9945 contains a SYS output which can be regulated up to 5V. Bypass SYS to GND with a 22μF or larger ceramic
capacitor to improve the transient droops. When charging a battery, the load on SYS is serviced first and the remaining
available current goes to charge the battery.
Battery PRE-CHARGE
During a charge cycle, if the battery voltage is below the VPRECH threshold and the RT9945 applies a pre-charge mode to
the battery. This feature revives deeply discharged cells and protects battery life. The RT9945 internally determines the
pre-charge rate as 10% of the fast charge current.
Thermal Regulation
The RT9945 features a thermal limit that reduces the charge current when the die temperature exceeds +125°C. As the
temperature increases, the RT9945 features a junction temperature regulation loop. If the power dissipation of the IC
results in a junction temperature greater than the thermal regulation threshold (125°C), the RT9945 throttles back on the
charge current in order to maintain a junction temperature around the thermal regulation threshold (125°C). The RT9945
monitors the junction temperature, TJ, of the die and disconnects the battery from the input if TJ exceeds 125°C. This
operation continues until junction temperature falls below the thermal regulation threshold (125°C) by the hysteresis
level. This feature prevents the maximum power dissipation from exceeding typical design conditions.
Capacitor Selection
Connect a ceramic capacitor from PWR_IN to GND as close to the IC as possible for proper stability. For most applications,
connect a 4.7μF ceramic capacitor from IN to GND as close to the IC as possible.
Linear Regulators
The RT9945 offers five Integrated Linear Regulators, designed to be stable over the operating load range with the use of
external ceramic capacitors.
Low-Battery Detector
nLBO is an open-drain output that typically connects to the BATT FAULT input of the processor to indicate the battery has
been removed or discharged. nLBO is typically pulled up to VSYS. LBI monitors the input voltage (usually connect to
VSYS) and triggers the nLBO output (Figure 21). nLBO is high impedance when the voltage from LBI exceeds the battery
rising threshold VLBITH = 1.05V (typ.). nLBO is low when the voltage from LBI falls below the low-battery falling threshold
VLBITH = 1V (typ.) (Figure 22). Connecting LBI to two-resistor voltage divider to detect the external resistor embedded in
a battery pack and is also used as a pack ID function.
When system first power up or back from deep sleep mode , LBI will check the VSYS voltage. If VSYS voltage is lower
than setting voltage, system will not power up or wake up.
If the low-battery-detector feature is not required, connect nLBO to ground and connect LBI to SYS.
nLBO LBI
SYS
+ 1V
VSYS
- 1.05V
1V
LBI
nLBO
Figure 21. LBI and nLBO Application Circuit Figure 22. Typical LBI Rising and Falling Threshold
Voltage
Thermal Considerations
For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation
depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference
between junction to ambient. The maximum power dissipation can be calculated by following formula :
PD(MAX) = ( TJ(MAX) - TA ) / θJA
Where TJ(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the
junction to ambient thermal resistance.
For recommended operating conditions specification of RT9945, where TJ(MAX) is the maximum junction temperature of
the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout
dependent. For WQFN-40L 5x5 packages, the thermal resistance θJA is 36°C/W on the standard JEDEC 51-7 four layers
thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula :
PD(MAX) = ( 125°C - 25°C) / (36°C/W) = 2.778W for WQFN-40L 5x5 packages
The maximum power dissipation depends on operating ambient temperature for fixed TJ (MAX) and thermal resistance θJA.
For RT9945 packages, the Figure 23 of derating curves allows the designer to see the effect of rising ambient temperature
on the maximum power allowed.
GND GND
CPWR_IN CSYS
PWR_HOLD
R14
PWR_ON
VSYS
HP_PWR
PWR_IN
PWR_IN
PWR_ID
ISETU
CLK
PWR_EN
LBI
S2
S1
L
1
E E2
1 1
2 2
e b
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A3 Note : The configuration of the Pin #1 identifier is optional,
A1
but must be located within the zone indicated.
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,
specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.