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    VLSI Design: Dept. of CSE Bangladesh University

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    Imran Hossain
    The document discusses voltage transfer characteristics (VTC) of ideal and non-ideal inverters. It defines key logic voltage levels such as VIL, VIH, VOL, VOH that describe input and output voltage thresholds. Noise margins NML and NMH represent safety thresholds to prevent erroneous outputs due to noisy inputs. Proper noise margins ensure signals are correctly interpreted as logic 0 or 1.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    VLSI Design: Dept. of CSE Bangladesh University

    Uploaded by

    Imran Hossain
    29 views10 pages
    The document discusses voltage transfer characteristics (VTC) of ideal and non-ideal inverters. It defines key logic voltage levels such as VIL, VIH, VOL, VOH that describe input and output voltage thresholds. Noise margins NML and NMH represent safety thresholds to prevent erroneous outputs due to noisy inputs. Proper noise margins ensure signals are correctly interpreted as logic 0 or 1.

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    VLSI_Lec_4

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    The document discusses voltage transfer characteristics (VTC) of ideal and non-ideal inverters. It defines key logic voltage levels such as VIL, VIH, VOL, VOH that describe input and output voltage thresholds. Noise margins NML and NMH represent safety thresholds to prevent erroneous outputs due to noisy inputs. Proper noise margins ensure signals are correctly interpreted as logic 0 or 1.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    29 views10 pages

    VLSI Design: Dept. of CSE Bangladesh University

    Uploaded by

    Imran Hossain
    The document discusses voltage transfer characteristics (VTC) of ideal and non-ideal inverters. It defines key logic voltage levels such as VIL, VIH, VOL, VOH that describe input and output voltage thresholds. Noise margins NML and NMH represent safety thresholds to prevent erroneous outputs due to noisy inputs. Proper noise margins ensure signals are correctly interpreted as logic 0 or 1.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 10

    VLSI Design

    CSE-3106

    Dept. of CSE
    Bangladesh University
    In Out

    Circuit

    Ideal Scenario

    Out
    In

    Circuit

    Practical Scenario
    The Ideal Inverter

    The ideal inverter has the following voltage transfer characteristic (VTC) and is
    described by the following symbol
    0/1 1/0

    Vout Vout
    Infinite Slope Finite Slope
    Vdd Vdd

    0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin

    Actual I/O Characteristic of a Inverter with Finite Slope


    VTC of Non-Ideal Inverter Voltage Level Definitions

    For the (VTC) of the non-ideal inverter no Vref is defined. There is now an undefined logic state. The
    points (VIH ,VOL ) and (VIL ,VOH ) are defined as the points on the VTC curve where slope is -1.
    Logic Voltage Level Definitions

     VL – The nominal voltage corresponding to


    a low-logic state at the output of a logic
    gate for vi = VH
    Logic Voltage Level Definitions

     VL – The nominal voltage corresponding to a low-logic state at the


    output of a logic gate for vi = VH
     VH – The nominal voltage corresponding to a high-logic state at the
    output of a logic gate for vi = VL
     VIL – The maximum input voltage that will be recognized as a low input
    logic level
     VIH – The minimum input voltage that will be recognized as a high input
    logic level
     VOH – The output voltage corresponding to an input voltage of VIL
     VOL – The output voltage corresponding to an input voltage of VIH
    Top
    ic 7
    -8
    Logic Voltage Level Definitions

    Typically, V-=0.
    V+=5 for bipolar logic,
    V+=1.8, 2.5, 3.3 for MOS logic
    V+=1.0-1.5 for ultra low voltage logic
    Noise Margins

     Noise margins represent “safety margins”


    that prevent the circuit from producing
    erroneous outputs in the presence of noisy
    inputs
     Noise margins are defined for low and high
    input levels using the following equations:

    NML = VIL – VOL

    NMH = VOH – VIH


    Noise Margin Summary

    For any signal to be considered as logic ‘0’ and logic ‘1’, it should be in the NML and
    NMH ranges, respectively

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