ELECTRICAL ENGINEERING DEPARTMENT

ACADEMIC SESSION: DECEMBER 2019

DEC50143 - CMOS IC DESIGN & FABRICATION
PRACTICAL WORK 6 : Layout Design and Simulation of Full Adder
PRACTICAL WORK
DATE :
LECTURER’S NAME: Noor Laila Binti Asha’ari
GROUP NO. :
TOTAL
STUDENT ID & NAME : MARKS
(100%)

(1) HERYANSHAH BIN SUHIMI @SUHAIMI (07DTK18F1016)

DATE SUBMIT : DATE RETURN :

Part A: Designing the layout of 1-bit full adder

1) A 1-bit full adder has been designed by using half-adder and OR gate that have been
inserted from pratical 3 and 5. No error were found when using design rule checker.

1-bit full adder layout

Part B: Simulating the layout of Full Adder

1) Clock has been added to input A, input B and input Cin as shown on figure below.

Figure B.1 – Input A clock settings

Figure B.2 – Input B clock settings

Figure B.3 – Input Cin clock settings

 2) Before the layout has been tested with simulation, the visible node “sum” and “carry”
has been added to the full adder output.

3) The layout has been tested with simulation.

Figure B.4 – Full adder timing diagram and layout simulation

Part C: Designing the layout of IC 4008 - 4 Bit Binary Full Adder

1. An IC 4008 has been designed by using Four(4) 1-bit binary full adder. The Cout of
full adder has been connected to the Cin of the next full adder. The layout was
attached at the next page (Landscape position).
Figure C.1 – Full Adder Layout (IC4008)
 2. There is no error after do DRC. The layout area has been measured.

Figure C.2 – Optimized Layout Area = 901 λ x 512 λ = 461,312 λ2

RESULT:

1. The layout of Full Adder (without any DRC error). (Provided at procedure)
2. The timing diagram of Full Adder. (Provided at procedure)
3. The layout of IC 4008 (without any DRC error). (Provided at procedure)
4. The optimized area of the IC 4008 layout. (Provided at procedure)

DISCUSSION:

1. Explain the theory of full adder along with its truth table.

- Full Adder is the adder which adds three inputs and produces two outputs. The
first two inputs are A and B and the third input is an input carry as C-IN. The
output carry is designated as C-OUT and the normal output is designated as S
which is SUM.

(4 marks)
2. Discuss TWO (2) applications of full adder circuit in electronic system.

- Arithmetic Logic Unit (ALU)

- Ripple Carry Adder
(2 marks)
3. State the steps of how to draw the full adder layout.

Step 1: Draw two input XOR gate and AND gate with connecting them to input
A and B together. XOR gate output as sum and AND gate output as carry.

Step 2: Then, 1-bit half adder produced. After that, draw another 1-bit half
adder and OR gate. Connect sum output to the input A of another half adder
circuit. Let input B of another half adder circuit as Cin.

Step 3: Connect the output of carry to the Input of OR gate.

Step 4: Finally, label the final output as SUM OUT and CARRY OUT.
(4marks)
CONCLUSION:

- 1-bit full adder can be designed using two 1-bit half adder and OR gate.
- 4-bit full adder can be designed using four 1-bit full adder by connecting the
carry out of first 1-bit full adder to the second Cin of full adder.
 PRACTICAL SKILL ASSESSMENT RUBRIC
DEC50143 CMOS IC DESIGN & FABRICATION
PRACTICAL WORK 6
Student Name : HERYANSHAH BIN SUHIMI @SUHAIMI Class : DTK5A – S1
Date :
Student ID# : 07DTK18F1016

SCORE DESCRIPTION
ASPECTS EXCELLENT MODERATE POOR SCALE SCORE
4-5 2-3 1
Use correct technology feature Use correct technology feature
A. Technology feature Use other technology feature. x1
for ALL parts of the layout. for parts of the layout.
Follow lambda design rule for
Follow lambda design rule for Follow lambda design rule for
B. Design rule minimum width and spacing for x1
MANY of the polygons. ONLY a few of the polygons.
ALL polygons.
Use correct PMOS and NMOS Use acceptable PMOS and NMOS Use incorrect PMOS and
C. Transistor size x2
transistor size. transistor size. NMOS transistor size.
Use correct number of metal Use correct metal layers but Use incorrect metal layers and
D. Metal layers x2
layers and width. incorrect width. width.
‘No DRC error’ Able to produce ‘No DRC error’ Able to produce ‘No DRC error’ Not able to produce ‘No DRC
E. x2
display display for ALL layouts. display for some of the layouts. error’ display at ALL.
Layout Design Produce acceptable floorplan
Produce good floorplan and Produce appropriate floorplan
F. – input / output / and input / output layout x2
input / output layout design. and input / output layout design.
floorplan design.
Not able to produce any
Able to produce the simulation Able to produce the simulation
G Layout simulation simulation for ALL of the x2
of ALL layouts correctly. for some of the layouts correctly.
layouts.
Layout size (end Produce small layout size (end Produce acceptable layout size Produce large layout size (end
H. x2
product) product). (end product). product).
TOTAL / 70

…………….…………………….
Supervisor Name & Signature
 SUSTAINABILITY AND ENVIRONMENT FRIENDLY SKILL RUBRIC - CLO3

SCORE DESCRIPTION
ITEM ASPECTS EXCELLENT MODERATE POOR SCALE SCORE
4-5 2-3 1

Layout Performance Total using technology feature Using technology feature Not using transistor technology
& Low Power Design having green elements to achieve having green elements either to feature having green elements to
technology feature both layout performance achieve layout performance achieve layout performance
A. x 10 / 50
efficiency and low power efficiency or low power efficiency and low power
consumption is evident in the consumption in the final consumption in the final layout.
final layout. layout.
B. Final IC Layout Size Total usage of environment Using environment friendly, No usage of environment
friendly, green materials / green materials / elements or friendly, green materials /
elements or reduce, recycled and reduce, recycled and reused elements or reduce, recycled and
x 10 / 50
reused concept to produce small concept that help to produce reused concept thus producing
IC layout size is clearly evident. acceptable IC layout size is large IC layout size.
partly evident.
Total Generic Skill : / 100

…………….…………………….
Supervisor Name & Signature