How to Efficiently Analyze a DDR4

Interface
Taranjit Kukal
Zhen Mu Ph.D
Cadence Design Systems
MemCon 2015
Agenda

• Power-aware signal integrity (SI) in memory bus design and

analysis
• Modeling methodology for integrated core and power-aware
parallel bus system with Cadence-Sigrity tools
• Building an integrated core and power-aware parallel bus
system in Cadence-Sigrity tool environment
• Case study
– A virtual reference design based on the Cadence DDR4 IP test chip,
package, and PCB
– Simulation and measurement correlation

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 Parallel Bus Analysis at System Level

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Challenges to classic SI tools

• As clock rate goes up and

design density increases,
memory design faces more
challenges
– Data rates increase
– Core voltage and I/O voltage
decrease
– Impact of power noise on signal
increases
– Noise budget decreases
• SI tools need to provide
solutions to meet new
design requirements

4 © 2015 Cadence Design Systems, Inc. All rights reserved.

SSO/SSN impact on design

• Design problems caused by SSO

– False triggers due to power/ground level changes
– Reduced timing margin due to SSO induced skew
– Reduced voltage margin due to power/ground noise
– Slew rate variation

Courtesy of VIA Technologies

5 © 2015 Cadence Design Systems, Inc. All rights reserved.

DDR4 technology demands

• Increasing data rates

• Shrinking design margin
• Decreasing power
• Introducing serial link
design methodologies
– JEDEC standard specifies
BER for data signals
• Design and analysis need
to consider core and
system at the same time

6 © 2015 Cadence Design Systems, Inc. All rights reserved.

 Modeling methodology for integrated core
and power aware parallel bus system with
Cadence-Sigrity tools

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Systems,Inc. All All
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rights worldwide. Cadence and the Cadence logo are
reserved.
registered trademarks and Sigrity is a trademark of Cadence Design Systems.
Core and power-aware parallel bus systems

• Core System  Power-Aware Parallel Bus

PCB
Package
C4-Bumps
System
DECAPS
DECAPS Package C4-Bumps
DECAPS
PCB
PACKAGE PCB
PACKAGE
DIE
TRACE IOs CORE IOs C5-Balls DIE
IOs CORE IOs
Cdie
C5-Balls
-- nes
TRACE
Cdie

l la s&
Pla

-- yers
VRM

na ane
G-

(OVDD) -- VRM
PK

Sig G-Pl
(OVDD)
TOP

--
PK
TOP
VDD
OVDD
GND Signal
-- nes
OVDD GND

l la s&
BOTTOM
Pla

-- yers
VRM

na ane
VRM BOTTOM
B-

(VDD) GND-Via (VDD)

Sig B-Pl
GND-Via
PC

--

(IOs)
--
GND-Via

PC
OVDD-Via

--
TOP (Core) TOP

--
OVDD-Via
VDD-plane VDD-Via VDD/OVDD-plane
Signal-Via
GND-plane Signal layer

OVDD-plane OVDD-Via GND-Via GND-plane

BOTTOM BOTTOM

Core Power Distribution Path for POWER-INTEGRITY (PI) SIGNALS Switching through
power and ground references

8 © 2015 Cadence Design Systems, Inc. All rights reserved.

 Power-aware parallel bus

• PCB parallel bus consists of data and strobe signal nets and
power distribution network (PDN)

1st-byte lane of 2nd-byte lane of

• DATA (DQ<0>-DQ<7>) and • DATA (DQ<8>-DQ<15>) and
• STROBE (DQS_N<0> & DQS_P<0>) • STROBE (DQS_N<1> & DQS_P<1>)
• PDNs consists of PWR and GND planes of PCB (packages)
9 © 2015 Cadence Design Systems, Inc. All rights reserved.
Cadence IO SSO Chip-PKG-PCB Co-Simulation
VDD_IO
Chip Package PCB
Main
Buffer Input
Driver

Receiver
Main Buffer
RX
Input
Buffer
Main Buffer
107mV
Buffer

VSS VRM

Including Chip IO
Interconnect Model

10 © 2015 Cadence Design Systems, Inc. All rights reserved.

Core-system model

Core-Model IC-Package Model PCB Model Core-VRM-Model

Rcore_1 Lcore_1 Lcore_2 Rcore_2 Lr
Rgrid S-parameter
ImuP Cb Rr
model from
R-L-C model PowerSI Cd +
from XtractIM for PCB Rb -
Cchip for Core-PDN, Rd Vdd
Norton IC-Package With PCB Lb
Equivalent Core-PDN, DECAPS
Circuit w/wo Behavioral from the
Package output impedance
DECAPS characteristic

• Rgrid, Cchip values and current profile are critical for

optimizing power integrity performance of Core-PDN
• Minimizing transient voltage drop at the core is critical to
guarantee the specified core-operating frequency

11 © 2015 Cadence Design Systems, Inc. All rights reserved.

A model of power-aware parallel bus system
Controller Memory
Controller Package PCB Connector Package Memory
Sig-1
IO-pwr-die CLoad
IO-PDN, PCB
Sig-2
IO-PDN,
IO- gnd-die Signal-Nets with
Signal-Nets CLoad
and IO-PDN,
and
w/wo Signal-Nets
IO1
Sig-1 w/wo
Package and
Package
Sig-2 DECAPS w/wo
DECAPS
for IO-PDN Package
for IO-PDN Power-aware
IO2 DECAPS for
IBIS Model
IO-PDN Using T2B
R-L-C Model
from XtractIM CLoad
or S-parameter R-L-C Model
S-parameter Model from from XtractIM
or
Model from PowerSI S-parameter
PowerSI (Field Solver)Sig-N
IOn Model from
Sig-N(Field Solver) PowerSI CLoad
(Field Solver)
Power-aware
SPICE
IBIS Model Circuit
Using T2B SPICE Model
Circuit
Power-aware IOs are connected
IO-VRM
to DATA and STROBE nets
12 © 2015 Cadence Design Systems, Inc. All rights reserved.
Integrated core and power-aware parallel bus
system
Core-Model Package PCB VRM-Model

Rgrid Cb Rr Core-System
ImuP Cd +
Core-PDN
Rb
SPICE
- Model
Cchip Circuit
Rd Vdd
SPICE Lb Model
Circuit
Model
DIMM Routing Memory Termination
Controller
Sig-1 Rt1
IO-pwr-die PCB CLoad
IO-PDN, Rt2 Vt Model of
IO- gnd-die Signal-Nets with Sig-2

and IO-PDN, CLoad power-

Sig-1 w/wo Signal-Nets Rt1 aware
IO1 and
Package SPICE
Sig-2 DECAPS w/wo Circuit Rt2 Vt parallel bus
for IO-PDN Package Model
IO2 DECAPS for
IO-PDN SPICE
R-L-C Model Rt1 Circuit
from XtractIM CLoad Model
or S-parameter Rt2 Vt
S-parameter Model from
Model from PowerSI
PowerSI (Field Solver)Sig-N Rt1
IOn
Sig-N (Field Solver) CLoad
Rt2 Vt

Power-aware
IBIS Model Power-aware
Using T2B SPICE IBIS Model
Circuit
Model
IO-VRM Power-aware IOs are connected
to DATA and STROBE nets
Using T2B

13 © 2015 Cadence Design Systems, Inc. All rights reserved.

Efficient modeling simulation and analysis process
for core and system
Using MCP Editor of SystemSI, Create
. Build Block-level Model
of the Integrated Core&System in SystemSI
Additional Connecting Ports in the Connector
model for connecting Memory and
Termination blocks
Generate Electrical Models for
[1] Parallel Bus + IO_PDN + Core_PDN
Assign Electrical Models to
of PCB, using PowerSI
[4] Controller [5] Memory [6] VRMs, and
[2] Parallel Bus + IO_PDN + Core_PDN of [7] Memory Termination and [8] Core blocks
Packages, using XtractIM/PowerSI
[3] Power-aware Controller and Memory, Connect Blocks of the Integrated
using T2B or SPICE Core&System
[4] VRM for Core-PDN and IO-PDN, using
R-L-C and DC-source
[5] Core (Norton Equivalent Circuit Model) Check Connectivity between blocks based on
the Frequency-domain simulation
[6] Interconnect (as per JDEC spec)
[7] Termination circuit (Rt and Vt) Setup Parameters for time-domain
simulations of Integrated Core &System

Assign Electrical Models to Run Time -domain Simulations for Power

[1] PCB [2] Package and [3] Connector blocks, and Signal Integrity performance evaluations
of Core&System

Using MCP Editor of SystemSI, Create Additional Analyze Simulation Results for Power and
Connecting Ports in the PCB model for Signal integrity performance of
connecting Package, Connector and VRM blocks Core&System: 2D waveforms and Reports

14 © 2015 Cadence Design Systems, Inc. All rights reserved.

 Building an integrated core and power
aware parallel bus system

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SPEED2000
All rightsare trademarks of Cadence Design Systems.
reserved.
Today’s parallel bus design needs new functions
for system level design and verification
• Traditionally, all connections of sub-systems have to appear in topology
editor
• The complexity of power-aware system makes setup and connection very
difficult

Main
Buffer Input
Main Buffer
Input
RX
Main
Buffer Buffer
Buffer

Impossible/impractical to connect all

sub-system representations, S-
parameters and Spice circuits with many
ports, in a topology-editing-only
environment

16 © 2015 Cadence Design Systems, Inc. All rights reserved.

Power-aware SI: Cadence® Sigrity™ SystemSI™
technology

• An evolution from topology based environment and physical

layout
– Keeping the advantage of topology editing
– Providing a clear view of system connection

17 © 2015 Cadence Design Systems, Inc. All rights reserved.

Power-aware SI: Cadence® Sigrity™ SystemSI™
technology (cont’)
• Hierarchical bus topologies
– As simple and direct as in topology environment for pre-layout
exploration
– As efficient and complete as in physical layout for sub-system
connections

18 © 2015 Cadence Design Systems, Inc. All rights reserved.

SystemSI™ as the design platform

• Blocks represent each sub-system for the integrated core

and power-aware parallel bus system
• Built-in, application-specific blocks for
− Controller
− Memory,
− VRM and
− Add blocks

19 © 2015 Cadence Design Systems, Inc. All rights reserved.

 PowerSI™
Electrical model generation
T2B™
XcitePI™

T2B™

PowerSI™

XtractIM™
20 © 2015 Cadence Design Systems, Inc. All rights reserved.
Power-aware IBIS I/O models

• Power-aware I/O buffer models for the controller and

memory devices are “must have” for time-domain SSN
simulations
− IBIS 5.0 standard provides power/ground current details
− Pre-driver current, crow-bar current, and on-die decap current information
− Simulation with IBIS 5.0 models is efficient and proven-
accurate
• Sigrity™ T2B (transistor-to-behavioral) tool generates the
power-aware IBIS models in 5.0 standard

21 © 2015 Cadence Design Systems, Inc. All rights reserved.

Power-aware IBIS model generation using T2B™
tool
• Sigrity™ T2B™ model conversion utility tool can be used for
efficiently converting
− SPICE-Transistor I/O models to power-aware IBIS I/O
models, standard v5.0

22 © 2015 Cadence Design Systems, Inc. All rights reserved.

Core model extraction using XcitePI™

Inputs
• LEF/DEF or GDS
LEF/DEF GDS GUI
• Cadence technology file (.ict)
• XcitePI configuration file or
Outputs
• Core / IO interconnect model
− SPICE netlist XcitePI - IOME
Electrical
What-if Model
• Model results Performance
Assessment
Analysis Generation

− Power pin RL
− Power net capacitance
SPICE
− Power net impedance Netlist

− Signal net RLC

− Signal net return and
insertion loss
23 © 2015 Cadence Design Systems, Inc. All rights reserved.
Package model generation using Sigrity™
XtractIM™ tool

• Package model
IC-Package Layout file (.SPD)
for core and
system can be XtractIM(XIM)
extracted using Full Wave
Solver

Sigrity™ Single
Broadband
XtractIM™ tool frequency
extraction
frequency
extraction

Optimization SPICE Sub-circuit

over broadband (Single-stage IBIS-[Pin]
frequency Lumped RLC and
(DC-2 or 3 GHz) circuit) [Package Model]

Multi-stage RLC
circuit with
Broadband
accuracy

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PCB model generation using Sigrity™ PowerSI™
tool
• S-parameter model of PCB contains couplings
between signals and power nets, with true return
path represented

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25
Connecting blocks in SystemSI™

• Blocks of core and power-aware parallel bus system are

connected through MCP (Model Connection Protocol)

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 Solution demonstration: An LPDDR4
design

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LPDDR4 package-on-package

• Low-power parallel
designs in mobile
applications
– Controller die
– 12X12mm BGA
– Pin count = 216
– Memory package
– 12X12mm BGA
– Pin count = 216
– Bottom package
– 18X18mm BGA
– Pin count = 289
– 4 layers

28 © 2015 Cadence Design Systems, Inc. All rights reserved.

Package design in Allegro Package Designer

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Inc. All rights Systems.
Extracting package interconnects using Sigrity
XtractIM technology

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XtractIM are trademarks
All rights reserved.of Cadence Design Systems.
Simulating LPDDR4 design using Sigrity
SystemSI technology
Building block topology

Defining bus groups

Setting up timing budget

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SystemSI are trademarks
All rights reserved. of Cadence Design Systems.
Reporting measurements of a LPDDR4 design
using Sigrity SystemSI technology

Generating measurement report

Defining eye masks

for Data and Addr

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Design Sigrity is a Inc.
trademark of Cadence
All rights Design Systems.
reserved.
Generating measurement report for timing and
signal quality

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Signal quality reported by simulating the design
with channel analysis option

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 Case study: Simulation and measurement
correlation of a DDR4 design

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2015Cadence
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rights worldwide. Cadence and the Cadence logo are
reserved.
registered trademarks and Sigrity is a trademark of Cadence Design Systems.
 PowerSI
Topology
T2B
XcitePI

PowerSI

XtractIM
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Stimulus settings

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Distributed power network at controller

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Power at the memory side (ripple +/- 0.02 V)

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 Eye Mean
Eye height measurement Height
Sim Results 556 mV
H/W Results 526 mV

Peak to peak 0.8 V

Peak to peak 0.8 V

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 Eye Width Mean
Eye width measurement Sim Results 412 ps

H/W Results 403 ps

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 tDIPW(DQ)
Data tDIPW measurement Mean Max Min

Sim Results 473 ps 449 ps

H/W Results 586 ps - 453 ps

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Strobe tDQSH/tDQSL measurement tDQSH Mean
Sim Results 470 ps

H/W Results 455 ps

tDQSH Mean
Sim Results 468 ps

H/W Results 476 ps

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Report generation settings

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tDVAC variation with cycle of a DQS net

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tDVAC Strobe report
tDVAC Mean Max Min

Sim Results 367 ps 360 ps

H/W Results 347 ps 382.7 ps 343.10 ps

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Slew rate variation with cycle of a DQ net

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Slew rate report SRIN_dIVW_Fall Mean Max Min

Sim Results -3.13 V/ns -1.96 V/ns

H/W Results - 2.32 V/ns -2.81 V/ns -2.19 V/ns

SRIN_dIVW_Rise Mean Max Min

Sim Results 2.92 V/ns 1.92 V/ns

H/W Results 1.86 V/ns 2.79 V/ns 1.8 V/ns

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 Summary

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Conclusion

• DDR4 and LPDDR4 technologies pose new challenges to

parallel bus design and analysis
– Serial link design methods introduced to the design specification
– Lower power assumption requires dedicated margin tuning
• Combination of power-aware SI simulation and channel
simulation is the only way to support these new technologies
• Cadence Sigrity™ technology provides comprehensive
system level SI/PI solutions for core, package, and PCB
– Unique methodology of power-aware simulation for core and parallel
bus system
– Behavioral model (Chip and core power) generation and simulation
– Package and board model extraction
– Integration of patented channel simulation approach in parallel bus
analysis flow

52 © 2015 Cadence Design Systems, Inc. All rights reserved.

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and Allegro are
registered trademarks and Sigrity, SystemSI, and XtractIM are trademarks of Cadence Design Systems. All other
trademarks are the property of their respective owners.