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    Process: Power Transistor

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    Nelson antonio
    This document provides details on process CP219 for an NPN high current transistor chip, including the epitaxial planar process used, die size and thickness specifications, bonding pad areas and metalization details, gross die yield per wafer, and principal device types produced using this process. Electrical characteristics are also specified but not detailed here.

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    Process: Power Transistor

    Uploaded by

    Nelson antonio
    11 views2 pages
    This document provides details on process CP219 for an NPN high current transistor chip, including the epitaxial planar process used, die size and thickness specifications, bonding pad areas and metalization details, gross die yield per wafer, and principal device types produced using this process. Electrical characteristics are also specified but not detailed here.

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    CP219l

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    This document provides details on process CP219 for an NPN high current transistor chip, including the epitaxial planar process used, die size and thickness specifications, bonding pad areas and metalization details, gross die yield per wafer, and principal device types produced using this process. Electrical characteristics are also specified but not detailed here.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    11 views2 pages

    Process: Power Transistor

    Uploaded by

    Nelson antonio
    This document provides details on process CP219 for an NPN high current transistor chip, including the epitaxial planar process used, die size and thickness specifications, bonding pad areas and metalization details, gross die yield per wafer, and principal device types produced using this process. Electrical characteristics are also specified but not detailed here.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    PROCESS CP219

    Power Transistor
    NPN - High Current Transistor Chip

    PROCESS DETAILS
    Process EPITAXIAL PLANAR
    Die Size 83 x 83 MILS
    Die Thickness 11 MILS
    Base Bonding Pad Area 13.2 x 19.7 MILS
    Emitter Bonding Pad Area 13.2 x 21.2 MILS
    Top Side Metalization Al - 30,000Å
    Back Side Metalization Au - 12,000Å

    GEOMETRY
    GROSS DIE PER 4 INCH WAFER
    1,670

    PRINCIPAL DEVICE TYPES


    2N5336
    2N5337
    2N5338
    2N5339
    2N5427
    2N5428
    2N5429
    2N5430
    D44H11
    CJD44H11

    BACKSIDE COLLECTOR

    R3 (22-March 2010)
    w w w. c e n t r a l s e m i . c o m
    PROCESS CP219
    Typical Electrical Characteristics

    R3 (22-March 2010)
    w w w. c e n t r a l s e m i . c o m

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