Microprocessor and Peripherals Interfacing-ECC501

Q1) Discuss features of Microprocessor 8086. 

Buses:
Address Bus:​ 8086 has a 20-bit address bus, hence it can access 220 Byte memory i.e. 1MB. The
address range for this memory is 00000H … FFFFFH.

Data Bus:​ 8086 has a 16-bit data bus i.e. it can access 16 bit data in one operation. Its ALU and
internal data registers are also 16-bit.
Hence 8086 is called as a 16-bit µP.

Control Bus:​ The control bus carries the signals responsible for performing various operations such
as RD , WR etc.

8086 supports Pipelining​.

It is the process of “Fetching the next instruction, while executing the current instruction”. Pipelining
improves performance of the system.

8086 has 2 Operating Modes.

Minimum Mode … here 8086 is the only processor in the system (uni-processor).
Maximum Mode … 8086 with other processors like 8087-NDP/8089-IOP etc. Maximum mode is
intended for multiprocessor configuration.

8086 provides Memory Banks.

The entire memory of 1 MB is divided into 2 banks of 512KB each, in order to transfer 16-
bits in 1 cycle. The banks are called Lower Bank (even) and Higher Bank (odd).

8086 supports Memory Segmentation.

Segmentation means dividing the memory into logical components. Here the memory is divided into
4 segments: Code, Stack, Data and Extra Segment.

8086 has 256 interrupts.

The ISR addresses for these interrupts are stored in the IVT (Interrupt Vector Table).

​8086 has a 16-bit IO address​ it can access 216 IO ports (216 = 65536 i.e. 64K IO Ports).
Q2) Draw and explain the block diagram of microprocessor based system

Ans.: T​he microprocessor is a semiconductor device (Integrated Circuit) manufactured by the VLSI
(Very Large Scale Integration) technique. It includes the ALU, register arrays and control circuit on a
single chip.
● A system designed using a microprocessor as its CPU is called a microcomputer. The
Microprocessor based system (single board microcomputer) consists of microprocessor as
CPU, semiconductor memories like EPROM and RAM, input device, output device and
interfacing devices.
● The memories, input device, output device and interfacing devices are called peripherals.
The popular input devices are keyboard and floppy disk and the output devices are printer,
LED/LCD displays, CRT monitor, etc.

● In the µP based system, the microprocessor is the master and all other peripherals are
slaves. The master controls all the peripherals and initiates all operations. The work done by
the processor can be classified into the following three groups.

Work done internal to the processor

Work done external to the processor

Operations initiated by the slaves or peripherals.

● The work done internal to the processors are addition, subtraction, logical operations, data
transfer operations, etc.
● The work done external to the processor is reading/writing the memory and reading/writing
the I/O devices or the peripherals. If the peripheral requires the attention of the master then
it can interrupt the master and initiate an operation.
● The microprocessor is the master, which controls all the activities of the system. To perform
a specific job or task, the microprocessor has to execute a program stored in memory. The
program consists of a set of instructions. It issues address and control signals and fetches the
instruction and data from memory.
 BUSES:
The buses are group of lines that carries data, address or control signals.

● The CPU Bus has multiplexed lines, i.e., same line is used to carry different signals
● The CPU interface is provided to demultiplex, the multiplexed lines, to generate chip select
signals and additional control signals.
● The system bus has separate lines for each signal.
All the slaves in the system are connected to the same system bus. At any time instant
communication takes place between the master and one of the slaves.

PERIPHERAL DEVICES:

● The EPROM memory is used to store permanent programs and data.

● The RAM memory is used to store temporary programs and data.
● The input device is used to enter the program, data and to operate the system.
● The output device is used for examining the results.

Since the speed of I/O devices does not match with the speed of microprocessor, an
interface device is provided between system bus and I/O devices. Generally I/O devices are
slow devices.
Q3) Draw and explain Architecture of 8086 Microprocessors

8086 has 2-stage pipelining, its architecture is divided into two units:
Bus Interface Unit (BIU)
Execution Unit (EU)

BUS INTERFACE UNIT (BIU)

It provides the interface of 8086 to other devices.

It operates w.r.t. Bus cycles .
This means it performs various machine cycles such as Mem Read, IO Write
etc to transfer data with Memory and I/O devices.
It performs the following functions:
It generates the 20-bit physical address for memory access.
Fetches Instruction from memory.
Transfers data to and from the memory and IO.
Supports Pipelining using the 6-byte instruction queue.
The main components of the BIU are as follows:

SEGMENT REGISTERS:

CS Register
CS holds the base (Segment) address for the Code Segment. All programs are stored in the
Code Segment.
It is multiplied by 10H (16d), to give the 20-bit physical address of the Code Segment. Eg: If
CS = 4321H then CS 10H = 43210H Starting address of Code Segment.
CS register cannot be modified by executing any instruction except branch instructions

DS Register
DS holds the base (Segment) address for the Data Segment.
It is multiplied by 10H (16d), to give the 20-bit physical address of the Data Segment. Eg: If
DS = 4321H then DS 10H = 43210H Starting address of Data Segment.

SS Register
SS holds the base (Segment) address for the Stack Segment.
It is multiplied by 10H (16d), to give the 20-bit physical address of the Stack Segment. Eg: If
SS = 4321H then SS 10H = 43210H Starting address of Stack Segment.

ES Register
ES holds the base (Segment) address for the Extra Segment.
It is multiplied by 10H (16d), to give the 20-bit physical address of the Extra Segment. Eg: If
ES = 4321H then ES 10H = 43210H Starting address of Extra Segment.

Instruction Pointer (IP register)

It is a 16-bit register.
It holds offset of the next instruction in the Code Segment.

Address of the next instruction is calculated as CS x 10H + IP. IP is incremented after every
instruction byte is fetched.
IP gets a new value whenever a branch occurs.

Address Generation Circuit

The BIU has a Physical Address Generation Circuit. It generates the 20-bit physical address
using Segment and Offest addresses using the formula:
Physical address = Segment Address x 10h + Offset Address

Viva Question:​ Explain the real procedure to obtain the Physical Address?
The Segment address is left shifted by 4 positions, this multiplies the number by 16 (i.e. 10h)
and then the offset address is added.
Eg: If Segment address is 1234h and 0ffset address is 0005h, then the physical address
(12345h) is calculated as follows: 1234h = (0001 0010 0011 0100)binary
Left shift by four positions and we get (0001 0010 0011 0100 0000)binary i.e. 12340h
Now add (0000 0000 0000 0101)binary i.e. 0005h and we get (0001 0010 0011 0100
0101)binary i.e. 12345h.

6-Byte Pre-Fetch Queue {Pipelining – 4m}

It is a 6-byte FIFO RAM used to implement Pipelining.
Fetching the next instruction while executing the current instruction is called Pipelining.
BIU fetches the next “six instruction-bytes” from the Code Segment and stores it into the
queue. Execution Unit (EU) removes instructions from the queue and executes them.
The queue is refilled when atleast two bytes are empty as 8086 has a 16-bit data bus.
Pipelining increases the efficiency of the µP.
Pipelining fails when a branch occurs, as the pre-fetched instructions are no longer useful.
Hence as soon as 8086 detects a branch operation, it clears/discards the entire queue. Now,
the next six bytes from the new location (branch address) are fetched and stored in the
queue and Pipelining continues.

Execution Unit (EU)

It fetches instructions from the Queue in BIU, decodes and executes them.
It performs arithmetic, logic and internal data transfer operations.
It sends request signals to the BIU to access the external module.
It operates w.r.t. T-States (clock cycles).

The main components of the EU are as follows:

General Purpose Registers

8086 has four 16-bit general-purpose registers AX, BX, CX and DX. These are available to
the programmer, for storing values during programs. Each of these can be divided into two
8-bit registers such as AH, AL; BH, BL; etc. Beside their general use, these registers also
have some specific functions.
AX Register (16-Bits)
It holds operands and results during multiplication and division operations. All IO data
transfers using IN and OUT instructions use A reg (AL/AH or AX). It functions as
accumulator during string operations.

BX Register (16-Bits)
Holds the memory address (offset address), in Indirect Addressing modes.

CX Register (16-Bits)
Holds count for instructions like: Loop, Rotate, Shift and String Operations.

DX Register (16-Bits)
It is used with AX to hold 32 bit values during Multiplication and Division.
It is used to hold the address of the IO Port in indirect IO addressing mode.

Special Purpose Registers

Stack Pointer (SP 16-Bits)
It is holds offset address of the top of the Stack. Stack is a set of memory locations operating
in LIFO manner. Stack is present in the memory in Stack Segment.
SP is used with the SS Reg to calculate physical address for the Stack Segment. It used
during instructions like PUSH, POP, CALL, RET etc. During PUSH instruction, SP is
decremented by 2 and during POP it is incremented by 2.

Base Pointer (BP 16-Bits)

BP can hold offset address of any location in the stack segment.
It is used to access random locations of the stack.

Source Index (SI 16-Bits)

It is normally used to hold the offset address for Data segment but can also be used for other
segments using Segment Overriding. It holds offset address of source data in Data Seg,
during String Operations.

Destination Index (DI 16-Bits)

It is normally used to hold the offset address for Extra segment but can also be used for
other segments using Segment Overriding. It holds offset address of destination in Extra
Seg, during String Operations.

ALU (16-Bits)
It has a 16-bit ALU. It performs 8 and 16-bit arithmetic and logic operations.

Operand Register
It is a 16-bit register used by the control register to hold the operands temporarily. It is not
available to the Programmer.

Instruction Register and Instruction Decoder (Present inside the Control Unit) The EU
fetches an opcode from the queue into the Instruction Register. The Instruction Decoder
decodes it and sends the information to the control circuit for execution.
 Flag Register (16-Bits)

It has 9 Flags.
These flags are of two types: 6-Status (Condition) Flags and 3-Control Flags.
Status flags are affected by the ALU, after every arithmetic or logic operation. They give the
status of the current result.
The Control flags are used to control certain operations. They are changed by the
programmer.

STATUS FLAGS

Carry flag (CY)

It is set whenever there is a carry {or borrow} out of the MSB of a the result (D7 bit for an
8-bit operation D15 bit for a 16-bit operation)

Parity Flag (PF)

It is set if the result has even parity.

Auxiliary Carry Flag (AC)

It is set if a carry is generated out of the Lower Nibble. It is used only in 8-bit operations like
DAA and DAS.

Zero Flag (ZF)

It is set if the result is zero.

Sign Flag (SF)

It is set if the MSB of the result is 1.
For signed operations, such a number is treated as –ve.
 Overflow Flag (OF)
It will be set if the result of a signed operation is too large to fit in the number of bits available
to represent it. It can be checked using the instruction INTO (Interrupt on Overflow).

CONTROL FLAGS
Trap Flag (TF)
It is used to set the Trace Mode i.e. start Single Stepping Mode.
Here the P is interrupted after every instruction so that the program can be debugged.

Interrupt Enable Flag (IF)

It is used to mask (disable) or unmask (enable) the INTR interrupt.

Direction Flag (DF)

If this flag is set, SI and DI are in auto-decrementing mode in String Operations.
MEMORY SEGMENTATION IN 8086

Q4) Explain the need of segmentation

Or Explain the concept of segmentation

Ans.:

Segmentation means dividing the memory into logically different parts called segments.
8086 has a 20-bit address bus, hence it can access 220 Bytes i.e. 1MB memory.
But this also means that Physical address will now be 20 bit.
It is not possible to work with a 20 bit address as it is not a byte compatible number. (20
bits is two and a half bytes).
To avoid working with this incompatible number, we create a virtual model of the memory.
Here the memory is divided into 4 segments: Code, Stack Data and Extra.
 The max size of a segment is 64KB and the minimum size is 16 bytes.
Now programmer can access each location with a VIRTUAL ADDRESS.
The Virtual Address is a combination of Segment Address and Offset Address.
Segment Address indicates where the segment is located in the memory (base address)
Offset Address gives the offset of the target location within the segment.
Since both, Segment Address and Offset Address are 16 bits each, they both are
compatible numbers and can be easily used by the programmer.
Moreover, Segment Address is given only in the beginning of the program, to initialize the
segment. Thereafter, we only give offset address.
Hence we can access 1 MB memory using only a 16 bit offset address for most part of the
program. This is the advantage of segmentation.
Moreover, dividing Code, stack and Data into different segments, makes the memory more
organized and prevents accidental overwrites between them.
The Maximum Size of a segment is 64KB because offset addresses are of 16 bits. 216 =
64KB.
As max size of a segment is 64KB, programmer can create multiple Code/Stack/Data
segments till the entire 1 MB is utilized, but only one of each type will be currently active.
The physical address is calculated by the microprocessor, using the formula:
PHYSICAL ADDRESS = SEGMENT ADDRESS X 10H + OFFSET ADDRESS
Ex: if Segment Address = 1234H and Offset Address is 0005H then Physical Address =
1234H x 10H + 0005H = 12345H
This formula automatically ensures that the minimum size of a segment is 10H bytes
(10H = 16 Bytes).

Code Segment
This segment is used to hold the program to be executed.
Instruction are fetched from the Code Segment.
CS register holds the 16-bit base address for this segment.
IP register (Instruction Pointer) holds the 16-bit offset address.

Data Segment
This segment is used to hold general data.
This segment also holds the source operands during string operations.
DS register holds the 16-bit base address for this segment.
BX register is used to hold the 16-bit offset for this segment.
SI register (Source Index) holds the 16-bit offset address during String Operations.
Stack Segment
This segment holds the Stack memory, which operates in LIFO manner.
SS holds its Base address.
SP (Stack Pointer) holds the 16-bit offset address of the Top of the Stack.
BP (Base Pointer) holds the 16-bit offset address during Random Access.

Extra Segment
This segment is used to hold general data
Additionally, this segment is used as the destination during String Operations. ES holds the
Base Address.
DI holds the offset address during string operations.

Advantages of Segmentation:
It permits the programmer to access 1MB using only 16-bit address.
Its divides the memory logically to store Instructions, Data and Stack separately.

Disadvantage of Segmentation:
1)Although the total memory is 16*64 KB, at a time only 4*64 KB memory can be accessed.
Q5) Explain Memory banking in 8086
Ans.:
As 8086 has a 16-bit data bus, it should be able to access 16-bit data in one cycle.
To do so it needs to read from 2 memory locations, as one memory location carries
only one byte. 16-bit data is stored in two consecutive memory locations.
However, if both these memory locations are in the same memory chip then they
cannot be accessed at the same time, as the address bus of the chip cannot contain two
address simultaneously.
Hence, the memory of 8086 is divided into two banks each bank provides 8-bits.
The division is done in such a manner that any two consecutive locations lie in two
different chips. Hence each chip contains alternate locations.
One bank contains all even addresses called the “Even bank”, while the other is
called “Odd bank” containing all odd addresses.
Generally for any 16-bit operation, the Even bank provides the lower byte and the
ODD bank provides the higher byte. Hence the Even bank is also called the Lower bank and
the Odd bank is also called the Higher bank.

ODD Bank EVEN Bank

Also called as “Higher bank” Also called as “Lower bank”

Address range: Address range:

00001H 00000H
00003H 00002H
00005H 00004H
. .
FFFFFH FFFFEH

Selected when BHE = 0 Selected when A0 = 0

BHE A0 OPERATION

0 0 R/W 16-bit from both banks

0 1 R/W 8-bit from higher bank

1 0 R/W 8-bit from lower bank

1 1 No operation (Idle).
Q6) Explain Pin configuration of 8086
PIN DESCRIPTIONS
Machine Cycles

S2’ S1’ S0’ Bus Cycle / Machine Cycle

0 0 0 INTA Cycle

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode Fetch

1 0 1 Memory Read

1 1 0 Memory Write

1 1 1 Inactive

Segment Selection

S4 S3 Segment. Selected

0 0 Extra Segment

0 1 Stack Segment

1 0 CS/No Segment Selected

1 1 Data Segment

Queue Synchronization

QS1 QS0 Queue Operation

0 0 NOP

0 1 Opcode Fetch from queue

1 0 Queue is Cleared

1 1 Fetch remaining instruction bytes from queue

 CLK
This is the clock-input line.
An external clock generator (8284) provides the clock signal. 8086 required single phase,
33% duty cycle, TTL clock signal.

RESET
This is the reset input signal. The 8284 Clock generator provides it. It Clears the Flag
register and the Instruction Queue.
It also Clears the DS, SS, ES and IP registers and Sets the bits of CS register.
Hence the reset vector address of 8086 is FFFFOH
(as CS = FFFFH and IP = 0000H).

READY
This signal is used to synchronize the P with slower peripherals. Devices inform the P
whether they are ready or not.
µP samples the READY input during T3 state of a Machine Cycle If device is Ready it send a
“1” on the Ready pin else send a “0”.
If Ready pin is 0, P inserts wait-states between T3 and T4 and will only come out of Wait
state when Ready becomes 1 thereby ensuring that the Device is ready.

TEST
It is an active low input line dedicated for 8087 Co-processor.
In Maximum Mode whenever the Co-Processor is busy it makes this pin HIGH.
µP samples the TEST input only when it encounters the WAIT instruction.

If the TEST pin is high, the µP enters wait state, till TEST pin becomes low i.e. 8087 is free.
In minimum mode it is not used and is connected to ground (VIVA Q).

MN/ MX
This is an input signal to 8086.
If this signal is HIGH, 8086 is in Minimum mode i.e. Uni-Processor system. If this signal is
Low, 8086 is in Maximum mode i.e. Multiprocessor system.
NMI
This is a non-maskable, edge triggered, high priority interrupt.
On receiving an interrupt on NMI line, the µP executes INT 2 i.e. and takes control to
location 2 x 4 = 00008H in the Interrupt Vector Table (IVT), to get the value for CS ad IP.

INTR
This is a maskable, level triggered, low priority interrupt.
On receiving an interrupt on INTR line, the µP executes 2 INTA cycles.
On FIRST INTA pulse, the interrupting device (8259) prepares to send a vector number “N”.

On SECOND INTA pulse, the interrupting device (8259 PIC) sends vector number “N” to µP.
Now µP will multiply N x 4 and go to the IVT to obtain the ISR address i.e. values for IP and
CS.

RD
It is an active low output signal. When it is low 8086 reads from memory or IO.

VCC and GND

Used for power supply. Two grounds are due to the two internal layers in µP.

AD15 - AD0
It carries A15 - A0 (address) during T1 of a Machine Cycle when ALE = 1.
It carries D15 - D0 (data) for remaining T-States of a Machine Cycle when ALE = 0.

A16/S3 - A19/S6
These lines carry (A16 … A19) during T1 of every M/C Cycle. T2 onwards these lines carry
the Status signals S3 … S6.
S3 and S4 indicate the memory segment currently accessed. S5 gives the status of the
Interrupt Enable Flag. S6 goes low when 8086 controls the system bus.

BHE /S7

It carries BHE during T1. BHE is used to enable the higher bank.
T2 onwards it carries S7, which is reserved for "further development".
MIN Mode / Max Mode Signals (10m question --- Important)

HOLD --- RQ 0/ GT 0
In Minimum Mode this line carries the HOLD input signal.
The DMA Controller issues the HOLD signal to request for the system bus.
In response 8086 completes the current bus cycle and releases the system bus.
In Maximum Mode it carries the bi-directional RQ 0/ GT 0 signal (Request/Grant).The
external bus master (eg: 8087) sends an active low pulse to request for the sys bus.
In response the 8086 completes the current bus cycle, releases the system bus and sends
an active low Grant pulse on the same line to the external bus controller.
8086 gets back the system bus only after external bus master sends an active low release
pulse on the same line.

HLDA --- RQ 1/ GT 1
In Minimum Mode this line carries the HLDA signal.
This signal is issued by 8086 after releasing the system bus.
In Maximum Mode it functions as RQ 1/ GT 1, which is the same as RQ 0/ GT 0 but is of
lower priority.

WR --- LOCK

In Minimum Mode this line carries the WR signal.

It is used with M/ IO to write to Memory or IO Device.

In Maximum Mode it functions as the LOCK output line.

When this signal is active (i.e. low) the external bus master cannot take control of the system
bus. It is activated when 8086 executes an instruction with the LOCK prefix, and remains
active till next instruction.

LOCK Prefix: Normally a bus request is serviced after the current machine cycle and an
interrupt request is serviced after the current instruction cycle.
But if we write LOCK prefix before any instruction, then even if there is a bus request, the
bus will be released only after the current instruction. Hence the bus is said to be locked
during the instruction.

µP will maintain LOCK signal low throughout the instruction to indicate that it is performing
an instruction with LOCK prefix. LOCK signal is given to 8289 Bus Arbiter in Loosely
Coupled Systems, to prevent 8289 from releasing the system bus to other bus masters
DEN --- S0

In Minimum Mode it carries the DEN signal

It is used to enable the data transceivers (bi-directional buffers - IC 8286).
In Maximum Mode it carries the S0 signal.
In Maximum Mode, Bus Controller (IC 8288) gives the DEN signal.

DT/ R --- S1

In Minimum Mode it carries the DT/ R signal

This signal goes low for a Read operation and high for a write operation.
In Maximum Mode it carries the S1 signal.

In Maximum Mode, Bus Controller gives the DT/ R signal.

DEN DT/ R Action

1 X Transreceiver is disabled

0 0 Receive data

0 1 Transmit data

M/ IO --- S2

In Minimum Mode it carries the M/ IO signal, to distinguish between Memory and IO access.

In Maximum Mode it carries the S2 signal.

In Maximum Mode S2 , S1 and S0 are used to generate the appropriate control signal.

M/ IO’ RD WR Action

1 0 1 Memory Read

1 1 0 Memory Write

0 0 1 I/O Read

0 1 0 I/O Write
 ALE --- QS0
In Minimum Mode it carries the ALE signal, which is used to latch the address.
In Maximum Mode it carries the QS0 signal.
It is used with QS1 to indicate the Instruction Queue Status.
In Maximum Mode, Bus Controller gives the ALE signal.

INTA --- QS1

In Minimum Mode it carries the INTA signal

It is issued in response to an interrupt on the INTR line.
It is used to read the vector number form the interrupting device.
In Maximum Mode it carries the QS1 signal.
In Maximum Mode, Bus Controller gives the INTA’ signal.

As shown above there are two INTA cycles.

Each INTA cycle is of 4 T-states

In the 1st INTA cycle, the interrupting device (8259) starts preparing the vector
number “N”.
In the 2nd INTA cycle, 8259 sends the vector number (Type Number) “N”, to the
microprocessor, through the multiplexed address data bus.
The microprocessor then multiplies the number by 4 and goes to the corresponding
location in the IVT (Interrupt Vector Table).
From there it obtains the values of Segment Address and Offset Address for the ISR
of the corresponding interrupt, and hence executes the ISR.
LOCK signal is held low between the two INTA cycles, so that the bus is not
released in between this process.
Q7) Explain Addressing modes of 8086
Ans.:
ADDRESSING MODES FOR DATA MEMORY {IMP}

IMMEDIATE ADDRESSING MODE

In this mode the operand is specified in the instruction itself. Instructions are longer but the
operands are easily identified.

Eg: MOV CL, 12H ; Moves 12 immediately into CL register

MOV BX, 1234H ; Moves 1234 immediately into BX register

REGISTER ADDRESSING MODE

In this mode operands are specified using registers.
Instructions are shorter but operands cant be identified by looking at the instruction.

Eg: MOV CL, DL ; Moves data of DL register into CL register

MOV AX, BX ; Moves data of BX register into AX register

DIRECT ADDRESSING MODE

In this mode address of the operand is directly specified in the instruction.
Here only the offset address is specified, the segment being indicated by the instruction.

Eg: MOV CL, [4321H] ; Moves data from location 4321H in the data
; segment into CL
; The physical address is calculated as
; DS * 10H + 4321
; Assume DS = 5000H
; P A= 50000 + 4321 = 54321H
; CL [54321H]
Eg: MOV CX, [4320H] ; Moves data from location 4320H and 4321H
; in the data segment into CL and CH resp.

INDIRECT ADDRESSING MODES

REGISTER INDIRECT ADDRESSING MODE

In this mode the µP uses any of the 2 base registers BP, BX or any of the two index registers
SI, DI to provide the offset address for the data byte.

The segment is indicated by the Base Registers: BX -- Data Segment, BP --- Stack Segment

Eg: MOV CL, [BX] ; Moves a byte from the address pointed by BX in Data
; Segment into CL.
; Physical Address calculated as DS * 10H + BX
Eg: MOV [BP], CL ; Moves a byte from CL into the location pointed by BP in
; Stack Segment.
; Physical Address calculated as SS * 10H + BP
REGISTER RELATIVE ADDRESSING MODE

In this mode the operand address is calculated using one of the base registers and a 8-bit or
a 16-bit displacement.

Eg:MOV CL, [BX+4] ; Moves a byte from the address pointed by BX+4 in
; Data Seg to CL.
; Physical Address: DS * 10H + BX + 4H

Eg:MOV 12H [BP], CL ; Moves a byte from CL to location pointed by BP+12H in

; the Stack Seg.
; Physical Address: SS * 10H + BP + 12H

BASE INDEXED ADDRESSING MODE

Here, operand address is calculated as Base register plus an Index register.

Eg: MOV CL, [BX+SI] ; Moves a byte from the address pointed by BX+SI
; in Data Segment to CL.
; Physical Address: DS * 10H + BX + SI
Eg: MOV [BP+DI], CL ; Moves a byte from CL into the address pointed by
; BP+DI in Stack Segment.
; Physical Address: SS * 10H + BP + DI

BASE RELATIVE PLUS INDEX ADDRESSING MODE

In this mode the address of the operand is calculated as Base register plus Index register
plus 8-bit or 16-bit displacement.

Eg:MOV CL, [BX+DI+20] ; Moves a byte from the address pointed by

; BX+SI+20H in Data Segment to CL.
; Physical Address: DS * 10H + BX + SI+ 20H

Eg:MOV [BP+SI+2000], CL ; Moves a byte from CL into the location pointed by

; BP+SI+2000H in Stack Segment.
; Physical Address: SS * 10H + BP+SI+2000H

I​ MPLIED ADDRESSING MODE

In this addressing mode the operands are implied and are hence not specified in the
instruction.
Eg: STC ; Sets the Carry Flag.
Eg: CLD ; Clears the Direction Flag.
Important points for understanding addressing modes…

Anything given in square brackets will be an Offset Address also called Effective Address.

MOV instruction by default operates on the Data Segment; unless specified otherwise.

BX and BP are called Base Registers.

BX holds Offset Address for Data Segment. BP holds Offset Address for Stack Segment.

SI and DI are called Index Registers

The Segment to be operated is decided by the Base Register and NOT by the Index
Register.

ADDRESSING MODES FOR PROGRAM MEMORY

(optional --- to be written only if asked)

This addressing mode is required for instructions that cause a branch in the program. If the
Branch is within the same segment, it is called as an Intra-Segment Branch or a Near
Branch. If the Branch is in a different segment, it is called as an Inter-Segment Branch or a
Far Branch.

INTRA SEGMENT DIRECT ADDRESSING MODE

Address is specified directly in the instruction as an 8-bit (or 16-bit) displacement.
The effective address is thus calculated by adding the displacement to current value of IP.
As it is intra-segment, ONLY IP changes, CS does not change.
If the displacement is 8-bit it is called as a Short Branch.
This addressing mode is also called as relative addressing mode.
Eg: Code SEGMENT
.
.
Prev: ………
.
.
Current: JMP Prev ; IP Offset address of “Prev”
.
.
Code ENDS

Or

Code SEGMENT
.
.
Current: JMP Next .
.
.
Next: …………
.
.
Code ENDS
IP Offset address of “Next”

INTER SEGMENT DIRECT ADDRESSING MODE

The new Branch location is specified directly in the instruction

Both CS and IP get new values, as this is an inter-segment branch.
Eg:
Code_1 SEGMENT
.
.
.
.
Current: JMP NextSeg ; CS Segment address of “NextSeg”
; IP Offset address of “NextSeg”
.
.
.

Code_1 ENDS

Code_2 SEGMENT
.
.
.
.
NextSeg: …………
.
.
.
.
Code_2 ENDS

INTRA SEGMENT INDIRECT ADDRESSING MODE

Address is specified indirectly through a register or a memory location (in DS only). The
value in the IP is replaced with the new value.
As it is intra-segment, ONLY IP changes, CS does not change.

Eg: JMP WORD PTR [BX] ; IP {DS:[BX], DS:[BX+1]}

INTER SEGMENT INDIRECT ADDRESSING MODE

The new Branch location is specified indirectly through a register or a memory location (in
DS only).
Both CS and IP get new values, as this is an inter-segment branch.

Eg: JMP DWORD PTR [BX] ; IP {DS:[BX], DS:[BX+1]},

; CS {DS:[BX+2], DS:[BX+3]}

ADDRESSING MODES FOR STACK MEMORY (optional, to be written only if asked)

REGISTER ADDRESSING MODE
Here the operands are specified in registers (ONLY 16-bit registers).

EG: PUSH BX; Transfers BH at location pointed by SP-1 and BL at location

; pointed by SP-2 in the Stack segment. Also SP SP - 2.

REGISTER INDIRECT ADDRESSING MODE

Here the address of the operand is specified in the registers.

Eg: PUSH [BX] ; Transfers a word from location pointed by BX and BX+1 in
; data segment to SP-1 and SP-2 in Stack Segment.

​ lag Addressing Mode

F
Here the contents of Flag register are transferred to and from the Stack.

Eg: PUSHF ; Transfers higher byte of Flag register to SP-1

; and lower byte to SP-2 in the Stack Segment.

​ egment Register Addressing Mode

S
Here the segment registers (except CS) are transferred to and from the Stack.

Eg: PUSH DS ; Transfers higher byte of DS register to location

; SP - 1 and lower byte to SP-2 in the Stack Segment.

Software Model, also called Programmers model, Means all the registers available to
the programmer.
Q8) Compare JMP and CALL instructions

Q9) Compare Procedure and Macro

Q10) Explain the string instructions of 8086

● A String is a series of bytes stored sequentially in the memory. String Instructions

operate on such "Strings".
● The Source String is at a location pointed by SI in the Data Segment.
● The Destination String is at a location pointed by DI in the Extra Segment.
● The Count for String operations is always given by CX.
● Since CX is a 16-bit register we can transfer max 64 KB using a string instruction.
● SI and/or DI are incremented/decremented after each operation depending upon the
direction flag “DF” in the flag register.
● If DF = 0, it is auto increment. This is done by CLD instruction. If DF = 1, it is auto
decrement. This is done by STD instruction.

​MOVS: MOVSB/MOVSW (Move String)

It is used to transfer a word/byte from data segment to extra segment. The offset of the
source in data segment is in SI.
The offset of the destination in extra segment is in DI.
SI and DI are incremented / decremented depending upon the direction flag.

Eg: MOVSB ; ES:[DI] DS:[SI] … byte transfer

; SI SI ± 1 … depending upon DF
; DI DI ± 1 … depending upon DF

MOVSW ; {ES:[DI], ES:[DI + 1]} {DS:[SI], DS:[SI + 1]}

; SI SI ± 2
; DI DI ± 2

​LODS: LODSB/LODSW (Load String)

It is used to Load AL (or AX) register with a byte (or word) from data segment. The offset of
the source in data segment is in SI.
SI is incremented / decremented depending upon the direction flag (DF).

Eg: LODSB ; AL DS:[SI] … byte transfer

; SI SI ± 1 … depending upon DF
LODSW ; AL DS:[SI]; AH DS:[SI + 1]
; SI SI ± 2

​STOS: STOSB/STOSW (Store String)

It is used to Store AL (or AX) into a byte (or word) in the extra segment. The offset of the
source in extra segment is in DI.
DI is incremented / decremented depending upon the direction flag (DF).
Eg: STOSB ; ES:[DI] AL … byte transfer
; DI DI ± 1 … depending upon DF
STOSW ; ES:[DI] AL; ES:[DI+1] AH … word transfer
; DI DI ± 2 … depending upon DF

​CMPS: CPMSB/CMPSW (Compare String)

It is used to compare a byte (or word) in the data segment with a byte (or word) in the extra
segment.
The offset of the byte (or word) in data segment is in SI. The offset of the byte (or word) in
extra segment is in DI.
SI and DI are incremented / decremented depending upon the direction flag.
Comparison is done by subtracting the byte (or word) from extra segment from the byte (or
word) from Data segment.
The Flag bits are affected, but the result is not stored anywhere.

Eg :CMPSB ; Compare DS:[SI] with ES:[DI] … byte operation

; SI SI ± 1 … depending upon DF
; DI DI ± 1 … depending upon DF

CMPSW ; Compare {DS:[SI], DS:[SI+1]}

; with {ES:[DI], ES:[DI+1]}
; SI SI ± 2 … depending upon DF
; DI DI ± 2 … depending upon DF

​SCAS: SCASB/SCASW (Scan String)

It is used to compare the contents of AL (or AX) with a byte (or word) in the extra segment.
The offset of the byte (or word) in extra segment is in DI.
DI is incremented / decremented depending upon the direction flag (DF). Comparison is
done by subtracting a byte (or word) from extra segment from AL (or AX). The Flag bits are
affected, but the result is not stored anywhere.

Eg: SCASB ; Compare AL with ES:[DI] … byte operation

; DI DI ± 1 … depending upon DF

SCASW ; Compare {AX} with {ES:[DI], ES:[DI+1]}

; DI DI ± 1 … depending upon DF
 ● REP​ ​(Repeat prefix used for string instructions)

This is an instruction prefix, which can be used in string instructions. It can be used with
string instructions only.
It causes the instruction to be repeated CX number of times.
After each execution, the SI and DI registers are incremented/decremented based on the DF
(Direction Flag ) in the Flag register and CX is decremented.
i.e. DF = 1; SI, DI decrements. .

Thus, it is important that before we use the REP instruction prefix the following steps must
be carried out:
CX must be initialized to the Count value. If auto decrementing is required, DF must be set
using STD instruction else cleared using CLD instruction.

EG: MOV CX, 0023H CLD

REP MOVSB

The above section of a program will cause the following string operation
ES:[DI] DS:[SI], SI SI + 1, DI DI + 1, CX CX – 1
to be executed 23H times (as CX = 23H) in auto incrementing mode (as DF is cleared).

REPZ/REPE (Repeat on Zero/Equal)

It is a conditional repeat instruction prefix.It behaves the same as a REP instruction provided
the Zero Flag is set (i.e. ZF = 1).It is used with CMPS instruction.

REPNZ/REPNE (Repeat on No Zero/Not Equal)

It is a conditional repeat instruction prefix.It behaves the same as a REP instruction provided
the Zero Flag is reset (i.e. ZF = 0).It is used with SCAS instruction.

Please Note: 8086 instruction set has only 3 instruction prefixes :

ESC (to identify 8087 instructions)
LOCK (to lock the system bus during an instruction)
REP (to repeatedly execute string instructions)
Q11) Explain Instruction Format for 8086

Instructions in 8086 can be of size 1 byte to 6 bytes. The distribution of the bytes is as
follows
Opcode Byte
The first byte is called the “opcode byte”.
It has a 6-bit opcode that indicates the operation to be performed. It has two more bits “d”
and “w”

d: direction
1 = data moves from operand specified by r/m to operand specified by reg. 0 = data moves
from operand specified by reg to operand specified by r/m.

w: word/ byte
1: data is a word: 16-bits 0: data is a byte: 8-bits

Addressing Mode Byte

mod (2 bits):
These are called “mode” bits. They decide how r/m is interpreted.
00: r/m is a memory operand, but no displacement 01: r/m is a memory operand, with 8-bit
displacement
10: r/m is a memory operand, with 16-bit displacement 11: r/m is a register operand

reg (3 bits):
This specifies the register used as the first operand, which may act as source or destination
depending upon the “d”(direction) bit
r/m (3 bits):
This specifies the second operand which may either be a register or a memory location
depending upon the “mod” bits.
Q12) Explain Assembler Directives of 8086

Assembly language has 2 types of statements:

Executable: Instructions that are translated into Machine Code by the assembler.

Assembler Directives:
Statements that direct the assembler to do some special task. No M/C language code is
produced for these statements.
Their main task is to inform the assembler about the start/end of a segment, procedure or
program, to reserve appropriate space for data storage etc.
Some of the assembler directives are listed below

DB (Define Byte) ; Used to define a Byte type variable.

Eg: SUM DB 0; Assembler reserves 1 Byte of memory for the variable
; named SUM and initialize it to 0.

DW (Define Word) ; Used to define a Word type variable (2 Bytes).

DD (Double Word) ; Used to define a Double Word type variable (4 Bytes).

DQ (Quad Word) ; Used to define a Quad Word type variable (8 Bytes).

DT (Ten Bytes) ; Used to define 10 Bytes to a variable (10 Bytes).

DUP() ; Copies the contents of the bracket followed by this

; keyword into the memory location specified before it.
Eg: LIST DB 10 DUP (0) ; Stores LIST as a series of 10 bytes initialized to Zero.

SEGMENT ; Used to indicate the beginning of a segment.

ENDS ; Used to indicate the end of a segment.

ASSUME ; Associates a logical segment with a processor segment.

Eg: Assume CS:Code ; Makes the segment "Code" the actual Code Segment.

PROC ; Used to indicate the beginning of a procedure.

ENDP ; Used to indicate the end of a procedure.

END ; Used to indicate the end of a program.

EQU ; Defines a constant

E.g.:: AREA EQU 25H ; Creates a constant by the name AREA with a value 25H
 EVEN / ALIGN ; Ensures that the data will be stored by the assembler in the memory
in an aligned form. Aligned data works faster as it can be accessed in One cycle. Misaligned
data, though is valid, requires two cycles to be accessed hence works slower.

OFFSET ; Can be used to tell the assembler to simply substitute the offset address
of any variable. E.g.:: MOV Si, OFFSET String1 ; SI gets the offset address of String1

Start ; It’s the label from where the microprocessor to start executing the program

Model Directives
.MODEL SMALL ; All Data Fits in one 64 KB segment.
All Code fits in one 64 KB Segment

.MODEL MEDIUM ; All Data Fits in one 64 KB segment.

Code may be greater than 64 KB

.MODEL LARGE ; Both Data and Code may be greater than 64 KB

Combined Example:

Data SEGMENT
LIST DB 10 DUP (0) ; Stores LIST as a series of 10 bytes initialized to zero …
Data ENDS

Code SEGMENT
Assume CS: Code, DS: Data ; Makes Code Code Segment
; and Data Data Segment.
Start: …
…
…

Code ENDS
END Start
Q13) Explain INT 21H (DOS Interrupt)
Ans
DOS provides various internal interrupts which are used by the system programmer. The
most commonly used interrupt is INT 21H.
It invokes inbuilt DOS functions which can be used to perform tasks such as reading a user
input char from the screen, displaying result on the screen, exiting the program etc.
While calling the INT21H Dos interrupt, we must first assign a correct value in AH register.
The value in the AH register selects the INT 21H function which is required by the user.
The most commonly used INT 21H functions are as shown:
Q13) Explain Interrupts in 8086

An interrupt is a special condition that arises during the working of a µP.

The µP services it by executing a subroutine called Interrupt Service Routine (ISR).
There are 3 sources of interrupts for 8086:

External Signal (Hardware Interrupts):

These interrupts occur as signals on the external pins of the µP. 8086 has two pins to accept
hardware interrupts, NMI and INTR.

Special instructions (Software Interrupts):

These interrupts are caused by writing the software interrupt instruction INTn where “n” can
be any value from 0 to 255 (00H to FFH).
Hence all 256 interrupts can be invoked by software.

Condition Produced by the Program (Internally Generated Interrupts):

8086 is interrupted when some special conditions occur while executing certain instructions
in the program.
Eg: An error in division automatically causes the INT 0 interrupt.

INTERRUPT VECTOR TABLE (IVT) {10M --- IMPORTANT }

The IVT contains ISR address for the 256 interrupts.

Each ISR address is stored as CS and IP.
As each ISR address is of 4 bytes (2–CS and 2-IP), each ISR address requires 4 locations
to be stored. There are 256 interrupts: INT 0 … INT 255 the total size of the IVT is 256 x 4 =
1KB.
The first 1KB of memory, address 00000 H … 003FF H, are reserved for the IVT.
Whenever an interrupt INT N occurs, µP does N x 4 to get values of IP and CS from the IVT
and hence perform the ISR.
DEDICATED INTERRUPTS (INT 0 … INT 4)

1) INT O (Divide Error)

This interrupt occurs whenever there is division error
i.e. when the result of a division is too large to be stored.
This condition normally occurs when the divisor is very small as compared to the dividend or
the divisor is zero.
Its ISR address is stored at location 0 x 4 = 00000H in the IVT.
 INT 1 (Single Step)
The µP executes this interrupt after every instruction if the TF is set.
It puts µP in Single Stepping Mode i.e. the µP pauses after executing every instruction. This
is very useful during debugging.
Its ISR generally displays contents of all registers.
Its ISR address is stored at location 1 x 4 = 00004H in the IVT.

INT 2 (Non Maskable Interrupt)

The µP executes this ISR in response to an interrupt on the NMI line. Its ISR address is
stored at location 2 x 4 = 00008H in the IVT.

INT 3 (Breakpoint Interrupt)

This interrupt is used to cause Breakpoints in the program. It is caused by writing the
instruction INT 03H or simply INT.
It is useful in debugging large programs where Single Stepping is inefficient. Its ISR is used
to display the contents of all registers on the screen.
Its ISR address is stored at location 3 x 4 = 0000CH in the IVT.

INT 4 (Overflow Interrupt)

This interrupt occurs if the Overflow Flag is set AND the µP executes the INTO instruction
(Interrupt on overflow).
It is used to detect overflow error in signed arithmetic operations. Its ISR address is stored at
location 4 x 4 = 00010H in the IVT.

Please Note: INT 0 … INT 4 are called as dedicated interrupts as these interrupts are
dedicated for the above-mentioned special conditions.

RESERVED INTERRUPTS

INT 5 … INT 31
These levels are reserved by INTEL to be used in higher processors like 80386, Pentium
etc. They are not available to the user.

User defined Interrupts

INT 32 … INT 255
These are user defined, software interrupts.
ISRs for these interrupts are written by the users to service various user defined conditions.
These interrupts are invoked by writing the instruction INT n.
Its ISR address is obtained by the µP from location n x 4 in the IVT.

HARDWARE INTERRUPTS

NMI (Non Maskable Interrupt)

This is a non-maskable, edge triggered, high priority interrupt. On receiving an interrupt on
NMI line, the µP executes INT 2.
µP obtains the ISR address from location 2 x 4 = 00008H from the IVT.
It reads 4 locations starting from this address to get the values for IP and CS, to execute the
ISR.

INTR
This is a maskable, level triggered, low priority interrupt.
On receiving an interrupt on INTR line, the µP executes 2 INTA pulses.
1st INTA pulse --- the interrupting device calculates (prepares to send) the vector number.
2nd INTA pulse --- the interrupting device sends the vector number “N” to the µP.
Now µP multiplies N x 4 and goes to the corresponding location in the IVT to obtain the ISR
address. INTR is a maskable interrupt.
It is masked by making IF = 0 by software through CLI instruction.
It is unmasked by making IF = 1 by software through STI instruction.

Response to any interrupt --- INT N

The µP will PUSH Flag register into the Stack. SS:[SP–1], SS:[SP-2] Flag
SP SP – 2
Clear IF and TF in the Flag register and thus disables INTR interrupt.
IF 0, TF 0
PUSH CS into the Stack. SS:[SP–1], SS:[SP-2] CS SP SP – 2
PUSH IP into the Stack. SS:[SP–1], SS:[SP-2] IP SP SP – 2
Load new IP from the IVT IP [N x 4], [N x 4 + 1]
Load new CS from the IVT IP [N x 4 + 2], [N x 4 + 3]

Since CS and IP get new values, control shifts to the address of the ISR and the ISR thus
begins. At the end of the ISR the P encounters the IRET instruction and returns to the main
program in the following steps.

Response to IRET instruction

The µP will restore IP from the stack

IP SS:[SP], SS:[SP+1]
SP SP + 2
The µP will restore CS from the stack
CS SS:[SP], SS:[SP+1]
SP SP + 2
The µP will restore FLAG register from the stack
Flag SS:[SP], SS:[SP+1] SP SP + 2
Priority in 8086 interrupts is of two types:
Simultaneous Occurrence:
When more than one interrupts occur simultaneously then, all s/w interrupts except single
stepping, get the highest priority.
This is followed by NMI. Next is INTR. Finally, the lowest priority is of the single stepping
interrupt.
Eg: Assume the µP is executing a DIV instruction that causes a division error and
simultaneously INTR occurs.
Here INT 0 (Division error) will be serviced first i.e. its ISR will be executed, as it has higher
priority, and then INTR will be serviced.

Ability to interrupt another ISR:

Since software interrupts (INT N) are non-maskable, they can interrupt any ISR.
NMI is also non-maskable hence it can also interrupt any ISR.
But INTR and Single stepping cannot interrupt another ISR as both are disabled before µP
enters an ISR by IF 0 and TF 0.

Eg: Assume the µP executes DIV instruction that causes a division error. So µP gets the
INT 0 interrupt and now µP enters the ISR for INT 0. During the execution of this ISR, NMI
and INTR occur.
Here µP will branch out from the ISR of INT 0 and service NMI (as NMI is non-maskable).
After completing the ISR of NMI µP will return to the ISR for INT 0.
INTR is still pending but the µP will not service INTR during the ISR of INT 0 (as IF 0).
µP will first finish the INT 0 ISR and only then service INTR. Thus INTR and Single stepping
cannot interrupt an existing ISR.
Interrupt priority Flowchart {Optional – Only for reference}
Q14) 8086 Configurations

8282 – 8-bit (Octal) Latch

8282 is an 8-bit latch.

In 8086, the address bus is multiplexed with the data bus and status bits.
8282 is used to latch the address from this bus.
The ALE signal is connected to STB of 8282.
When STB (ALE) is high, the input is latched and transferred to the output. Hence
address is latched.
When STB (ALE) is low, the input is discarded.
Hence, data is not latched. The previously latched address remains at the output.
As totally 21 bits are to be latched (A19-A0 and BHE ), 3 latches are required, each
latch being 8-bit.

8286 – 8-bit Data Trans-receiver

8286 is an 8-bit Trans-receiver.

It acts as a bi-directional buffer, and increases the driving capacity of the data bus.
It is enabled when OE is low.
T controls the direction of data. If T = 1: data is transmitted.
If T = 0: data is received.
As the data bus is 16-bits, 2 trans-receivers are required.
Its main function is to prevent address and allow data to be transferred on the data
bus.
In the 1st T-State when the bus contains address, OE is high hence the transreceiver
is disabled.

Thereafter when the bus contains data OE is low and the transreceiver is enabled. Thus it
only allows data to pass.

8284 – Clock Generator

 8284 is a Clock Generator IC.
It provides the CLOCK (CLK) signal, a train of pulses at a constant freq, to the entire
circuit.

It synchronizes the READY ( RD Y) signal which indicates that an interface is ready

for data.
It also synchronizes the RESET (RST) signal which is used to initialize the system.
There are 2 ways of providing the frequency input to 8284.
Through EFI (External Frequency Input)
A "Pulse Generator" circuit can be connected to the EFI pin, to provide an external freq.
Through X1, X2 (Oscillator Clock Inputs)
An Oscillator can be connected across the X1, X2 lines to provide constant clock signal.
In both the cases the Output Clock frequency = 1/3rd of the Input Clock frequency to
produce a 33% duty cycle required by the Microprocessor. ¾
Clock Selection is done by the F/ C pin.

F/ C = 1 Input Clock given through EFI pin.

F/ C = 0 Input Clock given through Oscillator inputs X1, X2 pins.

Q 16) Explain Minimum Mode of 8086 microprocessor

● 8086 works in Minimum Mode, when MN/ ¯MX = 1.

● Minimum Mode, 8086 is the only processor in the system. The Minimum
Mode circuit of 8086 is as shown below:
● Clock is provided by the 8284 clock generator, it provides CLK, RESET and
READY input to 8086.
● Address from the address bus is latched into 8282 8-bit latch. Three such
latches are needed, as address bus is 20-bit. The ALE of 8086 is connected
to STB of the latch. The ALE for this latch is given by 8086 itself.
● The data bus is driven through 8286 8-bit trans-receiver. Two such
trans-receivers are needed, as the data bus is 16-bit. The trans-receivers are
enabled through the DEN signal, while the direction of data is controlled by
the DT/ ¯R signal. ¯DEN is connected to ¯OE and DT/ ¯R is connected to T.
Both ¯DEN and DT/ ¯R are given by 8086 itself.

● Control signals for all operations are generated by decoding M/¯IO , ¯RD and
¯WR signals.

● M/¯IO , ¯RD and ¯WR are decoded by a 3:8 decoder like IC 74138. Bus
Request (DMA) is done using the HOLD and HLDA signals.
● ¯INTA is given by 8086, in response to an interrupt on INTR line.