Course Syllabus for CSE-424

1. Title: Digital System Design (Sessional) Course Code: CSE-424

2. Credits: 1.5 (3 hours of lab work per week) Session: 2018-19

3. Course Teacher: Dr. Asaduzzaman, Professor, Dept. of CSE, CUET

Md. Billal Hossain, Lecturer, Dept. of CSE, CUET
4. Learning Resources:
Textbook(s): Morris Mano, Charles R. Kime, Madison; Tom Martin, -- Logic and computer design
fundamentals, FIFTH EDITION (2015) Pearson
Reference:
Alan B. Marcovitz,-- Introduction to Logic Design, Third Edition, McGraw-Hill
M. Morris Mano and Michael D. Ciletti, -- Digital Design with an Introduction to the Verilog HDL
(FIFTH EDITION, 2015), Pearson
5. Catalog Description: Sessional based on the following topics:
Register transfer logic, Hardware description language, inter register transfer, bus transfer, memory transfer,
microoperations and macrooperations, design of bus systems, representation of digital data in registers and memory,
design of a simple computer. Processor organization, design of arithmetic logic unit (ALU), status register, design of
shifter, design of processor unit, design of accumulator. Control Logic Design, Control organization, Design of
hardwire and software control, Micro-program sequencer. Computer Design with a given System configuration:
Instruction set, Programming, Fetch cycle, Execution cycle, Design of computer registers, Design of control, Bus
buffer and memory cycle of microcomputers. Design of memory subsystem using SRAM and DRAM. Design of
various I/O devices and systems. Design special purpose controllers

6. Prerequisite(s): CSE-121, CSE-122 and CSE-321

7. Course Designation as Elective or Required: Required

8. Course Objectives:
(a) Familiarization with the Digital System Design tools (VHDL, Xiling, etc.) and hardware equipment
(b) Introduce the concept of various component design and use them to design a digital computer
(c) Design and analyze a complete digital system by combining various components

9. Student Learning Outcomes: After successfully completing the course with a grade of D (2.0/4.0) or
better, the student should be able to do the following

No Course Outcomes (COs)

.
1 Analyze the design principle of a digital system to decompose the whole system in
various modules using modular approach
2 Design various Modules of a digital computer such as Adder, Arithmetic unit, ALU
memory, processor, etc.
3 Implement and Analyze the design components using modern design tool (VHDL) and
 traditional hardware based system
10. Mapping of Program Outcomes Addressed by COs
CO-PO mapping
CO# Program Outcome (PO) PO#
1 Problem analysis: Identify, formulate, research literature and analyse 2
complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences and engineering sciences.
2 Design/Development of solutions: Design solutions for complex engineering 3
problems and design systems, components or processes that meet specified
needs with appropriate consideration for public health and safety, cultural,
societal, and environmental considerations.

3 Modern tool usage: Create, select and apply appropriate techniques, 5

resources, and modern engineering and IT tools, including prediction and
modelling, to complex engineering problems, with an understanding of the
limitations.

CO—PO—WP—WA Mapping

Complex Engineering Activities

Complex Engineering Problem Solving
Programs Outcomes (PO)
Engineering Knowledge

Life-long Learning
Problem Analysis

Design

Modern Tools

Ethics

Teamwork

Project Management and Finance

Engineers and Society

Environment and sustainability

Investigation

Communication
No Title of Course
.

1. CSE-423: Digital System × × × ×

Design (Theory)

2. CSE-424: Digital System × × × ×

Design (Sessional)
 1
NO
(Sessional) CSE-424: Digital System Design COURSE CODE & TITLE

C3, C4, A3, P3 BLOOM`S TAXONOMY LEVEL

2, 3, 5
POs
ENGINEERING FUNDAMENTAL WK3

SPECIALIST KNOWLEDGE WK4

WP1

ENGINEERING DESIGN WK5

X X X X
Depth of knowledge

ENGINEERING PRACTICE WK6

RESEARCH LITERATURE WK8

RANGE OF CONFLICTING REQUIREMENTS WP2

X
DEPTH OF ANALYSIS REQUIRED WP3

FAMILIARITY OF ISSUES WP4

EXTENSIVE APPLICABLE CODES WP5

COMPLEX PROBLEM SOLVING

CONFLICTING REQUIREMENTS STAKEHOLDERS INVOLVEMENT & WP6

X
INTERDEPENDENCE WP7

RANGE OF RESOURCES EA1

LEVEL OF INTERACTIONS EA2

INNOVATIONS EA3
COMPLEX

ENVIRONMENT CONSEQUENCES TO SOCIETY & EA4

ACTIVITIES

FAMILIARITY OF ISSUES EA5

NATURAL SCIENCES WK1 PO1

MATHEMATICS WK2

ENGINEERING FUNDAMENTAL WK3

Mapping of Complex engineering problem/ complex activities/knowledge profile 

SPECIALIST KNOWLEDGE WK4

NATURAL SCIENCES WK1 PO2

MATHEMATICS WK2

ENGINEERING FUNDAMENTAL WK3

SPECIALIST KNOWLEDGE WK4

X X X

ENGINEERING DESIGN WK5 PO3

KNOWLEDGE PROFILE

RESEARCH LITERATURE WK8 PO4

X

ENGINEERING PRACTICE WK6 PO5

COMPREHENSION WK7 PO6

COMPREHENSION WK7 PO7

COMPREHENSION WK7 PO8

 11. Assessment Strategy:
Course Complex
Program Knowledge Complex Engineering
Possible tasks Outcomes Engineering
Outcomes (PO) Profile (WK)) Problem (WP)
(CO) Activities (EA)

T-1: Decompose the whole design problem into sub problems

WP1: Depth of
using modular approach considering multiple solutions
PO2: Knowledge
WK3
CO-1 Problem
WK4
T-2: Identify the specific requirements and constraints Analysis
involved in designing each of the modules or sub problems

N/A
PO3: Design/ WP3: Depth of
T-3: Design various Modules of a digital computer such as Adder, Analysis Required
CO-2 Development WK5
Arithmetic unit, ALU memory, processor, etc.
Solutions
PO5:
T-4: Use of modern tool in analysis and design of
CO-4 Use of Modern WK6 WP7: Interdependence
components
Tools:
Mapping of Tasks with POs, WPs, WKs and EA
 ASSESSMENT RUBRIC:
Tas Assessment
k Criteria Tools Exceptional Acceptable Marginal Unacceptable
No.
Draw the block Report Complete diagram of the Complete diagram of the Complete diagram of the
Complete diagram of the
diagram and Quiz system with valid logical system with valid logical system with valid logical
T-1 system with invalid
logic diagram reasoning that uses minimum reasoning that uses an reasoning that uses a lot of
logical reasoning
of the system number of components acceptable level of redundancy redundancy
Report & Explore limited Explore limited
Use of Explore available alternatives
Quiz Explore limited alternatives and alternatives and select alternatives and select
T-2 appropriate and select appropriate
select appropriate components complex components still inappropriate
components components
serving the purpose components
Report No Effective use of system No Effective use of
Use of formal Effective use of system Reasonable use of system
design principles still system design principles
T-3 design design principles ensuring the design principles ensuring the
meeting the desired and fails to ensure the
procedure desired objectives desired objectives
objectives desired objectives
Report & Standard software tools Standard software tools Minimal application and Inappropriate application
Analyze the
Lab are used effectively to are used with moderate use of Standard software and use of Standard
T-4 design using of
Performance develop and analyze the effectiveness to tools software tools
software Tools
designs develop and analyze the designs
 Lesson Plan

` Topic Lesson Learning Outcomes and corresponding CO Corresponding Assessment Method

(at the end of the lesson students will be able to …) COs

Week-01 Introduction to the  Lab orientation with safety instructions NA NA

Digital System Design  Identify various devices and equipment of Digital System Design
Lab Lab
 Install and use of VHDL software

Week -02 Introduction to VHDL  Use VHSIC (very high speed integrated circuit) hardware NA  Lab Report
description language (VHDL) to design digital system
 Explain VHDL language concept and design methodology

Week -03 Implementation of Full  Compare three different VHDL design methodology 3  Lab Report
Adder and parallel adder  Use the concept of modular approach in practical design  Lab Performance
Circuit in Dataflow,  Simulate the design using ‘testbench’ to verify the input output (Individual)
Behavioral & Structural relations
Design Process in VHDL

Week -04 Implementation of  Compare the design requirements of combinational and 3  Lab Report
Different Sequential sequential circuit  Lab Performance
Circuits in VHDL  Simulate the design using ‘testbench’ to verify the input output (Individual)
relations

Week -05 Implementation of a 4-bit  Realize synchronization among various components of a complex 3  Lab Report
Register and counter in system  Lab Performance
VHDL  Interconnect various time dependent components. (Individual)
 Simulate the design using ‘testbench’ to verify the input output
relations
Week -06 Implementation of  Draw the block diagram/Logic diagram representation of the 1&2  Lab Report
register transfer hardware  Lab Performance
statements in hardware  Identify appropriate LSI or MSI ICs for each block (Team)
 Implement the design and analyze its operation.

Week -07 Design and  Use systematic design procedure to design an Arithmetic Circuit 1, 2 & 3  Lab Report
Implementation of an 4- with given set of operation  Lab Performance
bit Arithmetic Circuit  Identify appropriate components (LSI or MSI ICs) for each block (Team)
of the design
 Implement the design in hardware as well as in VHDL and
analyze its operation

Week -08 Design and  Use systematic design procedure to design an ALU with given 1, 2 & 3  Lab Report
Implementation of an set of operation  Lab Performance
Arithmetic Logic Unit  Identify appropriate VHDL design method (Team)
(ALU) in VHDL  Implement the design in VHDL and analyze & synthesis the
design for optimization

Week -09 Design and  Use systematic design procedure to reduce the number of clock 1, 2 & 3  Lab Report
Implementation of a 4-bit pulse with given set of operation  Lab Performance
Combinational Shift Unit  Identify appropriate components (LSI or MSI ICs) for each block (Team)
of the design
 Implement the design in hardware as well as in VHDL and
analyze its operation

Week -10 Performance test  Individually solve open-ended hardware design problem using 1, 2 & 3  Lab Performance
VHDL (Individual)

Week -11 Viva-voce NA  Individual

Week -12 Quiz NA  Individual Test