Digital Logic & Processors

LAB MANUAL

Course code: 20 EC 1101

For
I Semester / I Year

Of
B.Tech.
CSE, ECSE, ECE, EEE

KL UNIVERSITY
VADDESWARAM, GUNTUR – 522 502 (A.P.) INDIA

2020-21

1
 DIGITAL LOGIC & PROCESSORS [ 19EC1101]

LIST OF EXPERIMENTS
Exp. NAME OF THE EXPERIMENTS Lab Type
No.
1 Introduction to Digital Electronics Lab and Logisim IN Lab
2 Realization of logic functions using TTL IC’s IN Lab
3 IN Lab
LED Control Using Universal Gates a) Using NAND Gate b) Using
NOR Gate
4 IN Lab
Introduction to verilog code
5 Design and verify given SOP and POS logic functions. F (x, y, z) = IN Lab
Σm (3, 5, 6, 7) and F (x, y, z) = πM (0, 1, 2, 4) and write Verilog HDL
to develop optimized hardware.
6 Design logic circuit of 2-bit magnitude comparator and 4-bit parity IN Lab
generator and write Verilog HDL to develop optimized hardware.
7 Design logic circuit for 4-bit Binary to Gray and 1–bit memory IN Lab
element and write Verilog HDL to develop optimized hardware.
8 Design Full-Adder using Multiplexer and Decoder and write Verilog IN Lab
HDL to develop optimized hardware.
9 IN Lab
Digital Display of the Department Name using 7-segment decoder
10 Design logic circuits of 3-bit shift registers using D flip-flops and write IN Lab
Verilog HDL to develop optimized hardware.
11 Design logic circuit of 3-bit Up-down counter using JK flip-flops and IN Lab
write Verilog HDL to develop optimized hardware.
12 Design PROM, PAL, PLA and LUT logic blocks for given Boolean IN Lab
functions S=A’B+AB’ and C=A’B and write Verilog HDL to develop
optimized hardware.
13 Design Half Adder CPLD-Macrocell and FPGA-CLB and write IN Lab
Verilog HDL to develop optimized hardware.

Signature of Course Coordinator Head of the Department

2
 LAB Evaluation Pattern

Internal and External Lab Evaluation Process:

Evaluation Weightage/marks Date Duration

Component (Hours)

Weightage (15%)

Max Marks (100)

Internal Lab 90 mts
Experiment

Weightage (15%)
SE Lab Exam 90 mts

Max Marks (100)

Experiment wise Evaluation:

Expt No. Date Aim / or Objective MARKS

Record (5M) Results/ Inference VivaVoce Total Signature

& & (5M) marks of Faculty
Graphs Analysis (20M) with date
(5M) (5M)

Total
NOTE: Teacher must maintain the same format in the attendance register of the said lab course

3
Note: In observation/Record book student must maintain this evaluation page.

4
Course Team members and Chamber Venue details
Chamber
Chamber Chamber
Consultation Signature of
S.No. Name of Faculty Consultatio Consultation
Timings for each Course faculty
n Day (s) Room No:
Day
1

10

11

12

13

14

15

16

17

18

5
6
Project Ideas

Sl.No Title of the Project

1 Design and implementation of a Totally Self-checking Circuit for Berger codes
2 Design and implementation of a Serial to parallel converter
3 Design and implementation of a 1 out of 8 detector.
4 Design and implementation of a Booth Algorithm
5 Design a car security system
6 Design and implementation of a Multiplier carry slave array
7 Design and Implement a vending Machine
8 Design and implementation of ALU
9 Design of Car Parking system
10 Transmit a given sequence through encoder and decode the same
11 Design and implement a 3 stage BILBO
12 Design and implementation a traffic light controller
13 LFSR for circuit fault testing and function verification
14 SDR and DDR data transfer system
15 Design a module that measure the period of any periodic signal
16 Fault diagnosis of VLSI circuits using FPGA
17 Design and implementation of a an unsigned 8-bit greater or equal comparator

18 Design and implementation of a 8-bit subtractor

19 Design and implementation of Random Counter
20 Design and implementation of a sequence detector
21 Design and implementation of XC4000 CLB
22 Diagnosis of Hazards in digital circuits using FPGA
23 Design and implementation of 3x3 binary multiplier with reduced number of gates

24 Design and synthesize a BCD to 7 Segment decoder circuit for driving a 7- Segment LED display

25 Design a dedicated data path for counting 0’s and 1’s

26 Design and implementation of 4-bit BCD adder
27 Home security sytem

7
 EXPERIMENT 1

Introduction to Digital Electronics Lab and Logisim:

Aim:- To study and familiarization of Logisim tool for digital electronics lab.

Required software’s or tools: -

Step 1: Install the Java 5 software:

Step 2: Install Logisim tool, it runs on any machine supporting Java 5 or later

8
Explanation of Logisim tool:

1. After successful installation of Logisim tool, we can see below window

1 2

Figure 1: The Logisim tool box view

The above figure 1 is described as follows

Point 1:- Is the basic tool bar.

Point 2:- Is the Digital electronic components block
Point 3:- Is the Component properties editor block.
Point 4:- Is the canvas for designing and simulating circuits.

The detailed explanation about each and every block and their usage of Logisim has been discussed in subsequent
experiments.

Results:

EXPERIMENT 2

REALIZATION OF LOGIC FUNCTIONS USING TTL IC’s

9
Aim: To Study and Verify the Logic Gates Using TTL IC’s

The required software’s or tools: Logisim software, Usage of Gates components

Theory: Logic gates are electronic circuits which perform logical functions on one or more inputs
to produce one output. There are seven logic gates. When all the input combinations of a logic
gate are written in a series and their corresponding outputs written along them, then this input/
output combination is called Truth Table.

Various gates and their working is explained as,

AND Gate
AND gate produces an output as 1, when all its inputs are 1; otherwise the output is 0. This gate
can have minimum 2 inputs but output is always one. Its output is 0 when any input is 0.

10
OR Gate
OR gate produces an output as 1, when any or all its inputs are 1; otherwise the output is 0. This
gate can have minimum 2 inputs but output is always one. Its output is 0 when all input are 0.

NOT Gate
NOT gate produces the complement of its input. This gate is also called an INVERTER. It always
has one input and one output. Its output is 0 when input is 1 and output is 1 when input is 0.

11
NAND Gate
NAND gate is actually a series of AND gate with NOT gate. If we connect the output of an AND
gate to the input of a NOT gate, this combination will work as NOT-AND or NAND gate. Its
output is 1 when any or all inputs are 0, otherwise output is 1.

NOR Gate
NOR gate is actually a series of OR gate with NOT gate. If we connect the output of an OR gate
to the input of a NOT gate, this combination will work as NOT-OR or NOR gate. Its output is 0
when any or all inputs are 1, otherwise output is 1.

12
13
Exclusive OR (X-OR) Gate

X-OR gate produces an output as 1, when number of 1’s at its inputs is odd, otherwise output is
0. It has two inputs and one output.

Exclusive NOR (X-NOR) Gate

X-NOR gate produces an output as 1, when number of 1’s at its inputs is not odd, otherwise
output is 0. It has two inputs and one output.

14
 Procedure:

1. Install the Logisim software as explained in Experiment 1.

2. Connect the inputs to the any one logic gate by clicking on the symbol on Logisim tool bar.
3. Connect the output to any logic gate by clicking on the symbol on Logisim tool bar

4. Apply various input combinations by selecting the symbol on Logisim tool bar and observe the
output by changing the inputs using the hand symbol.
5. Verify the truth table for each input/ output combination.
6. Repeat the process for all other logic gates.
Result:Verified the Logic Gates using TTL IC’s

EXPERIMENT – 3
15
 LED CONTROL USING UNIVERSAL GATES

AIM: To control given LED sequence using NAND and NOR gates

Apparatus: - Logisim software, Universal Gate components, LED.

Theory:

The use of AND, OR, and NOT gates in the synthesis of logic circuits. There are other basic logic functions that
are also used for this purpose. Particularly useful are the NAND and NOR functions which are obtained by
complementing the output generated by AND and OR operations, respectively. These functions are attractive
because they are implemented with simpler electronic circuits than the AND and OR functions.

Therefore, the NAND and NOR gates are known as universal logic gates. We can implement any logic by using
these universal logic gates. A logic circuit is designed to control LED’s using NAND and NOR logic gates.
The control of LEDs can be controlled according to our wish. The LEDs have to control according to the given
truth table.

Truth Table 1: -

16
 A B LED1 LED2
0 0 1 0
0 1 0 1
1 0 0 0
1 1 1 1

Circuit Implementation Using NAND Gate:

Figure 1: Logisim design using NAND gates for truth table 1

17
Circuit Implementation Using NOR Gate:

Figure 2: Logisim design using NOR gates for truth table 1

Procedure:

a) Make connections as per Figure 1 and 2 for NAND and NOR circuit implementation using Logisim.

b) By applying the inputs, the LED outputs needs to observe and the operation is verified with the
help of truth table.

Precautions:
1. Connections must be given properly.

Result:
1. Understand the concept of universal gates
2. Identify the replacement of universal gates instead of basic gates
3. LED on and off controlling using universal gates

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 EXPERIMENT 4 & 5

Introduction to verilog code. Design and verify given SOP and POS logic functions. F (x,
y, z) = Σm (3, 5, 6, 7) and F (x, y, z) = πM (0, 1, 2, 4) and write Verilog HDL to develop
optimized hardware.

Aim: To design and verify given SOP and POS logic functions. F (x, y, z) = Σm (3, 5, 6, 7) and F (x, y, z) =
πM (0, 1, 2, 4) and write Verilog HDL to develop optimized hardware.

Apparatus: Logisim Software

POS Truth Table:

Table: 1

Procedure:
1. Click on Explorer Pane ➔ Gates ➔ Take AND, OR and NOT gate ➔ select the required gate drag and drop
the symbol on drawing window and change the number of inputs as per the circuit diagram on Attribute table
1 by following fig 1.

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 Fig 1

2. To take input click on this symbol on Toolbar

3. To take Output click on this symbol on Toolbar

POS Logic Diagram:

Fig 2

4. After designing the logic diagram as shown in fig 2, make the input High/Low click on the hand symbol
on Toolbar

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5. Apply various input combinations and observe output for each one.

6. Verify the truth table for each input/ output combination.

7. To convert the circuit into sub-circuit appearance as a IC follow the procedure as shown below.

8. Click on Tool bar and select Edit viewed circuit sub-circuit appearance as shown in Fig 2, then the circuit
converts as shown in Fig 3. Then save the converted circuit.

Fig 2

Fig 3
9. Now open new file go to untitled, right click on it ➔ Load Library ➔click on Logisim Library as shown in
Fig 4

Fig 4

10. The saved file will appear at the last of Explorer Pane, Click on main drag and drop the symbol on drawing
window.
11. Assign Inputs and Outputs as shown in Fig 5

21
 Fig 5

Similarly we can repeat the procedural steps for SOP as follows,

SOP TRUTH TABLE:

SOP Circuit Diagram:

22
SOP IC PIN DIAGRAM:

SOP IC CIRCUIT DIAGRAM:

Verilog Code: F (x, y, z) = Σm (3, 5, 6, 7)

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F (x, y, z) = x’yz+xy’z+xyz’+xyz
module ckt (x,y,z,a,b,c,d,e,f,g,h);
input x,y,z;
inout a,b,c,d,e,f,g;
output h;
not(a,x);
not(b,y);
not (c,z);
and(d,a,y,z);
and(e,x,b,z);
and(f,x,y,c);
and(g,x,y,z);
or(h,d,e,f,g);
endmodule

Exercise problem: Write Verilog code for the given function F (x, y, z) = πM (0, 1, 2, 4)

Result:

EXPERIMENT 6

24
Design logic circuit of 2-bit magnitude comparator and 4-bit parity generator and write Verilog HDL to
develop optimized hardware.

Aim: To design logic circuit of 2-bit magnitude comparator and 4-bit parity generator and write Verilog
HDL to develop optimized hardware.
Apparatus: Logisim Software

THEORY:

• 2-bit magnitude comparator:

The comparison of two numbers is an operation that determines one number is greater than,
less than (or) equal to the other number. A magnitude comparator is a combinational circuit
that compares two numbers A and B and determines their relative magnitude. The outcome of
the comparator is specified by three binary variables that indicate whether A>B, A=B (or)
A<B.

CIRCUIT DIAGRAM:

25
 TRUTH TABLE

THEORY:
• 4-bit parity generator:
A parity bit is used for detecting errors during transmission of binary information. A parity
bit is an extra bit included with a binary message to make the number is either even or odd. The
message including the parity bit is transmitted and then checked at the receiver ends for errors.
An error is detected if the checked parity bit doesn’t correspond to the one transmitted. The
circuit that generates the parity bit in the transmitter is called a ‘parity generator’ and the circuit
that checks the parity in the receiver is called a ‘parity checker’. In even parity, the added parity
bit will make the total number of one’s is even amount. In odd parity, the added parity bit will
make the total number of one’s is odd amount. The parity checker circuit checks for possible
errors in the transmission. If the information is passed in even parity, then the bits required must
have an even number of 1’s. An error occur during transmission, if the received bits have an
odd number of 1’s indicating that one bit has changed in value during transmission.
CIRCUIT DIAGRAM:

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TRUTH TABLE:

A B C P

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

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 Procedure:
1. Take AND,OR, NOT and EX-NOR gates ➔ click on Explorer Pane ➔ Gates ➔select the required gate drag
and drop the symbol on drawing window and change the number of inputs as per the circuit on Attribute table
as shown in fig 1

Fig 1
2. To take input click on this symbol on Toolbar

3. To take Output click on this symbol on Toolbar

2-bit magnitude comparator Logic Diagram:

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 FIG: 2-bit magnitude comparator

4. To make the input High/Low click on the hand symbol on Toolbar

5. Apply various input combinations and observe output for each one.

6. Verify the truth table for each input/ output combination.

7. To convert the circuit into subcircuit appearance as a IC follow the procedure as shown below.

8. Click on Tool bar and select Edit viewed circuit subcircuit appearance as shown in Fig 2, then the circuit
converts as shown in Fig 3. Then save the converted circuit.

Fig 2

29
 Fig 3

9. Now open new file go to untitled, right click on it ➔ Load Library ➔click on Logisim Library as shown in
Fig 4

Fig 4

10. The saved file will appear at the last of Explorer Pane, Click on main drag and drop the symbol on drawing
window.

11. Assign Inputs and Outputs as shown in Fig 5

Fig 5

4-BIT PARITY GENERATOR LOGIC DIAGRAM:

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4-BIT PARITY GENERATOR IC PIN DIAGRAM:

4-BIT PARITY GENERATOR IC CIRCUIT DIAGRAM:

31
Verilog code for 2 bit magnitude comparator

module comparator2Bit(
input wire[1:0] a, b,
output wire eq
);

wire[3:0] s;

assign s[0] = ~a[1] & ~a[0] & ~b[1] & ~b[0];

assign s[1] = ~a[1] & a[0] & ~b[1] & b[0];
assign s[2] = a[1] & ~a[0] & b[1] & ~b[0];
assign s[3] = a[1] & a[0] & b[1] & b[0];

assign eq = s[0] | s[1] | s[2] | s[3];

endmodule

Exercise problem: Wite Verilog code for 4 bit parity generator

Result:

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 EXPERIMENT – 7

Design logic circuit for 4-bit Binary to Gray and 1–bit memory element and write Verilog HDL to develop
optimized hardware

Aim: Design logic circuit for 4-bit Binary to Gray and 1–bit memory element and write Verilog HDL to
develop optimized hardware.

Apparatus: Logisim Software

THEORY:

• 4-bit binary to gray code convertor:

Gray Code is one of the most important codes. It is a non-weighted code which
belongs to a class of codes called minimum change codes. In this codes while traversing from
one step to another step, only one bit in the code group changes. In case of Gray Code two
adjacent code numbers differs from each other by only one bit.
The input to the 4-bit binary-to-Gray code converter circuit is a 4-bit binary and the
output is a 4-bit Gray code. There are 16 possible combinations of 4-bit binary input and all
of them are valid. Hence no don’t cares. The 4-bit binary and the corresponding Gray code
are shown in the conversion table

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CIRCUIT DIAGRAM:

CONVERSION TABLE:

34
BOOLEAN EXPRESSIONS:
. From the conversion table, we observe that the expression for the outputs G4,G3,G2 and
G1 are as follows:

THEORY:
• SR FLIP-FLOP: There are two inputs to the flip-flop defined as R and S. When I/Ps R = 0
and S = 0 then O/P remains unchanged. When I/Ps R = 0 and S = 1 the flip-flop is switches
to the stable state where O/P is 1 i.e. SET. The I/P condition is R = 1 and S = 0 the flip-flop
is switched to the stable state where O/P is 0 i.e. RESET. The I/P condition is R = 1 and S =
1 the flip-flop is switched to the stable state where O/P is forbidden.

• JK FLIP-FLOP: For purpose of counting, the JK flip-flop is the idea element to use. The
variable J and K are called control I/Ps because they determine what the flip- flop does when a
positive edge arrives. When J and K are both 0s, both AND gates are disabled and Q retains its
last value.

• D FLIP –FLOP: This kind of flip flop prevents the value of D from reaching the Q output
until clock pulses occur. When the clock is low, both AND gates are disabled D can change
value without affecting the value of Q. On the other hand, when the clock is high, both AND
gates are enabled. In this case, Q is forced to equal the value of D. When the clock again goes
low, Q retains or stores the last value of D. a D flip flop is a bistable circuit whose D input is
transferred to the output after a clock pulse is received.

• T FLIP-FLOP: The T or "toggle" flip-flop changes its output on each clock edge, giving an
output which is half the frequency of the signal to the T input. It is useful for constructing

35
 binary counters, frequency dividers, and general binary addition devices. It can be made from
a J-K flip-flop by tying both of its inputs high.

CIRCUIT DIAGRAM:

SR Flip Flop

D Flip Flop

JK Flip Flop:

36
T Flip Flop:

TRUTH TABLE:

SR FLIP FLOP:
Clock S R Qn+1
1 0 0 NO CH ANGE
1 0 1 0
1 1 0 1
1 1 1 ?

D FLIP FLOP:

clock D Qn+1
1 0 0
37
 1 1 1

JK FLIPFLOP

Clock J K Qn+1
1 0 0 NO CHANGE
1 0 1 0
1 1 0 1
1 1 1 Toggle

T FLIPFLOP

Clock T Qn+1
1 0 NO CHANGE
1 1 Qn ’

Truth table:

Procedure:

1. To take NOT and EXOR gate ➔ click on Explorer Pane ➔ Gates ➔select the required gate drag and
drop the symbol on drawing window and change the number of inputs as per the circuit on Attribute
table as shown in fig 1
38
 Fig 1

2. To take input click on this symbol on Toolbar

3. To take Output click on this symbol on Toolbar

39
4. To make the input High/Low click on the hand symbol on Toolbar

5. Apply various input combinations and observe output for each one.

6. Verify the truth table for each input/ output combination.

7. To convert the circuit into subcircuit appearance as a IC follow the procedure as shown below.

8. Click on Tool bar and select Edit viewed circuit subcircuit appearance as shown in Fig 2, then the circuit conv
as shown in Fig 3. Then save the converted circuit.

Fig 2

40
 Fig 3

9. Now open new file go to untitled, right click on it ➔ Load Library ➔click on Logisim Library as
shown in Fig 4

Fig 4

10. The saved file will appear at the last of Explorer Pane, Click on main drag and drop the symbol on
drawing window.

11. Assign Inputs and Outputs as shown in Fig 5

FIG 5

Verilog code for 4 bit binary to grey convertor

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module bin2gray
(input [3:0] bin, //binary input
output [3:0] G //gray code output
);

//xor gates.
assign G[3] = bin[3];
assign G[2] = bin[3] ^ bin[2];
assign G[1] = bin[2] ^ bin[1];
assign G[0] = bin[1] ^ bin[0];

endmodule

RESULT:

EXPERIMENT – 8
Design Full-Adder using Multiplexer and Decoder and write Verilog HDL to develop
optimized hardware.
42
Aim: Design Full-Adder using Multiplexer and Decoder and write Verilog HDL to develop
optimized hardware.

Apparatus: Logisim Software

Truth Table:

A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Procedure:
1. Take MUX ➔ click on Explorer Pane ➔ plexers ➔select multiplexer, drag and drop the symbol on
drawing window and change the number of inputs as per the circuit on Attribute table as shown in fig
1

43
 Fig 1

2. To take input click on this symbol on Toolbar

3. To take Output click on this symbol on Toolbar

Logic Diagrams:

44
4. To make the input High/Low click on the hand symbol on Toolbar

5. Apply various input combinations and observe output for each one.

6. Verify the truth table for each input/ output combination.

7. To convert the circuit into subcircuit appearance as a IC follow the procedure as shown below.

8. Click on Tool bar and select Edit viewed circuit subcircuit appearance as shown in Fig 2, then the circuit conv
as shown in Fig 3. Then save the converted circuit.

Fig 2

Fig 3
45
 9. Now open new file go to untitled, right click on it ➔ Load Library ➔click on Logisim Library as
shown in Fig 4

Fig 4

10. The saved file will appear at the last of Explorer Pane, Click on main drag and drop the symbol on
drawing window.

11. Assign Inputs and Outputs as shown in Fig 5

Fig:5

Decoder Truth Table:

46
 SUM CARRY A B C
0 0 0 0 0
1 0 0 0 1
1 0 0 1 0
0 1 0 1 1
1 0 1 0 0
0 1 1 0 1
0 1 1 1 0
1 1 1 1 1

Decoder logic Diagram:

DECODER IC PIN DIAGRAM:

47
DECODER IC CIRCUIT DIAGRAM:

Verilog Code for full adder

full_adder( A, B, Cin, S, Cout);

input wire A, B, Cin;

output reg S, Cout;

always @(A or B or Cin)

begin
S = A ^ B ^ Cin;
Cout = A&B | (A^B) & Cin;
end
endmodule

Result:

EXPERIMENT – 9
DIGITAL DISPLAY OF DEPARTMENT NAME
48
Aim: To design logic for displaying Department Name “ECE”.
Apparatus:
1) NI Multisim
2) 3-Seven Segment Display
Theory:

Digital decoder IC is a device that converts one digital format into another, and one of the
most commonly-used device for doing this is the binary-coded decimal (BCD) to 7-segment
display decoder. The 7- segment light emitting diode (LED) provides a convenient way of
displaying information or digital data in the form of numbers, letters and alphanumeric
characters.
Typically, 7-segment displays consist of seven same colored LEDs (called segments) within
a single display package. In order to display the correct character or number, the correct
combination of LED segments has to be illuminated. This Multisim demonstrates the
illumination of each segment by displaying hex values (0000 through FFFF) in decimal
form from 0 through 9 and A through F.
The standard 7-segment LED display has eight input connections, one for each LED
segment and one that acts as a common terminal or connection for all internal display
segments. Some displays also have an additional input pin for displaying a decimal point.

.
Figure 1.(A)Common cathode display (B)Common anode display

49
 7-Segment Display Format

Figure 2: Seven Segment Display

Truth Table for a 7-segment display

Individual Segments Individual Segments

Display Display

f f
a b c D e g A b c d e g

× × × × × × 0 × × × × × × × 8

× × 1 × × × × × × 9

× × × × × 2 × × × × × × A

× × × × × 3 × × × × × b

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 × × × × 4 × × × × C

× × × × × 5 × × × × × d

× × × × × × 6 × × × × × E

× × × 7 × × × × F

Figure 3: 7-Segment Display Elements for all Numbers.

It can be seen that to display any single digit number from 0 to 9 in binary or letters from A to F
in hexadecimal, we would require 7 separate segment connections plus one additional connection
for the LED’s “common” connection

Binary Coded Decimal

Binary Coded Decimal (BCD or “8421” BCD) numbers are made up using just

4 data bits (a nibble or half a byte) similar to the Hexadecimal numbers we saw in the binary tutorial,
but unlike hexadecimal numbers that range in full from 0 through to F, BCD numbers only range
from 0 to 9, with the binary number patterns of 1010 through to 1111 (A to F) being invalid inputs
for this type of display and so are not used as shown below.

51
 Binary Binary
Decimal Pattern BCD Decimal Pattern BCD

8 4 2 1 8 4 2 1

0 0 0 0 0 0 8 1 0 0 0 8

1 0 0 0 1 1 9 1 0 0 1 9

2 0 0 1 0 2 10 1 0 1 0 Invalid

3 0 0 1 1 3 11 1 0 1 1 Invalid

4 0 1 0 0 4 12 1 1 0 0 Invalid

5 0 1 0 1 5 13 1 1 0 1 Invalid

6 0 1 1 0 6 14 1 1 1 0 Invalid

7 0 1 1 1 7 15 1 1 1 1 Invalid

52
BCD to 7-Segment Display Decoders

A binary coded decimal (BCD) to 7-segment display decoder such as the TTL

74LS47 or 74LS48, have 4 BCD inputs and 7 output lines, one for each LED segment. This allows
a smaller 4-bit binary number (half a byte) to be used to display all the denary numbers from 0 to
9 and by adding two displays together; a full range of numbers from 00 to 99 can be displayed
with just a single byte of 8 data bits.

BCD to 7-Segment Decoder

Procedure:

1. Open NIMultisim,then choose My DAQ

2. Create New File- Blank- NI My DAQ icon, then select design

53
 3. Create template, select only DIO inputs for connections

4. Place component, Select segment display

5. Make connections in the NI-Multisim

6. Execute the circuit and verify with truth table.

Figure 3: Simulated image of the displaying “department name- ECE”

Result:

1. Implemented department name on digital display using NI Multisim and verified

using truth table.
2. Learnt encode decimal numbers into 7 Segment display.

3.Understand the interfacing techniques and data acquisition using NI Multisim

54
 EXPERIMENT – 10
Design logic circuits of 3-bit shift registers using D flip-flops and write Verilog HDL
to develop optimized hardware.

Aim: Design logic circuits of 3-bit shift registers using D flip-flops and write Verilog HDL to develop
optimized hardware.

Apparatus: Logisim Software

SIPO Truth table:

CLK SI

X X 0 0 0 1

1 1 1 0 0 0

2 0 0 1 0 0

3 1 1 0 1 0

4 1 1 1 0 1

Procedure:
1. To take D Flipflop➔ click on Explorer Pane ➔ Memory ➔select D Flipflop, drag and drop
the symbol on drawing window as shown in fig 1

55
 Fig 1

2. To take input click on this symbol on Toolbar

3. To take Output click on this symbol on Toolbar

SIPO Logic Diagram:

4. To make the input High/Low click on the hand symbol on Toolbar

5. Apply various input combinations and observe output for each one.

6. Verify the truth table for each input/ output combination.

7. To convert the circuit into subcircuit appearance as a IC follow the procedure as shown below.
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8. Click on Tool bar and select Edit viewed circuit subcircuit appearance as shown in Fig 2, then the circuit
converts as shown in Fig 3. Then save the converted circuit.
 Fig 2

Fig 3

9. Now open new file go to untitled, right click on it ➔ Load Library ➔click on Logisim Library
as shown in Fig 4

Fig 4

10. The saved file will appear at the last of Explorer Pane, Click on main drag and drop the
symbol on drawing window.

11. Assign Inputs and Outputs as shown in Fig 5

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 Fig:5

PISO Logic Diagram:

PISO TRUTH TABLE:

CLK
X 0 0 0 1
1 1 1 0 1
2 0 1 1 0
3 0 0 1 1
4 0 0 0 1
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PISO IC PIN DIAGRAM:
PISO IC CIRCUIT DIAGRAM:

Verlog code

module shiftReg4(
input shift_in,
input clock,
output shift_out
);
reg bit0;
reg bit1;
reg bit2;
reg bit3;

assign shift_out = bit3;

always @(posedge clock) begin

bit3 <= bit2;
bit2 <= bit1;
bit1 <= bit0;
bit0 <= shift_in;
end

endmodule

Result:
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EXPERIMENT – 11
Design logic circuit of 3-bit Up-down counter using JK flip-flops and write Verilog
HDL to develop optimized hardware.

Aim: Design logic circuit of 3-bit Up-down counter using JK flip-flops and write Verilog HDL to
develop optimized hardware.

Apparatus: Logisim Software

TRUTH TABLE:

COUNT UP MODE COUNT DOWN MODE

CLK ENABLE STATE Q2 Q1 Q0 ENABLE STATE Q2 Q1 Q0
1 1 0 0 0 0 0 7 1 1 1
1 1 1 0 0 1 0 6 1 1 0
1 1 2 0 1 0 0 5 1 0 1
1 1 3 0 1 1 0 4 1 0 0
1 1 4 1 0 0 0 3 0 1 1
1 1 5 1 0 1 0 2 0 1 0
1 1 6 1 1 0 0 1 0 0 1
1 1 7 1 1 1 0 0 0 0 0

Procedure:
1. To take MUX ➔ click on Explorer Pane ➔ plexers ➔select multiplexer, drag and drop the
symbol on drawing window and change the number of inputs as per the circuit on Attribute
table as shown in fig 1

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 Fig 1
1. To take input click on this symbol on Toolbar

2. To take Output click on this symbol on Toolbar

LOGIC DIAGRAM:

3. To make the input High/Low click on the hand symbol on Toolbar

4. Apply various input combinations and observe output for each one.

5. Verify the truth table for each input/ output combination.

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6. To convert the circuit into subcircuit appearance as a IC follow the procedure as shown below.
7. Click on Tool bar and select Edit viewed circuit subcircuit appearance as shown in Fig 2, then the circuit
converts as shown in Fig 3. Then save the converted circuit.

Fig 2

Fig 3

8. Now open new file go to untitled, right click on it ➔ Load Library ➔click on Logisim Library
as shown in Fig 4

Fig 4

9. The saved file will appear at the last of Explorer Pane, Click on main drag and drop the
symbol on drawing window.

10. Assign Inputs and Outputs as shown in Fig 5

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 Fig:5
Verilog code
module counter (C, CLR, UP_DOWN, Q);
input C, CLR, UP_DOWN;
output [2:0] Q;
reg [2:0] tmp;

always @(posedge C or posedge CLR)

begin
if (CLR)
tmp = 3'b000;
else
if (UP_DOWN)
tmp = tmp + 1'b1;
else
tmp = tmp - 1'b1;
end
assign Q = tmp;
endmodule

RESULT:

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 EXPERIMENT – 12

Design PROM, PAL, PLA and LUT logic blocks for given Boolean functions
S=A’B+AB’ and C=A’B and write Verilog HDL to develop optimized hardware.

Aim: Design PROM, PAL, PLA and LUT logic blocks for given Boolean functions and write Verilog
HDL

Apparatus: DSCH CAD TOOL

Procedure:

1. Open the DSCH by double clicking it located in the installed directory of Dsch.
2. Select the foundry using the command File > Select Foundry
3. Save the design as “Lab 12” using File > Save as
4. Open a schematic design using the command Insert > Another Schema (.SCH)
5. Check for different input combinations by using mouse click on the inputs buttons to be on or off.
6. Now we will make the above schematics manually. Delete the existing diagram by selecting the
Cut command button from the icon menu bar and then select the whole diagram.
7. Save the design
8. Explore the Schema to new symbol, Make Verilog File, Generate Spice netlist in the File menu,
delays of each symbol and the Advanced Tab in the symbol library

Logic Diagram:

PROM schematic

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PAL design:

65
PLA design:

66
LUT design:

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Verilog code:
Design a BOOLEAN_LOGIC in Verilog in Dataflow style of modelling:
module boolean_Logic (input a, b, output s, c);
assign s = a ^ b;
assign c = a & b;
endmodule

Design BOOLEAN_LOGIC in Verilog in structural style of modelling:

module xor1(input a, b, output s);
xor (s, a, b);
endmodule
module and1(input a, b, output c);
and (c, a, b);
endmodule
module boolean_Logic (input a, b, output s, c);
xor1 u1(a, b, s);
and1 u2(a, b, c);
endmodule

Result:
Verified PROM, PAL, PLA and LUT logic blocks for given Boolean functions S=A’B+AB’ and C=A’B
and write Verilog HDL to develop optimized hardware.

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EXPERIMENT 13
Design Half Adder CPLD-Macrocell and FPGA-CLB and write Verilog
HDL to develop optimized hardware.

Aim: To design Half Adder CPLD-Macrocell and FPGA-CLB and write Verilog HDL and develop
optimized hardware.

Apparatus: DSCH CAD TOOL

Procedure:

1. Open the DSCH by double clicking it located in the installed directory of Dsch.
2. Select the foundry using the command File > Select Foundry
3. Save the design as “Lab 12” using File > Save as
4. Open a schematic design using the command Insert > Another Schema (.SCH)
5. Check for different input combinations by using mouse click on the inputs buttons to be on or off.
6. Now we will make the above schematics manually. Delete the existing diagram by selecting the
Cut command button from the icon menu bar and then select the whole diagram.
7. Save the design
8. Explore the Schema to new symbol, Make Verilog File, Generate Spice netlist in the File menu,
delays of each symbol and the Advanced Tab in the symbol library

Logic Diagram:
CPLD MACRO-CELL

CPLD MACRO-CELL
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HALF-ADDER CLB

HALF-ADDER
70
CLB
Verilog code:

HALF ADDER in Verilog in behavioural style of modelling using if-else statement:

module half adder (input x, y, output reg s, c);

always@(x or y)
begin
if (x == 0 && y == 0)
begin
s = 0; c = 0;
end
else if (x == 1 && y == 1)
begin
s = 0; c = 1;
end
else
begin
s = 1; c = 0;
end
end
endmodule
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HALF ADDER in Verilog in gatelevel style of modelling:

module half_adder (a,b,s,c);

input a,b;
output s,c;
xor(s,a,b);
and(c,a,b);
endmodule

output:

Result:

Designed Half Adder CPLD-Macrocell and FPGA-CLB and developed optimized hardware.

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